Patch Set 8:

Still wondering about my question in patch set #5 below?

Line 80:
Sorry, updating the last comment. Is PCIe port 3 being used for testing at the moment? if that's the case, then can we not commit the changes for now? This is not consistent with the current schematics.

I have changed from PCIe port 3 to PCIe port 8 in patch set #8. But this is just reserved and not being used at the moment. I will remove it in next patch.

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