[coreboot-gerrit] Change in coreboot[master]: mb/google/hatch: modify PCIe ports setting for mushu

[Amanda Hwang (Code Review)]

Amanda Hwang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38399 )

Change subject: mb/google/hatch: modify PCIe ports setting for mushu
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mb/google/hatch: modify PCIe ports setting for mushu

1. Enabled PCIe port for dGPU
2. Change WLAN PCIe port from port 14 to prot 7
3. Enabled PCIe port for GPU REFCLK

BUG=b:147249494
TEST=Ensure dGPU and WLAN shows up with lspci.

Change-Id: Iea3292be7d8029c35847118228bbb773418632a1
---
M src/mainboard/google/hatch/variants/mushu/overridetree.cb
1 file changed, 22 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/38399/1

diff --git a/src/mainboard/google/hatch/variants/mushu/overridetree.cb b/src/mainboard/google/hatch/variants/mushu/overridetree.cb
index c623fde..c584515 100644
--- a/src/mainboard/google/hatch/variants/mushu/overridetree.cb
+++ b/src/mainboard/google/hatch/variants/mushu/overridetree.cb
@@ -63,6 +63,28 @@
    		.fall_time_ns = 120,
    	},
    }"
+	
+	# Enable Root port 13(x4) for dGPU.
+	register "PcieRpEnable[12]" = "1"
+	register "PcieRpLtrEnable[12]" = "1"
+	# RP 13 uses CLK SRC 5
+	register "PcieClkSrcUsage[5]" = "12"
+	# ClkReq-to-ClkSrc mapping for CLK SRC 5
+	register "PcieClkSrcClkReq[5]" = "5"
+	
+	# PCIe port 3 reserve for GPU REFCLK
+	register "PcieRpEnable[2]" = "1"
+	register "PcieRpLtrEnable[2]" = "1"
+	# RP 3 uses CLK SRC 2
+	register "PcieClkSrcUsage[2]" = "2"
+	register "PcieClkSrcClkReq[2]" = "2"
+	
+	# PCIe port 7 for M.2 E-key WLAN
+	register "PcieRpEnable[6]" = "1"
+	register "PcieRpLtrEnable[6]" = "1"
+	# RP 7 uses CLK SRC 3
+	register "PcieClkSrcUsage[3]" = "6"
+	register "PcieClkSrcClkReq[3]" = "3"

# GPIO for SD card detect
    register "sdcard_cd_gpio" = "vSD3_CD_B"