[coreboot-gerrit] Change in coreboot[master]: mb/google/hatch/variants/mushu: modify PCIe ports setting

[Shelley Chen (Code Review)]

Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38399 )

Change subject: mb/google/hatch/variants/mushu: modify PCIe ports setting
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Patch Set 5:

(2 comments)

https://review.coreboot.org/c/coreboot/+/38399/5/src/mainboard/google/hatch/... 
File src/mainboard/google/hatch/variants/mushu/overridetree.cb:

https://review.coreboot.org/c/coreboot/+/38399/5/src/mainboard/google/hatch/... 
PS5, Line 75: 	# PCIe port 3 reserve for GPU REFCLK
            : 	register "PcieRpEnable[2]" = "1"
            : 	register "PcieRpLtrEnable[2]" = "
PCIE#3 seems to be connected to test points?

How is this connected to the GPU REFCLK?

https://review.coreboot.org/c/coreboot/+/38399/5/src/mainboard/google/hatch/... 
PS5, Line 80: 2
This should be 4 according to my discussion with shanthi.