Change in coreboot[master]: src/*: Make PCI ID macro names shorter

[Felix Singer (Code Review)]

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39331 )

Change subject: src/*: Make PCI ID macro names shorter
......................................................................

src/*: Make PCI ID macro names shorter

This patch shortens macro names containing PCI_{DEVICE,VENDOR}_ID_
with PCI_{DID,VID}_.

Used commands:
find -type f -exec sed -i 's/PCI_DEVICE_ID_/PCI_DID_/' {} ;
find -type f -exec sed -i 's/PCI_VENDOR_ID_/PCI_VID_/' {} ;

Signed-off-by: Felix Singer 
Change-Id: If9027700f53b6d0d3964c26a41a1f9b8f62be178
---
M src/device/pci_rom.c
M src/drivers/aspeed/ast2050/ast2050.c
M src/drivers/dec/21143/21143.c
M src/drivers/generic/bayhub/bh720.c
M src/drivers/intel/gma/opregion.c
M src/drivers/intel/i210/i210.c
M src/drivers/intel/ish/ish.c
M src/drivers/intel/wifi/wifi.c
M src/drivers/ricoh/rce822/rce822.c
M src/drivers/siemens/nc_fpga/nc_fpga.c
M src/drivers/xgi/common/XGI_main.h
M src/drivers/xgi/common/xgi_coreboot.c
M src/drivers/xgi/z9s/z9s.c
M src/include/device/pci_ids.h
M src/mainboard/google/poppy/variants/atlas/mainboard.c
M src/mainboard/google/poppy/variants/nocturne/mainboard.c
M src/mainboard/lenovo/x60/mainboard.c
M src/mainboard/siemens/mc_apl1/mainboard.c
M src/mainboard/siemens/mc_apl1/variants/mc_apl1/mainboard.c
M src/mainboard/siemens/mc_apl1/variants/mc_apl2/mainboard.c
M src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c
M src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c
M src/mainboard/siemens/mc_apl1/variants/mc_apl6/mainboard.c
M src/northbridge/amd/agesa/family14/northbridge.c
M src/northbridge/amd/agesa/family15tn/iommu.c
M src/northbridge/amd/agesa/family15tn/northbridge.c
M src/northbridge/amd/agesa/family16kb/northbridge.c
M src/northbridge/amd/pi/00630F01/iommu.c
M src/northbridge/amd/pi/00630F01/northbridge.c
M src/northbridge/amd/pi/00660F01/northbridge.c
M src/northbridge/amd/pi/00730F01/iommu.c
M src/northbridge/amd/pi/00730F01/northbridge.c
M src/northbridge/intel/gm45/gma.c
M src/northbridge/intel/haswell/gma.c
M src/northbridge/intel/haswell/minihd.c
M src/northbridge/intel/haswell/northbridge.c
M src/northbridge/intel/i440bx/northbridge.c
M src/northbridge/intel/i945/gma.c
M src/northbridge/intel/i945/northbridge.c
M src/northbridge/intel/nehalem/gma.c
M src/northbridge/intel/nehalem/nehalem.h
M src/northbridge/intel/nehalem/northbridge.c
M src/northbridge/intel/pineview/gma.c
M src/northbridge/intel/sandybridge/gma.c
M src/northbridge/intel/sandybridge/northbridge.c
M src/northbridge/intel/sandybridge/pcie.c
M src/northbridge/intel/x4x/gma.c
M src/soc/amd/common/block/hda/hda.c
M src/soc/amd/common/block/iommu/iommu.c
M src/soc/amd/common/block/lpc/lpc.c
M src/soc/amd/common/block/sata/sata.c
M src/soc/amd/common/block/smbus/sm.c
M src/soc/amd/picasso/acp.c
M src/soc/amd/picasso/northbridge.c
M src/soc/amd/picasso/usb.c
M src/soc/amd/stoneyridge/include/soc/pci_devs.h
M src/soc/amd/stoneyridge/northbridge.c
M src/soc/amd/stoneyridge/usb.c
M src/soc/cavium/common/pci/uart.c
M src/soc/intel/apollolake/report_platform.c
M src/soc/intel/baytrail/ehci.c
M src/soc/intel/baytrail/emmc.c
M src/soc/intel/baytrail/gfx.c
M src/soc/intel/baytrail/hda.c
M src/soc/intel/baytrail/lpe.c
M src/soc/intel/baytrail/lpss.c
M src/soc/intel/baytrail/northcluster.c
M src/soc/intel/baytrail/pcie.c
M src/soc/intel/baytrail/sata.c
M src/soc/intel/baytrail/sd.c
M src/soc/intel/baytrail/southcluster.c
M src/soc/intel/baytrail/xhci.c
M src/soc/intel/braswell/emmc.c
M src/soc/intel/braswell/gfx.c
M src/soc/intel/braswell/lpe.c
M src/soc/intel/braswell/lpss.c
M src/soc/intel/braswell/northcluster.c
M src/soc/intel/braswell/pcie.c
M src/soc/intel/braswell/sata.c
M src/soc/intel/braswell/sd.c
M src/soc/intel/braswell/southcluster.c
M src/soc/intel/braswell/xhci.c
M src/soc/intel/broadwell/adsp.c
M src/soc/intel/broadwell/ehci.c
M src/soc/intel/broadwell/hda.c
M src/soc/intel/broadwell/igd.c
M src/soc/intel/broadwell/lpc.c
M src/soc/intel/broadwell/me.c
M src/soc/intel/broadwell/minihd.c
M src/soc/intel/broadwell/pcie.c
M src/soc/intel/broadwell/sata.c
M src/soc/intel/broadwell/serialio.c
M src/soc/intel/broadwell/smbus.c
M src/soc/intel/broadwell/systemagent.c
M src/soc/intel/broadwell/xhci.c
M src/soc/intel/cannonlake/bootblock/report_platform.c
M src/soc/intel/cannonlake/vr_config.c
M src/soc/intel/common/block/cse/cse.c
M src/soc/intel/common/block/dsp/dsp.c
M src/soc/intel/common/block/graphics/graphics.c
M src/soc/intel/common/block/hda/hda.c
M src/soc/intel/common/block/i2c/i2c.c
M src/soc/intel/common/block/lpc/lpc.c
M src/soc/intel/common/block/p2sb/p2sb.c
M src/soc/intel/common/block/pcie/pcie.c
M src/soc/intel/common/block/pmc/pmc.c
M src/soc/intel/common/block/sata/sata.c
M src/soc/intel/common/block/scs/mmc.c
M src/soc/intel/common/block/scs/sd.c
M src/soc/intel/common/block/smbus/smbus.c
M src/soc/intel/common/block/spi/spi.c
M src/soc/intel/common/block/sram/sram.c
M src/soc/intel/common/block/systemagent/systemagent.c
M src/soc/intel/common/block/uart/uart.c
M src/soc/intel/common/block/xdci/xdci.c
M src/soc/intel/common/block/xhci/xhci.c
M src/soc/intel/denverton_ns/csme_ie_kt.c
M src/soc/intel/denverton_ns/lpc.c
M src/soc/intel/denverton_ns/npk.c
M src/soc/intel/denverton_ns/pmc.c
M src/soc/intel/denverton_ns/sata.c
M src/soc/intel/denverton_ns/systemagent.c
M src/soc/intel/denverton_ns/uart.c
M src/soc/intel/denverton_ns/xhci.c
M src/soc/intel/icelake/bootblock/report_platform.c
M src/soc/intel/quark/ehci.c
M src/soc/intel/quark/gpio_i2c.c
M src/soc/intel/quark/lpc.c
M src/soc/intel/quark/northcluster.c
M src/soc/intel/quark/sd.c
M src/soc/intel/quark/spi.c
M src/soc/intel/quark/uart.c
M src/soc/intel/skylake/bootblock/report_platform.c
M src/soc/intel/skylake/vr_config.c
M src/soc/intel/tigerlake/bootblock/report_platform.c
M src/southbridge/amd/agesa/hudson/hda.c
M src/southbridge/amd/agesa/hudson/hudson.c
M src/southbridge/amd/agesa/hudson/ide.c
M src/southbridge/amd/agesa/hudson/lpc.c
M src/southbridge/amd/agesa/hudson/pci.c
M src/southbridge/amd/agesa/hudson/pcie.c
M src/southbridge/amd/agesa/hudson/sata.c
M src/southbridge/amd/agesa/hudson/sd.c
M src/southbridge/amd/agesa/hudson/sm.c
M src/southbridge/amd/agesa/hudson/usb.c
M src/southbridge/amd/cimx/sb800/late.c
M src/southbridge/amd/pi/hudson/hda.c
M src/southbridge/amd/pi/hudson/hudson.c
M src/southbridge/amd/pi/hudson/ide.c
M src/southbridge/amd/pi/hudson/lpc.c
M src/southbridge/amd/pi/hudson/pci.c
M src/southbridge/amd/pi/hudson/pcie.c
M src/southbridge/amd/pi/hudson/sata.c
M src/southbridge/amd/pi/hudson/sd.c
M src/southbridge/amd/pi/hudson/sm.c
M src/southbridge/amd/pi/hudson/usb.c
M src/southbridge/intel/bd82x6x/azalia.c
M src/southbridge/intel/bd82x6x/lpc.c
M src/southbridge/intel/bd82x6x/me.c
M src/southbridge/intel/bd82x6x/me_8.x.c
M src/southbridge/intel/bd82x6x/pci.c
M src/southbridge/intel/bd82x6x/pcie.c
M src/southbridge/intel/bd82x6x/sata.c
M src/southbridge/intel/bd82x6x/smbus.c
M src/southbridge/intel/bd82x6x/usb_ehci.c
M src/southbridge/intel/bd82x6x/usb_xhci.c
M src/southbridge/intel/i82371eb/bootblock.c
M src/southbridge/intel/i82371eb/early_pm.c
M src/southbridge/intel/i82371eb/early_smbus.c
M src/southbridge/intel/i82371eb/ide.c
M src/southbridge/intel/i82371eb/isa.c
M src/southbridge/intel/i82371eb/smbus.c
M src/southbridge/intel/i82371eb/usb.c
M src/southbridge/intel/i82801dx/ac97.c
M src/southbridge/intel/i82801dx/ide.c
M src/southbridge/intel/i82801dx/lpc.c
M src/southbridge/intel/i82801dx/pci.c
M src/southbridge/intel/i82801dx/usb.c
M src/southbridge/intel/i82801dx/usb2.c
M src/southbridge/intel/i82801gx/ac97.c
M src/southbridge/intel/i82801gx/azalia.c
M src/southbridge/intel/i82801gx/ide.c
M src/southbridge/intel/i82801gx/lpc.c
M src/southbridge/intel/i82801gx/nic.c
M src/southbridge/intel/i82801gx/pci.c
M src/southbridge/intel/i82801gx/pcie.c
M src/southbridge/intel/i82801gx/sata.c
M src/southbridge/intel/i82801gx/smbus.c
M src/southbridge/intel/i82801gx/usb.c
M src/southbridge/intel/i82801gx/usb_ehci.c
M src/southbridge/intel/i82801ix/early_smbus.c
M src/southbridge/intel/i82801ix/hdaudio.c
M src/southbridge/intel/i82801ix/lpc.c
M src/southbridge/intel/i82801ix/pci.c
M src/southbridge/intel/i82801ix/pcie.c
M src/southbridge/intel/i82801ix/sata.c
M src/southbridge/intel/i82801ix/smbus.c
M src/southbridge/intel/i82801ix/thermal.c
M src/southbridge/intel/i82801ix/usb_ehci.c
M src/southbridge/intel/i82801jx/hdaudio.c
M src/southbridge/intel/i82801jx/lpc.c
M src/southbridge/intel/i82801jx/pci.c
M src/southbridge/intel/i82801jx/pcie.c
M src/southbridge/intel/i82801jx/sata.c
M src/southbridge/intel/i82801jx/smbus.c
M src/southbridge/intel/i82801jx/thermal.c
M src/southbridge/intel/i82801jx/usb_ehci.c
M src/southbridge/intel/i82870/ioapic.c
M src/southbridge/intel/i82870/pcibridge.c
M src/southbridge/intel/ibexpeak/azalia.c
M src/southbridge/intel/ibexpeak/lpc.c
M src/southbridge/intel/ibexpeak/me.c
M src/southbridge/intel/ibexpeak/sata.c
M src/southbridge/intel/ibexpeak/smbus.c
M src/southbridge/intel/ibexpeak/thermal.c
M src/southbridge/intel/ibexpeak/usb_ehci.c
M src/southbridge/intel/lynxpoint/azalia.c
M src/southbridge/intel/lynxpoint/lpc.c
M src/southbridge/intel/lynxpoint/me_9.x.c
M src/southbridge/intel/lynxpoint/pcie.c
M src/southbridge/intel/lynxpoint/sata.c
M src/southbridge/intel/lynxpoint/serialio.c
M src/southbridge/intel/lynxpoint/smbus.c
M src/southbridge/intel/lynxpoint/usb_ehci.c
M src/southbridge/intel/lynxpoint/usb_xhci.c
M src/southbridge/ricoh/rl5c476/rl5c476.c
M src/southbridge/ti/pci1x2x/pci1x2x.c
M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Pci22.h
228 files changed, 4,921 insertions(+), 4,921 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/39331/1

[build bot (Jenkins) (Code Review)]

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39331 )

Change subject: src/*: Make PCI ID macro names shorter
......................................................................

Patch Set 1:

(6 comments)

https://review.coreboot.org/c/coreboot/+/39331/1/src/include/device/pci_ids.... 
File src/include/device/pci_ids.h:

https://review.coreboot.org/c/coreboot/+/39331/1/src/include/device/pci_ids.... 
PS1, Line 2044: #define PCI_VID_AKS		0x416c
'AKS' may be misspelled - perhaps 'ASK'?

https://review.coreboot.org/c/coreboot/+/39331/1/src/include/device/pci_ids.... 
PS1, Line 2045: #define PCI_DID_AKS_ALADDINCARD	0x0100
'AKS' may be misspelled - perhaps 'ASK'?

https://review.coreboot.org/c/coreboot/+/39331/1/src/include/device/pci_ids.... 
PS1, Line 2046: #define PCI_DID_AKS_CPC		0x0200
'AKS' may be misspelled - perhaps 'ASK'?

https://review.coreboot.org/c/coreboot/+/39331/1/src/soc/intel/skylake/vr_co... 
File src/soc/intel/skylake/vr_config.c:

https://review.coreboot.org/c/coreboot/+/39331/1/src/soc/intel/skylake/vr_co... 
PS1, Line 229: 		         (igd_id == PCI_DID_INTEL_KBL_GT3E_SULTM_2)) {
code indent should use tabs where possible

https://review.coreboot.org/c/coreboot/+/39331/1/src/southbridge/amd/agesa/h... 
File src/southbridge/amd/agesa/hudson/hudson.c:

https://review.coreboot.org/c/coreboot/+/39331/1/src/southbridge/amd/agesa/h... 
PS1, Line 80: 			else if (sd_device_id == PCI_DID_AMD_YANGTZE_SD) {
else should follow close brace '}'

https://review.coreboot.org/c/coreboot/+/39331/1/src/southbridge/amd/pi/huds... 
File src/southbridge/amd/pi/hudson/hudson.c:

https://review.coreboot.org/c/coreboot/+/39331/1/src/southbridge/amd/pi/huds... 
PS1, Line 54: 			else if (sd_device_id == PCI_DID_AMD_YANGTZE_SD) {
else should follow close brace '}'

[Nico Huber (Code Review)]

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39331 )

Change subject: src/*: Make PCI ID macro names shorter
......................................................................

Patch Set 1: Code-Review+1

(2 comments)

Needs a little more work and somebody with a lot of time to re-align
the whole `pci_ids.h`. But generally: Kill the boilerplate!

https://review.coreboot.org/c/coreboot/+/39331/1//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/39331/1//COMMIT_MSG@14 
PS1, Line 14: ;
Could have used `+` instead of `;` ;) should be much faster.

https://review.coreboot.org/c/coreboot/+/39331/1//COMMIT_MSG@14 
PS1, Line 14: find -type f -exec sed -i 's/PCI_VENDOR_ID_/PCI_VID_/' {} ;
Missing `g` modifier for the substitution. There are some lines with
multiple occurence (probably unused, as Jenkins didn't complain).

[Felix Singer (Code Review)]

Hello build bot (Jenkins), Angel Pons, Arthur Heymans, Michael Niewöhner, Andrey Petrov, Patrick Rudolph, Nico Huber, Damien Zammit, David Guckian, Vanessa Eusebio, Alexander Couzens, Werner Zeh, Felix Held,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/39331

to look at the new patch set (#2).

Change subject: src/*: Make PCI ID macro names shorter
......................................................................

src/*: Make PCI ID macro names shorter

This patch shortens macro names containing PCI_{DEVICE,VENDOR}_ID_
with PCI_{DID,VID}_.

Used commands:
find -type f -exec sed -i 's/PCI_DEVICE_ID_/PCI_DID_/' {} +
find -type f -exec sed -i 's/PCI_VENDOR_ID_/PCI_VID_/' {} +

Signed-off-by: Felix Singer 
Change-Id: If9027700f53b6d0d3964c26a41a1f9b8f62be178
---
M src/device/pci_rom.c
M src/drivers/aspeed/ast2050/ast2050.c
M src/drivers/dec/21143/21143.c
M src/drivers/generic/bayhub/bh720.c
M src/drivers/intel/gma/opregion.c
M src/drivers/intel/i210/i210.c
M src/drivers/intel/ish/ish.c
M src/drivers/intel/wifi/wifi.c
M src/drivers/ricoh/rce822/rce822.c
M src/drivers/siemens/nc_fpga/nc_fpga.c
M src/drivers/xgi/common/XGI_main.h
M src/drivers/xgi/common/xgi_coreboot.c
M src/drivers/xgi/z9s/z9s.c
M src/include/device/pci_ids.h
M src/mainboard/google/poppy/variants/atlas/mainboard.c
M src/mainboard/google/poppy/variants/nocturne/mainboard.c
M src/mainboard/lenovo/x60/mainboard.c
M src/mainboard/siemens/mc_apl1/mainboard.c
M src/mainboard/siemens/mc_apl1/variants/mc_apl1/mainboard.c
M src/mainboard/siemens/mc_apl1/variants/mc_apl2/mainboard.c
M src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c
M src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c
M src/mainboard/siemens/mc_apl1/variants/mc_apl6/mainboard.c
M src/northbridge/amd/agesa/family14/northbridge.c
M src/northbridge/amd/agesa/family15tn/iommu.c
M src/northbridge/amd/agesa/family15tn/northbridge.c
M src/northbridge/amd/agesa/family16kb/northbridge.c
M src/northbridge/amd/pi/00630F01/iommu.c
M src/northbridge/amd/pi/00630F01/northbridge.c
M src/northbridge/amd/pi/00660F01/northbridge.c
M src/northbridge/amd/pi/00730F01/iommu.c
M src/northbridge/amd/pi/00730F01/northbridge.c
M src/northbridge/intel/gm45/gma.c
M src/northbridge/intel/haswell/gma.c
M src/northbridge/intel/haswell/minihd.c
M src/northbridge/intel/haswell/northbridge.c
M src/northbridge/intel/i440bx/northbridge.c
M src/northbridge/intel/i945/gma.c
M src/northbridge/intel/i945/northbridge.c
M src/northbridge/intel/nehalem/gma.c
M src/northbridge/intel/nehalem/nehalem.h
M src/northbridge/intel/nehalem/northbridge.c
M src/northbridge/intel/pineview/gma.c
M src/northbridge/intel/sandybridge/gma.c
M src/northbridge/intel/sandybridge/northbridge.c
M src/northbridge/intel/sandybridge/pcie.c
M src/northbridge/intel/x4x/gma.c
M src/soc/amd/common/block/hda/hda.c
M src/soc/amd/common/block/iommu/iommu.c
M src/soc/amd/common/block/lpc/lpc.c
M src/soc/amd/common/block/sata/sata.c
M src/soc/amd/common/block/smbus/sm.c
M src/soc/amd/picasso/acp.c
M src/soc/amd/picasso/northbridge.c
M src/soc/amd/picasso/usb.c
M src/soc/amd/stoneyridge/include/soc/pci_devs.h
M src/soc/amd/stoneyridge/northbridge.c
M src/soc/amd/stoneyridge/usb.c
M src/soc/cavium/common/pci/uart.c
M src/soc/intel/apollolake/report_platform.c
M src/soc/intel/baytrail/ehci.c
M src/soc/intel/baytrail/emmc.c
M src/soc/intel/baytrail/gfx.c
M src/soc/intel/baytrail/hda.c
M src/soc/intel/baytrail/lpe.c
M src/soc/intel/baytrail/lpss.c
M src/soc/intel/baytrail/northcluster.c
M src/soc/intel/baytrail/pcie.c
M src/soc/intel/baytrail/sata.c
M src/soc/intel/baytrail/sd.c
M src/soc/intel/baytrail/southcluster.c
M src/soc/intel/baytrail/xhci.c
M src/soc/intel/braswell/emmc.c
M src/soc/intel/braswell/gfx.c
M src/soc/intel/braswell/lpe.c
M src/soc/intel/braswell/lpss.c
M src/soc/intel/braswell/northcluster.c
M src/soc/intel/braswell/pcie.c
M src/soc/intel/braswell/sata.c
M src/soc/intel/braswell/sd.c
M src/soc/intel/braswell/southcluster.c
M src/soc/intel/braswell/xhci.c
M src/soc/intel/broadwell/adsp.c
M src/soc/intel/broadwell/ehci.c
M src/soc/intel/broadwell/hda.c
M src/soc/intel/broadwell/igd.c
M src/soc/intel/broadwell/lpc.c
M src/soc/intel/broadwell/me.c
M src/soc/intel/broadwell/minihd.c
M src/soc/intel/broadwell/pcie.c
M src/soc/intel/broadwell/sata.c
M src/soc/intel/broadwell/serialio.c
M src/soc/intel/broadwell/smbus.c
M src/soc/intel/broadwell/systemagent.c
M src/soc/intel/broadwell/xhci.c
M src/soc/intel/cannonlake/bootblock/report_platform.c
M src/soc/intel/cannonlake/vr_config.c
M src/soc/intel/common/block/cse/cse.c
M src/soc/intel/common/block/dsp/dsp.c
M src/soc/intel/common/block/graphics/graphics.c
M src/soc/intel/common/block/hda/hda.c
M src/soc/intel/common/block/i2c/i2c.c
M src/soc/intel/common/block/lpc/lpc.c
M src/soc/intel/common/block/p2sb/p2sb.c
M src/soc/intel/common/block/pcie/pcie.c
M src/soc/intel/common/block/pmc/pmc.c
M src/soc/intel/common/block/sata/sata.c
M src/soc/intel/common/block/scs/mmc.c
M src/soc/intel/common/block/scs/sd.c
M src/soc/intel/common/block/smbus/smbus.c
M src/soc/intel/common/block/spi/spi.c
M src/soc/intel/common/block/sram/sram.c
M src/soc/intel/common/block/systemagent/systemagent.c
M src/soc/intel/common/block/uart/uart.c
M src/soc/intel/common/block/xdci/xdci.c
M src/soc/intel/common/block/xhci/xhci.c
M src/soc/intel/denverton_ns/csme_ie_kt.c
M src/soc/intel/denverton_ns/lpc.c
M src/soc/intel/denverton_ns/npk.c
M src/soc/intel/denverton_ns/pmc.c
M src/soc/intel/denverton_ns/sata.c
M src/soc/intel/denverton_ns/systemagent.c
M src/soc/intel/denverton_ns/uart.c
M src/soc/intel/denverton_ns/xhci.c
M src/soc/intel/icelake/bootblock/report_platform.c
M src/soc/intel/quark/ehci.c
M src/soc/intel/quark/gpio_i2c.c
M src/soc/intel/quark/lpc.c
M src/soc/intel/quark/northcluster.c
M src/soc/intel/quark/sd.c
M src/soc/intel/quark/spi.c
M src/soc/intel/quark/uart.c
M src/soc/intel/skylake/bootblock/report_platform.c
M src/soc/intel/skylake/vr_config.c
M src/soc/intel/tigerlake/bootblock/report_platform.c
M src/southbridge/amd/agesa/hudson/hda.c
M src/southbridge/amd/agesa/hudson/hudson.c
M src/southbridge/amd/agesa/hudson/ide.c
M src/southbridge/amd/agesa/hudson/lpc.c
M src/southbridge/amd/agesa/hudson/pci.c
M src/southbridge/amd/agesa/hudson/pcie.c
M src/southbridge/amd/agesa/hudson/sata.c
M src/southbridge/amd/agesa/hudson/sd.c
M src/southbridge/amd/agesa/hudson/sm.c
M src/southbridge/amd/agesa/hudson/usb.c
M src/southbridge/amd/cimx/sb800/late.c
M src/southbridge/amd/pi/hudson/hda.c
M src/southbridge/amd/pi/hudson/hudson.c
M src/southbridge/amd/pi/hudson/ide.c
M src/southbridge/amd/pi/hudson/lpc.c
M src/southbridge/amd/pi/hudson/pci.c
M src/southbridge/amd/pi/hudson/pcie.c
M src/southbridge/amd/pi/hudson/sata.c
M src/southbridge/amd/pi/hudson/sd.c
M src/southbridge/amd/pi/hudson/sm.c
M src/southbridge/amd/pi/hudson/usb.c
M src/southbridge/intel/bd82x6x/azalia.c
M src/southbridge/intel/bd82x6x/lpc.c
M src/southbridge/intel/bd82x6x/me.c
M src/southbridge/intel/bd82x6x/me_8.x.c
M src/southbridge/intel/bd82x6x/pci.c
M src/southbridge/intel/bd82x6x/pcie.c
M src/southbridge/intel/bd82x6x/sata.c
M src/southbridge/intel/bd82x6x/smbus.c
M src/southbridge/intel/bd82x6x/usb_ehci.c
M src/southbridge/intel/bd82x6x/usb_xhci.c
M src/southbridge/intel/i82371eb/bootblock.c
M src/southbridge/intel/i82371eb/early_pm.c
M src/southbridge/intel/i82371eb/early_smbus.c
M src/southbridge/intel/i82371eb/ide.c
M src/southbridge/intel/i82371eb/isa.c
M src/southbridge/intel/i82371eb/smbus.c
M src/southbridge/intel/i82371eb/usb.c
M src/southbridge/intel/i82801dx/ac97.c
M src/southbridge/intel/i82801dx/ide.c
M src/southbridge/intel/i82801dx/lpc.c
M src/southbridge/intel/i82801dx/pci.c
M src/southbridge/intel/i82801dx/usb.c
M src/southbridge/intel/i82801dx/usb2.c
M src/southbridge/intel/i82801gx/ac97.c
M src/southbridge/intel/i82801gx/azalia.c
M src/southbridge/intel/i82801gx/ide.c
M src/southbridge/intel/i82801gx/lpc.c
M src/southbridge/intel/i82801gx/nic.c
M src/southbridge/intel/i82801gx/pci.c
M src/southbridge/intel/i82801gx/pcie.c
M src/southbridge/intel/i82801gx/sata.c
M src/southbridge/intel/i82801gx/smbus.c
M src/southbridge/intel/i82801gx/usb.c
M src/southbridge/intel/i82801gx/usb_ehci.c
M src/southbridge/intel/i82801ix/early_smbus.c
M src/southbridge/intel/i82801ix/hdaudio.c
M src/southbridge/intel/i82801ix/lpc.c
M src/southbridge/intel/i82801ix/pci.c
M src/southbridge/intel/i82801ix/pcie.c
M src/southbridge/intel/i82801ix/sata.c
M src/southbridge/intel/i82801ix/smbus.c
M src/southbridge/intel/i82801ix/thermal.c
M src/southbridge/intel/i82801ix/usb_ehci.c
M src/southbridge/intel/i82801jx/hdaudio.c
M src/southbridge/intel/i82801jx/lpc.c
M src/southbridge/intel/i82801jx/pci.c
M src/southbridge/intel/i82801jx/pcie.c
M src/southbridge/intel/i82801jx/sata.c
M src/southbridge/intel/i82801jx/smbus.c
M src/southbridge/intel/i82801jx/thermal.c
M src/southbridge/intel/i82801jx/usb_ehci.c
M src/southbridge/intel/i82870/ioapic.c
M src/southbridge/intel/i82870/pcibridge.c
M src/southbridge/intel/ibexpeak/azalia.c
M src/southbridge/intel/ibexpeak/lpc.c
M src/southbridge/intel/ibexpeak/me.c
M src/southbridge/intel/ibexpeak/sata.c
M src/southbridge/intel/ibexpeak/smbus.c
M src/southbridge/intel/ibexpeak/thermal.c
M src/southbridge/intel/ibexpeak/usb_ehci.c
M src/southbridge/intel/lynxpoint/azalia.c
M src/southbridge/intel/lynxpoint/lpc.c
M src/southbridge/intel/lynxpoint/me_9.x.c
M src/southbridge/intel/lynxpoint/pcie.c
M src/southbridge/intel/lynxpoint/sata.c
M src/southbridge/intel/lynxpoint/serialio.c
M src/southbridge/intel/lynxpoint/smbus.c
M src/southbridge/intel/lynxpoint/usb_ehci.c
M src/southbridge/intel/lynxpoint/usb_xhci.c
M src/southbridge/ricoh/rl5c476/rl5c476.c
M src/southbridge/ti/pci1x2x/pci1x2x.c
M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Pci22.h
228 files changed, 4,921 insertions(+), 4,921 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/39331/2

[build bot (Jenkins) (Code Review)]

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39331 )

Change subject: src/*: Make PCI ID macro names shorter
......................................................................

Patch Set 2:

(6 comments)

https://review.coreboot.org/c/coreboot/+/39331/2/src/include/device/pci_ids.... 
File src/include/device/pci_ids.h:

https://review.coreboot.org/c/coreboot/+/39331/2/src/include/device/pci_ids.... 
PS2, Line 2044: #define PCI_VID_AKS		0x416c
'AKS' may be misspelled - perhaps 'ASK'?

https://review.coreboot.org/c/coreboot/+/39331/2/src/include/device/pci_ids.... 
PS2, Line 2045: #define PCI_DID_AKS_ALADDINCARD	0x0100
'AKS' may be misspelled - perhaps 'ASK'?

https://review.coreboot.org/c/coreboot/+/39331/2/src/include/device/pci_ids.... 
PS2, Line 2046: #define PCI_DID_AKS_CPC		0x0200
'AKS' may be misspelled - perhaps 'ASK'?

https://review.coreboot.org/c/coreboot/+/39331/2/src/soc/intel/skylake/vr_co... 
File src/soc/intel/skylake/vr_config.c:

https://review.coreboot.org/c/coreboot/+/39331/2/src/soc/intel/skylake/vr_co... 
PS2, Line 229: 		         (igd_id == PCI_DID_INTEL_KBL_GT3E_SULTM_2)) {
code indent should use tabs where possible

https://review.coreboot.org/c/coreboot/+/39331/2/src/southbridge/amd/agesa/h... 
File src/southbridge/amd/agesa/hudson/hudson.c:

https://review.coreboot.org/c/coreboot/+/39331/2/src/southbridge/amd/agesa/h... 
PS2, Line 80: 			else if (sd_device_id == PCI_DID_AMD_YANGTZE_SD) {
else should follow close brace '}'

https://review.coreboot.org/c/coreboot/+/39331/2/src/southbridge/amd/pi/huds... 
File src/southbridge/amd/pi/hudson/hudson.c:

https://review.coreboot.org/c/coreboot/+/39331/2/src/southbridge/amd/pi/huds... 
PS2, Line 54: 			else if (sd_device_id == PCI_DID_AMD_YANGTZE_SD) {
else should follow close brace '}'

[Felix Singer (Code Review)]

Hello build bot (Jenkins), Angel Pons, Arthur Heymans, Michael Niewöhner, Andrey Petrov, Patrick Rudolph, Nico Huber, Damien Zammit, David Guckian, Vanessa Eusebio, Alexander Couzens, Werner Zeh, Felix Held,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/39331

to look at the new patch set (#3).

Change subject: src/*: Make PCI ID macro names shorter
......................................................................

src/*: Make PCI ID macro names shorter

This patch shortens macro names containing PCI_{DEVICE,VENDOR}_ID_
with PCI_{DID,VID}_.

Used commands:
find -type f -exec sed -i 's/PCI_DEVICE_ID_/PCI_DID_/' {} +
find -type f -exec sed -i 's/PCI_VENDOR_ID_/PCI_VID_/' {} +

Signed-off-by: Felix Singer 
Change-Id: If9027700f53b6d0d3964c26a41a1f9b8f62be178
---
M src/device/pci_rom.c
M src/drivers/aspeed/ast2050/ast2050.c
M src/drivers/broadcom/bcm57xx_aspm_disable.c
M src/drivers/dec/21143/21143.c
M src/drivers/generic/bayhub/bh720.c
M src/drivers/intel/gma/opregion.c
M src/drivers/intel/i210/i210.c
M src/drivers/intel/ish/ish.c
M src/drivers/intel/wifi/wifi.c
M src/drivers/ricoh/rce822/rce822.c
M src/drivers/siemens/nc_fpga/nc_fpga.c
M src/drivers/xgi/common/XGI_main.h
M src/drivers/xgi/common/xgi_coreboot.c
M src/drivers/xgi/z9s/z9s.c
M src/include/device/pci_ids.h
M src/mainboard/google/poppy/variants/atlas/mainboard.c
M src/mainboard/google/poppy/variants/nocturne/mainboard.c
M src/mainboard/lenovo/x60/mainboard.c
M src/mainboard/siemens/mc_apl1/mainboard.c
M src/mainboard/siemens/mc_apl1/variants/mc_apl1/mainboard.c
M src/mainboard/siemens/mc_apl1/variants/mc_apl2/mainboard.c
M src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c
M src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c
M src/mainboard/siemens/mc_apl1/variants/mc_apl6/mainboard.c
M src/northbridge/amd/agesa/family14/northbridge.c
M src/northbridge/amd/agesa/family15tn/iommu.c
M src/northbridge/amd/agesa/family15tn/northbridge.c
M src/northbridge/amd/agesa/family16kb/northbridge.c
M src/northbridge/amd/pi/00630F01/iommu.c
M src/northbridge/amd/pi/00630F01/northbridge.c
M src/northbridge/amd/pi/00660F01/northbridge.c
M src/northbridge/amd/pi/00730F01/iommu.c
M src/northbridge/amd/pi/00730F01/northbridge.c
M src/northbridge/intel/gm45/gma.c
M src/northbridge/intel/haswell/gma.c
M src/northbridge/intel/haswell/minihd.c
M src/northbridge/intel/haswell/northbridge.c
M src/northbridge/intel/haswell/pcie.c
M src/northbridge/intel/i440bx/northbridge.c
M src/northbridge/intel/i945/gma.c
M src/northbridge/intel/i945/northbridge.c
M src/northbridge/intel/nehalem/gma.c
M src/northbridge/intel/nehalem/nehalem.h
M src/northbridge/intel/nehalem/northbridge.c
M src/northbridge/intel/pineview/gma.c
M src/northbridge/intel/sandybridge/gma.c
M src/northbridge/intel/sandybridge/northbridge.c
M src/northbridge/intel/sandybridge/pcie.c
M src/northbridge/intel/x4x/gma.c
M src/soc/amd/common/block/hda/hda.c
M src/soc/amd/common/block/iommu/iommu.c
M src/soc/amd/common/block/lpc/lpc.c
M src/soc/amd/common/block/sata/sata.c
M src/soc/amd/common/block/smbus/sm.c
M src/soc/amd/picasso/acp.c
M src/soc/amd/picasso/northbridge.c
M src/soc/amd/picasso/usb.c
M src/soc/amd/stoneyridge/include/soc/pci_devs.h
M src/soc/amd/stoneyridge/northbridge.c
M src/soc/amd/stoneyridge/usb.c
M src/soc/cavium/common/pci/uart.c
M src/soc/intel/apollolake/report_platform.c
M src/soc/intel/baytrail/ehci.c
M src/soc/intel/baytrail/emmc.c
M src/soc/intel/baytrail/gfx.c
M src/soc/intel/baytrail/hda.c
M src/soc/intel/baytrail/lpe.c
M src/soc/intel/baytrail/lpss.c
M src/soc/intel/baytrail/northcluster.c
M src/soc/intel/baytrail/pcie.c
M src/soc/intel/baytrail/sata.c
M src/soc/intel/baytrail/sd.c
M src/soc/intel/baytrail/southcluster.c
M src/soc/intel/baytrail/xhci.c
M src/soc/intel/braswell/emmc.c
M src/soc/intel/braswell/gfx.c
M src/soc/intel/braswell/lpe.c
M src/soc/intel/braswell/lpss.c
M src/soc/intel/braswell/northcluster.c
M src/soc/intel/braswell/pcie.c
M src/soc/intel/braswell/sata.c
M src/soc/intel/braswell/sd.c
M src/soc/intel/braswell/southcluster.c
M src/soc/intel/braswell/xhci.c
M src/soc/intel/broadwell/adsp.c
M src/soc/intel/broadwell/ehci.c
M src/soc/intel/broadwell/hda.c
M src/soc/intel/broadwell/igd.c
M src/soc/intel/broadwell/lpc.c
M src/soc/intel/broadwell/me.c
M src/soc/intel/broadwell/minihd.c
M src/soc/intel/broadwell/pcie.c
M src/soc/intel/broadwell/sata.c
M src/soc/intel/broadwell/serialio.c
M src/soc/intel/broadwell/smbus.c
M src/soc/intel/broadwell/systemagent.c
M src/soc/intel/broadwell/xhci.c
M src/soc/intel/cannonlake/bootblock/report_platform.c
M src/soc/intel/cannonlake/vr_config.c
M src/soc/intel/common/block/cse/cse.c
M src/soc/intel/common/block/dsp/dsp.c
M src/soc/intel/common/block/graphics/graphics.c
M src/soc/intel/common/block/hda/hda.c
M src/soc/intel/common/block/i2c/i2c.c
M src/soc/intel/common/block/lpc/lpc.c
M src/soc/intel/common/block/p2sb/p2sb.c
M src/soc/intel/common/block/pcie/pcie.c
M src/soc/intel/common/block/pmc/pmc.c
M src/soc/intel/common/block/sata/sata.c
M src/soc/intel/common/block/scs/mmc.c
M src/soc/intel/common/block/scs/sd.c
M src/soc/intel/common/block/smbus/smbus.c
M src/soc/intel/common/block/spi/spi.c
M src/soc/intel/common/block/sram/sram.c
M src/soc/intel/common/block/systemagent/systemagent.c
M src/soc/intel/common/block/uart/uart.c
M src/soc/intel/common/block/xdci/xdci.c
M src/soc/intel/common/block/xhci/xhci.c
M src/soc/intel/denverton_ns/csme_ie_kt.c
M src/soc/intel/denverton_ns/lpc.c
M src/soc/intel/denverton_ns/npk.c
M src/soc/intel/denverton_ns/pmc.c
M src/soc/intel/denverton_ns/sata.c
M src/soc/intel/denverton_ns/systemagent.c
M src/soc/intel/denverton_ns/uart.c
M src/soc/intel/denverton_ns/xhci.c
M src/soc/intel/icelake/bootblock/report_platform.c
M src/soc/intel/quark/ehci.c
M src/soc/intel/quark/gpio_i2c.c
M src/soc/intel/quark/lpc.c
M src/soc/intel/quark/northcluster.c
M src/soc/intel/quark/sd.c
M src/soc/intel/quark/spi.c
M src/soc/intel/quark/uart.c
M src/soc/intel/skylake/bootblock/report_platform.c
M src/soc/intel/skylake/vr_config.c
M src/soc/intel/tigerlake/bootblock/report_platform.c
M src/soc/intel/xeon_sp/uncore.c
M src/southbridge/amd/agesa/hudson/hda.c
M src/southbridge/amd/agesa/hudson/hudson.c
M src/southbridge/amd/agesa/hudson/ide.c
M src/southbridge/amd/agesa/hudson/lpc.c
M src/southbridge/amd/agesa/hudson/pci.c
M src/southbridge/amd/agesa/hudson/pcie.c
M src/southbridge/amd/agesa/hudson/sata.c
M src/southbridge/amd/agesa/hudson/sd.c
M src/southbridge/amd/agesa/hudson/sm.c
M src/southbridge/amd/agesa/hudson/usb.c
M src/southbridge/amd/cimx/sb800/late.c
M src/southbridge/amd/pi/hudson/hda.c
M src/southbridge/amd/pi/hudson/hudson.c
M src/southbridge/amd/pi/hudson/ide.c
M src/southbridge/amd/pi/hudson/lpc.c
M src/southbridge/amd/pi/hudson/pci.c
M src/southbridge/amd/pi/hudson/pcie.c
M src/southbridge/amd/pi/hudson/sata.c
M src/southbridge/amd/pi/hudson/sd.c
M src/southbridge/amd/pi/hudson/sm.c
M src/southbridge/amd/pi/hudson/usb.c
M src/southbridge/intel/bd82x6x/azalia.c
M src/southbridge/intel/bd82x6x/lpc.c
M src/southbridge/intel/bd82x6x/me.c
M src/southbridge/intel/bd82x6x/me_8.x.c
M src/southbridge/intel/bd82x6x/pci.c
M src/southbridge/intel/bd82x6x/pcie.c
M src/southbridge/intel/bd82x6x/sata.c
M src/southbridge/intel/bd82x6x/smbus.c
M src/southbridge/intel/bd82x6x/usb_ehci.c
M src/southbridge/intel/bd82x6x/usb_xhci.c
M src/southbridge/intel/i82371eb/bootblock.c
M src/southbridge/intel/i82371eb/early_pm.c
M src/southbridge/intel/i82371eb/early_smbus.c
M src/southbridge/intel/i82371eb/ide.c
M src/southbridge/intel/i82371eb/isa.c
M src/southbridge/intel/i82371eb/smbus.c
M src/southbridge/intel/i82371eb/usb.c
M src/southbridge/intel/i82801dx/ac97.c
M src/southbridge/intel/i82801dx/ide.c
M src/southbridge/intel/i82801dx/lpc.c
M src/southbridge/intel/i82801dx/pci.c
M src/southbridge/intel/i82801dx/usb.c
M src/southbridge/intel/i82801dx/usb2.c
M src/southbridge/intel/i82801gx/ac97.c
M src/southbridge/intel/i82801gx/azalia.c
M src/southbridge/intel/i82801gx/ide.c
M src/southbridge/intel/i82801gx/lpc.c
M src/southbridge/intel/i82801gx/nic.c
M src/southbridge/intel/i82801gx/pci.c
M src/southbridge/intel/i82801gx/pcie.c
M src/southbridge/intel/i82801gx/sata.c
M src/southbridge/intel/i82801gx/smbus.c
M src/southbridge/intel/i82801gx/usb.c
M src/southbridge/intel/i82801gx/usb_ehci.c
M src/southbridge/intel/i82801ix/early_smbus.c
M src/southbridge/intel/i82801ix/hdaudio.c
M src/southbridge/intel/i82801ix/lpc.c
M src/southbridge/intel/i82801ix/pci.c
M src/southbridge/intel/i82801ix/pcie.c
M src/southbridge/intel/i82801ix/sata.c
M src/southbridge/intel/i82801ix/smbus.c
M src/southbridge/intel/i82801ix/thermal.c
M src/southbridge/intel/i82801ix/usb_ehci.c
M src/southbridge/intel/i82801jx/hdaudio.c
M src/southbridge/intel/i82801jx/lpc.c
M src/southbridge/intel/i82801jx/pci.c
M src/southbridge/intel/i82801jx/pcie.c
M src/southbridge/intel/i82801jx/sata.c
M src/southbridge/intel/i82801jx/smbus.c
M src/southbridge/intel/i82801jx/thermal.c
M src/southbridge/intel/i82801jx/usb_ehci.c
M src/southbridge/intel/i82870/ioapic.c
M src/southbridge/intel/i82870/pcibridge.c
M src/southbridge/intel/ibexpeak/azalia.c
M src/southbridge/intel/ibexpeak/lpc.c
M src/southbridge/intel/ibexpeak/me.c
M src/southbridge/intel/ibexpeak/sata.c
M src/southbridge/intel/ibexpeak/smbus.c
M src/southbridge/intel/ibexpeak/thermal.c
M src/southbridge/intel/ibexpeak/usb_ehci.c
M src/southbridge/intel/lynxpoint/azalia.c
M src/southbridge/intel/lynxpoint/lpc.c
M src/southbridge/intel/lynxpoint/me_9.x.c
M src/southbridge/intel/lynxpoint/pcie.c
M src/southbridge/intel/lynxpoint/sata.c
M src/southbridge/intel/lynxpoint/serialio.c
M src/southbridge/intel/lynxpoint/smbus.c
M src/southbridge/intel/lynxpoint/usb_ehci.c
M src/southbridge/intel/lynxpoint/usb_xhci.c
M src/southbridge/ricoh/rl5c476/rl5c476.c
M src/southbridge/ti/pci1x2x/pci1x2x.c
M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Pci22.h
231 files changed, 4,936 insertions(+), 4,936 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/39331/3

[build bot (Jenkins) (Code Review)]

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39331 )

Change subject: src/*: Make PCI ID macro names shorter
......................................................................

Patch Set 3:

(6 comments)

https://review.coreboot.org/c/coreboot/+/39331/3/src/include/device/pci_ids.... 
File src/include/device/pci_ids.h:

https://review.coreboot.org/c/coreboot/+/39331/3/src/include/device/pci_ids.... 
PS3, Line 2044: #define PCI_VID_AKS		0x416c
'AKS' may be misspelled - perhaps 'ASK'?

https://review.coreboot.org/c/coreboot/+/39331/3/src/include/device/pci_ids.... 
PS3, Line 2045: #define PCI_DID_AKS_ALADDINCARD	0x0100
'AKS' may be misspelled - perhaps 'ASK'?

https://review.coreboot.org/c/coreboot/+/39331/3/src/include/device/pci_ids.... 
PS3, Line 2046: #define PCI_DID_AKS_CPC		0x0200
'AKS' may be misspelled - perhaps 'ASK'?

https://review.coreboot.org/c/coreboot/+/39331/3/src/soc/intel/skylake/vr_co... 
File src/soc/intel/skylake/vr_config.c:

https://review.coreboot.org/c/coreboot/+/39331/3/src/soc/intel/skylake/vr_co... 
PS3, Line 229: 		         (igd_id == PCI_DID_INTEL_KBL_GT3E_SULTM_2)) {
code indent should use tabs where possible

https://review.coreboot.org/c/coreboot/+/39331/3/src/southbridge/amd/agesa/h... 
File src/southbridge/amd/agesa/hudson/hudson.c:

https://review.coreboot.org/c/coreboot/+/39331/3/src/southbridge/amd/agesa/h... 
PS3, Line 80: 			else if (sd_device_id == PCI_DID_AMD_YANGTZE_SD) {
else should follow close brace '}'

https://review.coreboot.org/c/coreboot/+/39331/3/src/southbridge/amd/pi/huds... 
File src/southbridge/amd/pi/hudson/hudson.c:

https://review.coreboot.org/c/coreboot/+/39331/3/src/southbridge/amd/pi/huds... 
PS3, Line 54: 			else if (sd_device_id == PCI_DID_AMD_YANGTZE_SD) {
else should follow close brace '}'

[Felix Singer (Code Review)]

Hello build bot (Jenkins), Angel Pons, Arthur Heymans, Michael Niewöhner, Andrey Petrov, Patrick Rudolph, Nico Huber, Damien Zammit, David Guckian, Vanessa Eusebio, Alexander Couzens, Werner Zeh, Felix Held,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/39331

to look at the new patch set (#4).

Change subject: src/*: Make PCI ID macro names shorter
......................................................................

src/*: Make PCI ID macro names shorter

This patch shortens macro names containing PCI_{DEVICE,VENDOR}_ID_
with PCI_{DID,VID}_.

Used commands:
find -type f -exec sed -i 's/PCI_DEVICE_ID_/PCI_DID_/g' {} +
find -type f -exec sed -i 's/PCI_VENDOR_ID_/PCI_VID_/g' {} +

Signed-off-by: Felix Singer 
Change-Id: If9027700f53b6d0d3964c26a41a1f9b8f62be178
---
M src/device/pci_rom.c
M src/drivers/aspeed/ast2050/ast2050.c
M src/drivers/broadcom/bcm57xx_aspm_disable.c
M src/drivers/dec/21143/21143.c
M src/drivers/generic/bayhub/bh720.c
M src/drivers/intel/gma/opregion.c
M src/drivers/intel/i210/i210.c
M src/drivers/intel/ish/ish.c
M src/drivers/intel/wifi/wifi.c
M src/drivers/ricoh/rce822/rce822.c
M src/drivers/siemens/nc_fpga/nc_fpga.c
M src/drivers/xgi/common/XGI_main.h
M src/drivers/xgi/common/xgi_coreboot.c
M src/drivers/xgi/z9s/z9s.c
M src/include/device/pci_ids.h
M src/mainboard/google/poppy/variants/atlas/mainboard.c
M src/mainboard/google/poppy/variants/nocturne/mainboard.c
M src/mainboard/lenovo/x60/mainboard.c
M src/mainboard/siemens/mc_apl1/mainboard.c
M src/mainboard/siemens/mc_apl1/variants/mc_apl1/mainboard.c
M src/mainboard/siemens/mc_apl1/variants/mc_apl2/mainboard.c
M src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c
M src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c
M src/mainboard/siemens/mc_apl1/variants/mc_apl6/mainboard.c
M src/northbridge/amd/agesa/family14/northbridge.c
M src/northbridge/amd/agesa/family15tn/iommu.c
M src/northbridge/amd/agesa/family15tn/northbridge.c
M src/northbridge/amd/agesa/family16kb/northbridge.c
M src/northbridge/amd/pi/00630F01/iommu.c
M src/northbridge/amd/pi/00630F01/northbridge.c
M src/northbridge/amd/pi/00660F01/northbridge.c
M src/northbridge/amd/pi/00730F01/iommu.c
M src/northbridge/amd/pi/00730F01/northbridge.c
M src/northbridge/intel/gm45/gma.c
M src/northbridge/intel/haswell/gma.c
M src/northbridge/intel/haswell/minihd.c
M src/northbridge/intel/haswell/northbridge.c
M src/northbridge/intel/haswell/pcie.c
M src/northbridge/intel/i440bx/northbridge.c
M src/northbridge/intel/i945/gma.c
M src/northbridge/intel/i945/northbridge.c
M src/northbridge/intel/nehalem/gma.c
M src/northbridge/intel/nehalem/nehalem.h
M src/northbridge/intel/nehalem/northbridge.c
M src/northbridge/intel/pineview/gma.c
M src/northbridge/intel/sandybridge/gma.c
M src/northbridge/intel/sandybridge/northbridge.c
M src/northbridge/intel/sandybridge/pcie.c
M src/northbridge/intel/x4x/gma.c
M src/soc/amd/common/block/hda/hda.c
M src/soc/amd/common/block/iommu/iommu.c
M src/soc/amd/common/block/lpc/lpc.c
M src/soc/amd/common/block/sata/sata.c
M src/soc/amd/common/block/smbus/sm.c
M src/soc/amd/picasso/acp.c
M src/soc/amd/picasso/northbridge.c
M src/soc/amd/picasso/usb.c
M src/soc/amd/stoneyridge/include/soc/pci_devs.h
M src/soc/amd/stoneyridge/northbridge.c
M src/soc/amd/stoneyridge/usb.c
M src/soc/cavium/common/pci/uart.c
M src/soc/intel/apollolake/report_platform.c
M src/soc/intel/baytrail/ehci.c
M src/soc/intel/baytrail/emmc.c
M src/soc/intel/baytrail/gfx.c
M src/soc/intel/baytrail/hda.c
M src/soc/intel/baytrail/lpe.c
M src/soc/intel/baytrail/lpss.c
M src/soc/intel/baytrail/northcluster.c
M src/soc/intel/baytrail/pcie.c
M src/soc/intel/baytrail/sata.c
M src/soc/intel/baytrail/sd.c
M src/soc/intel/baytrail/southcluster.c
M src/soc/intel/baytrail/xhci.c
M src/soc/intel/braswell/emmc.c
M src/soc/intel/braswell/gfx.c
M src/soc/intel/braswell/lpe.c
M src/soc/intel/braswell/lpss.c
M src/soc/intel/braswell/northcluster.c
M src/soc/intel/braswell/pcie.c
M src/soc/intel/braswell/sata.c
M src/soc/intel/braswell/sd.c
M src/soc/intel/braswell/southcluster.c
M src/soc/intel/braswell/xhci.c
M src/soc/intel/broadwell/adsp.c
M src/soc/intel/broadwell/ehci.c
M src/soc/intel/broadwell/hda.c
M src/soc/intel/broadwell/igd.c
M src/soc/intel/broadwell/lpc.c
M src/soc/intel/broadwell/me.c
M src/soc/intel/broadwell/minihd.c
M src/soc/intel/broadwell/pcie.c
M src/soc/intel/broadwell/sata.c
M src/soc/intel/broadwell/serialio.c
M src/soc/intel/broadwell/smbus.c
M src/soc/intel/broadwell/systemagent.c
M src/soc/intel/broadwell/xhci.c
M src/soc/intel/cannonlake/bootblock/report_platform.c
M src/soc/intel/cannonlake/vr_config.c
M src/soc/intel/common/block/cse/cse.c
M src/soc/intel/common/block/dsp/dsp.c
M src/soc/intel/common/block/graphics/graphics.c
M src/soc/intel/common/block/hda/hda.c
M src/soc/intel/common/block/i2c/i2c.c
M src/soc/intel/common/block/lpc/lpc.c
M src/soc/intel/common/block/p2sb/p2sb.c
M src/soc/intel/common/block/pcie/pcie.c
M src/soc/intel/common/block/pmc/pmc.c
M src/soc/intel/common/block/sata/sata.c
M src/soc/intel/common/block/scs/mmc.c
M src/soc/intel/common/block/scs/sd.c
M src/soc/intel/common/block/smbus/smbus.c
M src/soc/intel/common/block/spi/spi.c
M src/soc/intel/common/block/sram/sram.c
M src/soc/intel/common/block/systemagent/systemagent.c
M src/soc/intel/common/block/uart/uart.c
M src/soc/intel/common/block/xdci/xdci.c
M src/soc/intel/common/block/xhci/xhci.c
M src/soc/intel/denverton_ns/csme_ie_kt.c
M src/soc/intel/denverton_ns/lpc.c
M src/soc/intel/denverton_ns/npk.c
M src/soc/intel/denverton_ns/pmc.c
M src/soc/intel/denverton_ns/sata.c
M src/soc/intel/denverton_ns/systemagent.c
M src/soc/intel/denverton_ns/uart.c
M src/soc/intel/denverton_ns/xhci.c
M src/soc/intel/icelake/bootblock/report_platform.c
M src/soc/intel/quark/ehci.c
M src/soc/intel/quark/gpio_i2c.c
M src/soc/intel/quark/lpc.c
M src/soc/intel/quark/northcluster.c
M src/soc/intel/quark/sd.c
M src/soc/intel/quark/spi.c
M src/soc/intel/quark/uart.c
M src/soc/intel/skylake/bootblock/report_platform.c
M src/soc/intel/skylake/vr_config.c
M src/soc/intel/tigerlake/bootblock/report_platform.c
M src/soc/intel/xeon_sp/uncore.c
M src/southbridge/amd/agesa/hudson/hda.c
M src/southbridge/amd/agesa/hudson/hudson.c
M src/southbridge/amd/agesa/hudson/ide.c
M src/southbridge/amd/agesa/hudson/lpc.c
M src/southbridge/amd/agesa/hudson/pci.c
M src/southbridge/amd/agesa/hudson/pcie.c
M src/southbridge/amd/agesa/hudson/sata.c
M src/southbridge/amd/agesa/hudson/sd.c
M src/southbridge/amd/agesa/hudson/sm.c
M src/southbridge/amd/agesa/hudson/usb.c
M src/southbridge/amd/cimx/sb800/late.c
M src/southbridge/amd/pi/hudson/hda.c
M src/southbridge/amd/pi/hudson/hudson.c
M src/southbridge/amd/pi/hudson/ide.c
M src/southbridge/amd/pi/hudson/lpc.c
M src/southbridge/amd/pi/hudson/pci.c
M src/southbridge/amd/pi/hudson/pcie.c
M src/southbridge/amd/pi/hudson/sata.c
M src/southbridge/amd/pi/hudson/sd.c
M src/southbridge/amd/pi/hudson/sm.c
M src/southbridge/amd/pi/hudson/usb.c
M src/southbridge/intel/bd82x6x/azalia.c
M src/southbridge/intel/bd82x6x/lpc.c
M src/southbridge/intel/bd82x6x/me.c
M src/southbridge/intel/bd82x6x/me_8.x.c
M src/southbridge/intel/bd82x6x/pci.c
M src/southbridge/intel/bd82x6x/pcie.c
M src/southbridge/intel/bd82x6x/sata.c
M src/southbridge/intel/bd82x6x/smbus.c
M src/southbridge/intel/bd82x6x/usb_ehci.c
M src/southbridge/intel/bd82x6x/usb_xhci.c
M src/southbridge/intel/i82371eb/bootblock.c
M src/southbridge/intel/i82371eb/early_pm.c
M src/southbridge/intel/i82371eb/early_smbus.c
M src/southbridge/intel/i82371eb/ide.c
M src/southbridge/intel/i82371eb/isa.c
M src/southbridge/intel/i82371eb/smbus.c
M src/southbridge/intel/i82371eb/usb.c
M src/southbridge/intel/i82801dx/ac97.c
M src/southbridge/intel/i82801dx/ide.c
M src/southbridge/intel/i82801dx/lpc.c
M src/southbridge/intel/i82801dx/pci.c
M src/southbridge/intel/i82801dx/usb.c
M src/southbridge/intel/i82801dx/usb2.c
M src/southbridge/intel/i82801gx/ac97.c
M src/southbridge/intel/i82801gx/azalia.c
M src/southbridge/intel/i82801gx/ide.c
M src/southbridge/intel/i82801gx/lpc.c
M src/southbridge/intel/i82801gx/nic.c
M src/southbridge/intel/i82801gx/pci.c
M src/southbridge/intel/i82801gx/pcie.c
M src/southbridge/intel/i82801gx/sata.c
M src/southbridge/intel/i82801gx/smbus.c
M src/southbridge/intel/i82801gx/usb.c
M src/southbridge/intel/i82801gx/usb_ehci.c
M src/southbridge/intel/i82801ix/early_smbus.c
M src/southbridge/intel/i82801ix/hdaudio.c
M src/southbridge/intel/i82801ix/lpc.c
M src/southbridge/intel/i82801ix/pci.c
M src/southbridge/intel/i82801ix/pcie.c
M src/southbridge/intel/i82801ix/sata.c
M src/southbridge/intel/i82801ix/smbus.c
M src/southbridge/intel/i82801ix/thermal.c
M src/southbridge/intel/i82801ix/usb_ehci.c
M src/southbridge/intel/i82801jx/hdaudio.c
M src/southbridge/intel/i82801jx/lpc.c
M src/southbridge/intel/i82801jx/pci.c
M src/southbridge/intel/i82801jx/pcie.c
M src/southbridge/intel/i82801jx/sata.c
M src/southbridge/intel/i82801jx/smbus.c
M src/southbridge/intel/i82801jx/thermal.c
M src/southbridge/intel/i82801jx/usb_ehci.c
M src/southbridge/intel/i82870/ioapic.c
M src/southbridge/intel/i82870/pcibridge.c
M src/southbridge/intel/ibexpeak/azalia.c
M src/southbridge/intel/ibexpeak/lpc.c
M src/southbridge/intel/ibexpeak/me.c
M src/southbridge/intel/ibexpeak/sata.c
M src/southbridge/intel/ibexpeak/smbus.c
M src/southbridge/intel/ibexpeak/thermal.c
M src/southbridge/intel/ibexpeak/usb_ehci.c
M src/southbridge/intel/lynxpoint/azalia.c
M src/southbridge/intel/lynxpoint/lpc.c
M src/southbridge/intel/lynxpoint/me_9.x.c
M src/southbridge/intel/lynxpoint/pcie.c
M src/southbridge/intel/lynxpoint/sata.c
M src/southbridge/intel/lynxpoint/serialio.c
M src/southbridge/intel/lynxpoint/smbus.c
M src/southbridge/intel/lynxpoint/usb_ehci.c
M src/southbridge/intel/lynxpoint/usb_xhci.c
M src/southbridge/ricoh/rl5c476/rl5c476.c
M src/southbridge/ti/pci1x2x/pci1x2x.c
M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Pci22.h
231 files changed, 4,936 insertions(+), 4,936 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/39331/4

[Felix Singer (Code Review)]

Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39331 )

Change subject: src/*: Make PCI ID macro names shorter
......................................................................

Patch Set 4:

(1 comment)

https://review.coreboot.org/c/coreboot/+/39331/1//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/39331/1//COMMIT_MSG@14 
PS1, Line 14: find -type f -exec sed -i 's/PCI_VENDOR_ID_/PCI_VID_/' {} ;
> Missing `g` modifier for the substitution. There are some lines with […]

Done

[Felix Singer (Code Review)]

Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39331 )

Change subject: src/*: Make PCI ID macro names shorter
......................................................................

Patch Set 4:
> Patch Set 1: Code-Review+1
>
> Needs a little more work and somebody with a lot of time to re-align
> the whole `pci_ids.h`.

I will do that in a follow-up patch.

[build bot (Jenkins) (Code Review)]

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39331 )

Change subject: src/*: Make PCI ID macro names shorter
......................................................................

Patch Set 5:

(6 comments)

https://review.coreboot.org/c/coreboot/+/39331/5/src/include/device/pci_ids.... 
File src/include/device/pci_ids.h:

https://review.coreboot.org/c/coreboot/+/39331/5/src/include/device/pci_ids.... 
PS5, Line 2044: #define PCI_VID_AKS		0x416c
'AKS' may be misspelled - perhaps 'ASK'?

https://review.coreboot.org/c/coreboot/+/39331/5/src/include/device/pci_ids.... 
PS5, Line 2045: #define PCI_DID_AKS_ALADDINCARD	0x0100
'AKS' may be misspelled - perhaps 'ASK'?

https://review.coreboot.org/c/coreboot/+/39331/5/src/include/device/pci_ids.... 
PS5, Line 2046: #define PCI_DID_AKS_CPC		0x0200
'AKS' may be misspelled - perhaps 'ASK'?

https://review.coreboot.org/c/coreboot/+/39331/5/src/soc/intel/skylake/vr_co... 
File src/soc/intel/skylake/vr_config.c:

https://review.coreboot.org/c/coreboot/+/39331/5/src/soc/intel/skylake/vr_co... 
PS5, Line 229: 		         (igd_id == PCI_DID_INTEL_KBL_GT3E_SULTM_2)) {
code indent should use tabs where possible

https://review.coreboot.org/c/coreboot/+/39331/5/src/southbridge/amd/agesa/h... 
File src/southbridge/amd/agesa/hudson/hudson.c:

https://review.coreboot.org/c/coreboot/+/39331/5/src/southbridge/amd/agesa/h... 
PS5, Line 80: 			else if (sd_device_id == PCI_DID_AMD_YANGTZE_SD) {
else should follow close brace '}'

https://review.coreboot.org/c/coreboot/+/39331/5/src/southbridge/amd/pi/huds... 
File src/southbridge/amd/pi/hudson/hudson.c:

https://review.coreboot.org/c/coreboot/+/39331/5/src/southbridge/amd/pi/huds... 
PS5, Line 54: 			else if (sd_device_id == PCI_DID_AMD_YANGTZE_SD) {
else should follow close brace '}'

[Michael Niewöhner (Code Review)]

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39331 )

Change subject: src/*: Make PCI ID macro names shorter
......................................................................

Patch Set 5: Code-Review+1

[David Guckian (Code Review)]

David Guckian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39331 )

Change subject: src/*: Make PCI ID macro names shorter
......................................................................

Patch Set 5: Code-Review+1

[Martin Roth (Code Review)]

Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39331 )

Change subject: src/*: Make PCI ID macro names shorter
......................................................................

Patch Set 5:

(1 comment)

https://review.coreboot.org/c/coreboot/+/39331/1//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/39331/1//COMMIT_MSG@8 
PS1, Line 8: 
           : This patch shortens macro names containing PCI_{DEVICE,VENDOR}_ID_
           : with PCI_{DID,VID}_.
Hi Felix,  I appreciate the effort you're putting in to make the coreboot codebase better.

Please be aware of the impact that this sort of change makes on trying to maintain coreboot for users not on the current branch.  Say for example that someone wants to port something back to the 4.9 branch.  After this sort of change, that's much harder.  If it touches one of these values, they now have to update this as well.

Is this change worth that?  I'm not going to try to answer that question, it's just something to keep in mind when making codebase-wide changes.  Something that seems relatively simple and innocuous can have wide-reaching effects.

[Felix Singer (Code Review)]

Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39331 )

Change subject: src/*: Make PCI ID macro names shorter
......................................................................

Patch Set 5:

(1 comment)

https://review.coreboot.org/c/coreboot/+/39331/1//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/39331/1//COMMIT_MSG@8 
PS1, Line 8: 
           : This patch shortens macro names containing PCI_{DEVICE,VENDOR}_ID_
           : with PCI_{DID,VID}_.
> Hi Felix,  I appreciate the effort you're putting in to make the coreboot codebase better. […]

Hi, thanks for your comment!

I am not sure if this change is really worth it, because I don't know how much the other branches are used or how much backporting work is made. I am using master branch, mostly.

These are just names, so nothing special. I can live with that, if this patch is not getting merged. This is just an idea to reduce the characters count so that Jenkins is less complaining about exceeding the characters limit.

[Patrick Georgi (Code Review)]

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39331 )

Change subject: src/*: Make PCI ID macro names shorter
......................................................................

Patch Set 5:

(1 comment)

https://review.coreboot.org/c/coreboot/+/39331/1//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/39331/1//COMMIT_MSG@8 
PS1, Line 8: 
           : This patch shortens macro names containing PCI_{DEVICE,VENDOR}_ID_
           : with PCI_{DID,VID}_.
> Hi, thanks for your comment! […]

Felix, how much post processing was needed on this? If the commands below do a good job (with no gotchas) I guess we could just prepare commits for the last couple of branches? (I'd volunteer to do that if the change is easily adapted)

Generally speaking, I think we shouldn't let older branches stop us from improving master, but an approach like this should  help backporters.

[Felix Singer (Code Review)]

Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39331 )

Change subject: src/*: Make PCI ID macro names shorter
......................................................................

Patch Set 5:

(1 comment)

https://review.coreboot.org/c/coreboot/+/39331/1//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/39331/1//COMMIT_MSG@8 
PS1, Line 8: 
           : This patch shortens macro names containing PCI_{DEVICE,VENDOR}_ID_
           : with PCI_{DID,VID}_.
> Felix, how much post processing was needed on this? If the commands below do a good job (with no got […]

Sounds like a good idea.

I only executed these commands. I did nothing else.

[Felix Held (Code Review)]

Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39331 )

Change subject: src/*: Make PCI ID macro names shorter
......................................................................

Patch Set 5: Code-Review+1

(1 comment)

i like this change, since it shortens the names without losing information.
with the commands to do this in the commit message i don't think that it makes upstreaming and rebasing from older branches much more inconvenient than it would be without this patch.
to get this patch in master we need to coordinate things a bit; when other patches that use those defines are merged within the 24h cool-off window, this would need to be rebased over and over again. if we agree that this is a good idea, we should probably try to get the 3 +2 to fast-track this. since the patch has been sitting here for nearly two weeks, i'd find this approach acceptable here, even though this is not a "the tree is broken and we need to fix it asap" situation

https://review.coreboot.org/c/coreboot/+/39331/5/src/include/device/pci_ids.... 
File src/include/device/pci_ids.h:

PS5: 
since 6 chars get removed, the tab-alignement of the values is broken in some places. might be a bit annoying to fix, but currently this doesn't look too nice

[Felix Singer (Code Review)]

Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39331 )

Change subject: src/*: Make PCI ID macro names shorter
......................................................................

Patch Set 5:

(1 comment)

Patchset:

PS5: 
I am wondering, is there still any interest in this? If so, I will rebase.

[Paul Menzel (Code Review)]

Attention is currently required from:  Felix Singer.
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39331 )

Change subject: src/*: Make PCI ID macro names shorter
......................................................................

Patch Set 5:

(1 comment)

Patchset:

PS5:
> I am wondering, is there still any interest in this? If so, I will rebase.

Yes, that’d be great.

[Felix Singer (Code Review)]

Attention is currently required from:  Felix Singer.
Hello build bot (Jenkins), Angel Pons, Arthur Heymans, Michael Niewöhner, Andrey Petrov, Patrick Rudolph, Nico Huber, Damien Zammit, David Guckian, Vanessa Eusebio, Alexander Couzens, Werner Zeh, Felix Held, David Guckian,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/39331

to look at the new patch set (#6).

Change subject: src/*: Make PCI ID macro names shorter
......................................................................

src/*: Make PCI ID macro names shorter

This patch shortens macro names containing PCI_{DEVICE,VENDOR}_ID_
with PCI_{DID,VID}_.

Used commands:
find -type f -exec sed -i 's/PCI_DEVICE_ID_/PCI_DID_/g' {} +
find -type f -exec sed -i 's/PCI_VENDOR_ID_/PCI_VID_/g' {} +

Change-Id: If9027700f53b6d0d3964c26a41a1f9b8f62be178
Signed-off-by: Felix Singer 
---
M src/device/pci_rom.c
M src/drivers/aspeed/ast2050/ast2050.c
M src/drivers/broadcom/bcm57xx_aspm_disable.c
M src/drivers/generic/bayhub/bh720.c
M src/drivers/generic/bayhub_lv2/lv2.c
M src/drivers/genesyslogic/gl9755/gl9755.c
M src/drivers/genesyslogic/gl9763e/gl9763e.c
M src/drivers/intel/gma/opregion.c
M src/drivers/intel/i210/i210.c
M src/drivers/intel/ish/ish.c
M src/drivers/ricoh/rce822/rce822.c
M src/drivers/siemens/nc_fpga/nc_fpga.c
M src/drivers/siemens/nc_fpga/nc_fpga_early.c
M src/drivers/usb/pci_xhci/pci_xhci.c
M src/drivers/wifi/generic/acpi.c
M src/drivers/wifi/generic/generic.c
M src/drivers/wifi/generic/smbios.c
M src/include/device/pci_ids.h
M src/mainboard/google/brya/variants/brya0/ramstage.c
M src/mainboard/google/hatch/variants/baseboard/mainboard.c
M src/mainboard/google/poppy/variants/atlas/mainboard.c
M src/mainboard/google/poppy/variants/nocturne/mainboard.c
M src/mainboard/intel/adlrvp/ramstage.c
M src/mainboard/lenovo/x60/mainboard.c
M src/mainboard/prodrive/hermes/devicetree.cb
M src/mainboard/siemens/mc_apl1/mainboard.c
M src/mainboard/siemens/mc_apl1/variants/mc_apl1/mainboard.c
M src/mainboard/siemens/mc_apl1/variants/mc_apl2/mainboard.c
M src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c
M src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c
M src/mainboard/siemens/mc_apl1/variants/mc_apl6/mainboard.c
M src/mainboard/siemens/mc_ehl/mainboard.c
M src/northbridge/amd/agesa/family14/northbridge.c
M src/northbridge/amd/agesa/family15tn/iommu.c
M src/northbridge/amd/agesa/family15tn/northbridge.c
M src/northbridge/amd/agesa/family16kb/northbridge.c
M src/northbridge/amd/pi/00730F01/iommu.c
M src/northbridge/amd/pi/00730F01/northbridge.c
M src/northbridge/intel/gm45/gma.c
M src/northbridge/intel/haswell/gma.c
M src/northbridge/intel/haswell/minihd.c
M src/northbridge/intel/haswell/northbridge.c
M src/northbridge/intel/haswell/pcie.c
M src/northbridge/intel/i440bx/northbridge.c
M src/northbridge/intel/i945/gma.c
M src/northbridge/intel/i945/northbridge.c
M src/northbridge/intel/ironlake/gma.c
M src/northbridge/intel/ironlake/northbridge.c
M src/northbridge/intel/pineview/gma.c
M src/northbridge/intel/sandybridge/gma.c
M src/northbridge/intel/sandybridge/northbridge.c
M src/northbridge/intel/sandybridge/pcie.c
M src/northbridge/intel/x4x/gma.c
M src/soc/amd/cezanne/data_fabric.c
M src/soc/amd/cezanne/root_complex.c
M src/soc/amd/common/block/acp/acp.c
M src/soc/amd/common/block/graphics/graphics.c
M src/soc/amd/common/block/hda/hda.c
M src/soc/amd/common/block/iommu/iommu.c
M src/soc/amd/common/block/lpc/lpc.c
M src/soc/amd/common/block/pci/pcie_gpp.c
M src/soc/amd/common/block/sata/sata.c
M src/soc/amd/common/block/smbus/sm.c
M src/soc/amd/picasso/data_fabric.c
M src/soc/amd/picasso/root_complex.c
M src/soc/amd/stoneyridge/include/soc/pci_devs.h
M src/soc/amd/stoneyridge/northbridge.c
M src/soc/amd/stoneyridge/usb.c
M src/soc/cavium/common/pci/uart.c
M src/soc/intel/alderlake/bootblock/report_platform.c
M src/soc/intel/alderlake/chip.h
M src/soc/intel/alderlake/cpu.c
M src/soc/intel/alderlake/fsp_params.c
M src/soc/intel/alderlake/vr_config.c
M src/soc/intel/apollolake/report_platform.c
M src/soc/intel/baytrail/ehci.c
M src/soc/intel/baytrail/emmc.c
M src/soc/intel/baytrail/gfx.c
M src/soc/intel/baytrail/hda.c
M src/soc/intel/baytrail/lpe.c
M src/soc/intel/baytrail/lpss.c
M src/soc/intel/baytrail/northcluster.c
M src/soc/intel/baytrail/pcie.c
M src/soc/intel/baytrail/sata.c
M src/soc/intel/baytrail/sd.c
M src/soc/intel/baytrail/southcluster.c
M src/soc/intel/baytrail/xhci.c
M src/soc/intel/braswell/emmc.c
M src/soc/intel/braswell/gfx.c
M src/soc/intel/braswell/lpe.c
M src/soc/intel/braswell/lpss.c
M src/soc/intel/braswell/northcluster.c
M src/soc/intel/braswell/pcie.c
M src/soc/intel/braswell/sata.c
M src/soc/intel/braswell/sd.c
M src/soc/intel/braswell/southcluster.c
M src/soc/intel/braswell/xhci.c
M src/soc/intel/broadwell/gma.c
M src/soc/intel/broadwell/minihd.c
M src/soc/intel/broadwell/northbridge.c
M src/soc/intel/broadwell/pch/adsp.c
M src/soc/intel/broadwell/pch/hda.c
M src/soc/intel/broadwell/pch/lpc.c
M src/soc/intel/broadwell/pch/me.c
M src/soc/intel/broadwell/pch/pcie.c
M src/soc/intel/broadwell/pch/sata.c
M src/soc/intel/broadwell/pch/serialio.c
M src/soc/intel/broadwell/pch/usb_ehci.c
M src/soc/intel/broadwell/pch/usb_xhci.c
M src/soc/intel/cannonlake/bootblock/report_platform.c
M src/soc/intel/cannonlake/vr_config.c
M src/soc/intel/common/block/cnvi/cnvi.c
M src/soc/intel/common/block/cse/cse.c
M src/soc/intel/common/block/dsp/dsp.c
M src/soc/intel/common/block/dtt/dtt.c
M src/soc/intel/common/block/graphics/graphics.c
M src/soc/intel/common/block/hda/hda.c
M src/soc/intel/common/block/i2c/i2c.c
M src/soc/intel/common/block/ipu/ipu.c
M src/soc/intel/common/block/lpc/lpc.c
M src/soc/intel/common/block/p2sb/p2sb.c
M src/soc/intel/common/block/pcie/pcie.c
M src/soc/intel/common/block/pmc/pmc.c
M src/soc/intel/common/block/sata/sata.c
M src/soc/intel/common/block/scs/mmc.c
M src/soc/intel/common/block/scs/sd.c
M src/soc/intel/common/block/smbus/smbus.c
M src/soc/intel/common/block/spi/spi.c
M src/soc/intel/common/block/sram/sram.c
M src/soc/intel/common/block/systemagent/systemagent.c
M src/soc/intel/common/block/uart/uart.c
M src/soc/intel/common/block/usb4/usb4.c
M src/soc/intel/common/block/usb4/xhci.c
M src/soc/intel/common/block/xdci/xdci.c
M src/soc/intel/common/block/xhci/xhci.c
M src/soc/intel/denverton_ns/csme_ie_kt.c
M src/soc/intel/denverton_ns/lpc.c
M src/soc/intel/denverton_ns/npk.c
M src/soc/intel/denverton_ns/pmc.c
M src/soc/intel/denverton_ns/sata.c
M src/soc/intel/denverton_ns/systemagent.c
M src/soc/intel/denverton_ns/uart.c
M src/soc/intel/denverton_ns/xhci.c
M src/soc/intel/elkhartlake/bootblock/report_platform.c
M src/soc/intel/icelake/bootblock/report_platform.c
M src/soc/intel/jasperlake/bootblock/report_platform.c
M src/soc/intel/quark/ehci.c
M src/soc/intel/quark/gpio_i2c.c
M src/soc/intel/quark/lpc.c
M src/soc/intel/quark/northcluster.c
M src/soc/intel/quark/sd.c
M src/soc/intel/quark/spi.c
M src/soc/intel/quark/uart.c
M src/soc/intel/skylake/bootblock/report_platform.c
M src/soc/intel/skylake/graphics.c
M src/soc/intel/skylake/vr_config.c
M src/soc/intel/tigerlake/bootblock/report_platform.c
M src/soc/intel/tigerlake/lpm.c
M src/soc/intel/tigerlake/systemagent.c
M src/soc/intel/xeon_sp/cpx/chip.c
M src/soc/intel/xeon_sp/uncore.c
M src/southbridge/amd/agesa/hudson/hda.c
M src/southbridge/amd/agesa/hudson/hudson.c
M src/southbridge/amd/agesa/hudson/ide.c
M src/southbridge/amd/agesa/hudson/lpc.c
M src/southbridge/amd/agesa/hudson/pci.c
M src/southbridge/amd/agesa/hudson/pcie.c
M src/southbridge/amd/agesa/hudson/sata.c
M src/southbridge/amd/agesa/hudson/sd.c
M src/southbridge/amd/agesa/hudson/sm.c
M src/southbridge/amd/agesa/hudson/usb.c
M src/southbridge/amd/cimx/sb800/late.c
M src/southbridge/amd/pi/hudson/hda.c
M src/southbridge/amd/pi/hudson/hudson.c
M src/southbridge/amd/pi/hudson/ide.c
M src/southbridge/amd/pi/hudson/lpc.c
M src/southbridge/amd/pi/hudson/pci.c
M src/southbridge/amd/pi/hudson/pcie.c
M src/southbridge/amd/pi/hudson/sata.c
M src/southbridge/amd/pi/hudson/sd.c
M src/southbridge/amd/pi/hudson/sm.c
M src/southbridge/amd/pi/hudson/usb.c
M src/southbridge/intel/bd82x6x/azalia.c
M src/southbridge/intel/bd82x6x/lpc.c
M src/southbridge/intel/bd82x6x/me.c
M src/southbridge/intel/bd82x6x/me_8.x.c
M src/southbridge/intel/bd82x6x/pci.c
M src/southbridge/intel/bd82x6x/pcie.c
M src/southbridge/intel/bd82x6x/sata.c
M src/southbridge/intel/bd82x6x/smbus.c
M src/southbridge/intel/bd82x6x/usb_ehci.c
M src/southbridge/intel/bd82x6x/usb_xhci.c
M src/southbridge/intel/common/early_smbus.c
M src/southbridge/intel/i82371eb/bootblock.c
M src/southbridge/intel/i82371eb/early_pm.c
M src/southbridge/intel/i82371eb/early_smbus.c
M src/southbridge/intel/i82371eb/ide.c
M src/southbridge/intel/i82371eb/isa.c
M src/southbridge/intel/i82371eb/smbus.c
M src/southbridge/intel/i82371eb/usb.c
M src/southbridge/intel/i82801dx/ac97.c
M src/southbridge/intel/i82801dx/ide.c
M src/southbridge/intel/i82801dx/lpc.c
M src/southbridge/intel/i82801dx/pci.c
M src/southbridge/intel/i82801dx/usb.c
M src/southbridge/intel/i82801dx/usb2.c
M src/southbridge/intel/i82801gx/ac97.c
M src/southbridge/intel/i82801gx/azalia.c
M src/southbridge/intel/i82801gx/ide.c
M src/southbridge/intel/i82801gx/lpc.c
M src/southbridge/intel/i82801gx/pci.c
M src/southbridge/intel/i82801gx/pcie.c
M src/southbridge/intel/i82801gx/sata.c
M src/southbridge/intel/i82801gx/smbus.c
M src/southbridge/intel/i82801gx/usb.c
M src/southbridge/intel/i82801gx/usb_ehci.c
M src/southbridge/intel/i82801ix/azalia.c
M src/southbridge/intel/i82801ix/lpc.c
M src/southbridge/intel/i82801ix/pci.c
M src/southbridge/intel/i82801ix/pcie.c
M src/southbridge/intel/i82801ix/sata.c
M src/southbridge/intel/i82801ix/smbus.c
M src/southbridge/intel/i82801ix/thermal.c
M src/southbridge/intel/i82801ix/usb_ehci.c
M src/southbridge/intel/i82801jx/azalia.c
M src/southbridge/intel/i82801jx/lpc.c
M src/southbridge/intel/i82801jx/pci.c
M src/southbridge/intel/i82801jx/pcie.c
M src/southbridge/intel/i82801jx/sata.c
M src/southbridge/intel/i82801jx/smbus.c
M src/southbridge/intel/i82801jx/thermal.c
M src/southbridge/intel/i82801jx/usb_ehci.c
M src/southbridge/intel/i82870/ioapic.c
M src/southbridge/intel/i82870/pcibridge.c
M src/southbridge/intel/ibexpeak/azalia.c
M src/southbridge/intel/ibexpeak/lpc.c
M src/southbridge/intel/ibexpeak/me.c
M src/southbridge/intel/ibexpeak/sata.c
M src/southbridge/intel/ibexpeak/smbus.c
M src/southbridge/intel/ibexpeak/thermal.c
M src/southbridge/intel/ibexpeak/usb_ehci.c
M src/southbridge/intel/lynxpoint/azalia.c
M src/southbridge/intel/lynxpoint/lpc.c
M src/southbridge/intel/lynxpoint/me.c
M src/southbridge/intel/lynxpoint/pcie.c
M src/southbridge/intel/lynxpoint/sata.c
M src/southbridge/intel/lynxpoint/serialio.c
M src/southbridge/intel/lynxpoint/smbus.c
M src/southbridge/intel/lynxpoint/usb_ehci.c
M src/southbridge/intel/lynxpoint/usb_xhci.c
M src/southbridge/ricoh/rl5c476/rl5c476.c
M src/southbridge/ti/pci1x2x/pci1x2x.c
M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Pci22.h
M src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/IndustryStandard/Pci22.h
254 files changed, 6,445 insertions(+), 6,445 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/39331/6

[build bot (Jenkins) (Code Review)]

Attention is currently required from: Raul Rangel, Patrick Rudolph, Mariusz Szafrański, Jonathan Zhang, Jason Glenesk, Anjaneya "Reddy" Chagam, Marshall Dawson, Johnny Lin, Tim Wawrzynczak, Christian Walter, Suresh Bellampalli, Michal Motyl, Tim Chu.
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39331 )

Change subject: src/*: Make PCI ID macro names shorter
......................................................................

Patch Set 6:

(6 comments)

File src/include/device/pci_ids.h:

Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133895):
https://review.coreboot.org/c/coreboot/+/39331/comment/62855751_55851ef3 
PS6, Line 2097: #define PCI_VID_AKS		0x416c
'AKS' may be misspelled - perhaps 'ASK'?

Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133895):
https://review.coreboot.org/c/coreboot/+/39331/comment/e6a62c65_e88e742a 
PS6, Line 2098: #define PCI_DID_AKS_ALADDINCARD	0x0100
'AKS' may be misspelled - perhaps 'ASK'?

Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133895):
https://review.coreboot.org/c/coreboot/+/39331/comment/038fa37f_14ba6434 
PS6, Line 2099: #define PCI_DID_AKS_CPC		0x0200
'AKS' may be misspelled - perhaps 'ASK'?

File src/soc/intel/skylake/vr_config.c:

Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133895):
https://review.coreboot.org/c/coreboot/+/39331/comment/3f661bb7_894250ac 
PS6, Line 215: 		         (igd_id == PCI_DID_INTEL_KBL_GT3E_SULTM_2)) {
code indent should use tabs where possible

File src/southbridge/amd/agesa/hudson/hudson.c:

Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133895):
https://review.coreboot.org/c/coreboot/+/39331/comment/7c03a752_e3ce595b 
PS6, Line 66: 			else if (sd_device_id == PCI_DID_AMD_YANGTZE_SD) {
else should follow close brace '}'

File src/southbridge/amd/pi/hudson/hudson.c:

Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133895):
https://review.coreboot.org/c/coreboot/+/39331/comment/36210b01_249cd018 
PS6, Line 41: 			else if (sd_device_id == PCI_DID_AMD_YANGTZE_SD) {
else should follow close brace '}'

[Felix Singer (Code Review)]

Attention is currently required from: Raul Rangel, Patrick Rudolph, Mariusz Szafrański, Jonathan Zhang, Jason Glenesk, Anjaneya "Reddy" Chagam, Marshall Dawson, Johnny Lin, Tim Wawrzynczak, Christian Walter, Suresh Bellampalli, Michal Motyl, Tim Chu.
Hello build bot (Jenkins), Raul Rangel, Patrick Rudolph, Mariusz Szafrański, Jonathan Zhang, Arthur Heymans, Andrey Petrov, Patrick Rudolph, Anjaneya "Reddy" Chagam, Nico Huber, David Guckian, Johnny Lin, Christian Walter, Suresh Bellampalli, Michal Motyl, Alexander Couzens, Werner Zeh, Tim Chu, Felix Held, Angel Pons, Michael Niewöhner, Jason Glenesk, Damien Zammit, Marshall Dawson, Tim Wawrzynczak, Vanessa Eusebio, David Guckian,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/39331

to look at the new patch set (#7).

Change subject: src/*: Make PCI ID macro names shorter
......................................................................

src/*: Make PCI ID macro names shorter

This patch shortens macro names containing PCI_{DEVICE,VENDOR}_ID_
with PCI_{DID,VID}_.

Used commands:
find -type f -exec sed -i 's/PCI_DEVICE_ID_/PCI_DID_/g' {} +
find -type f -exec sed -i 's/PCI_VENDOR_ID_/PCI_VID_/g' {} +

Change-Id: If9027700f53b6d0d3964c26a41a1f9b8f62be178
Signed-off-by: Felix Singer 
---
M src/device/pci_rom.c
M src/drivers/aspeed/ast2050/ast2050.c
M src/drivers/broadcom/bcm57xx_aspm_disable.c
M src/drivers/generic/bayhub/bh720.c
M src/drivers/generic/bayhub_lv2/lv2.c
M src/drivers/genesyslogic/gl9755/gl9755.c
M src/drivers/genesyslogic/gl9763e/gl9763e.c
M src/drivers/intel/gma/opregion.c
M src/drivers/intel/i210/i210.c
M src/drivers/intel/ish/ish.c
M src/drivers/ricoh/rce822/rce822.c
M src/drivers/siemens/nc_fpga/nc_fpga.c
M src/drivers/siemens/nc_fpga/nc_fpga_early.c
M src/drivers/usb/pci_xhci/pci_xhci.c
M src/drivers/wifi/generic/acpi.c
M src/drivers/wifi/generic/generic.c
M src/drivers/wifi/generic/smbios.c
M src/include/device/pci_ids.h
M src/mainboard/google/brya/variants/brya0/ramstage.c
M src/mainboard/google/hatch/variants/baseboard/mainboard.c
M src/mainboard/google/poppy/variants/atlas/mainboard.c
M src/mainboard/google/poppy/variants/nocturne/mainboard.c
M src/mainboard/intel/adlrvp/ramstage.c
M src/mainboard/lenovo/x60/mainboard.c
M src/mainboard/prodrive/hermes/devicetree.cb
M src/mainboard/siemens/mc_apl1/mainboard.c
M src/mainboard/siemens/mc_apl1/variants/mc_apl1/mainboard.c
M src/mainboard/siemens/mc_apl1/variants/mc_apl2/mainboard.c
M src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c
M src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c
M src/mainboard/siemens/mc_apl1/variants/mc_apl6/mainboard.c
M src/mainboard/siemens/mc_ehl/mainboard.c
M src/northbridge/amd/agesa/family14/northbridge.c
M src/northbridge/amd/agesa/family15tn/iommu.c
M src/northbridge/amd/agesa/family15tn/northbridge.c
M src/northbridge/amd/agesa/family16kb/northbridge.c
M src/northbridge/amd/pi/00730F01/iommu.c
M src/northbridge/amd/pi/00730F01/northbridge.c
M src/northbridge/intel/gm45/gma.c
M src/northbridge/intel/haswell/gma.c
M src/northbridge/intel/haswell/minihd.c
M src/northbridge/intel/haswell/northbridge.c
M src/northbridge/intel/haswell/pcie.c
M src/northbridge/intel/i440bx/northbridge.c
M src/northbridge/intel/i945/gma.c
M src/northbridge/intel/i945/northbridge.c
M src/northbridge/intel/ironlake/gma.c
M src/northbridge/intel/ironlake/northbridge.c
M src/northbridge/intel/pineview/gma.c
M src/northbridge/intel/sandybridge/gma.c
M src/northbridge/intel/sandybridge/northbridge.c
M src/northbridge/intel/sandybridge/pcie.c
M src/northbridge/intel/x4x/gma.c
M src/soc/amd/cezanne/data_fabric.c
M src/soc/amd/cezanne/root_complex.c
M src/soc/amd/common/block/acp/acp.c
M src/soc/amd/common/block/graphics/graphics.c
M src/soc/amd/common/block/hda/hda.c
M src/soc/amd/common/block/iommu/iommu.c
M src/soc/amd/common/block/lpc/lpc.c
M src/soc/amd/common/block/pci/pcie_gpp.c
M src/soc/amd/common/block/sata/sata.c
M src/soc/amd/common/block/smbus/sm.c
M src/soc/amd/picasso/data_fabric.c
M src/soc/amd/picasso/root_complex.c
M src/soc/amd/stoneyridge/include/soc/pci_devs.h
M src/soc/amd/stoneyridge/northbridge.c
M src/soc/amd/stoneyridge/usb.c
M src/soc/cavium/common/pci/uart.c
M src/soc/intel/alderlake/bootblock/report_platform.c
M src/soc/intel/alderlake/chip.h
M src/soc/intel/alderlake/cpu.c
M src/soc/intel/alderlake/fsp_params.c
M src/soc/intel/alderlake/vr_config.c
M src/soc/intel/apollolake/report_platform.c
M src/soc/intel/baytrail/ehci.c
M src/soc/intel/baytrail/emmc.c
M src/soc/intel/baytrail/gfx.c
M src/soc/intel/baytrail/hda.c
M src/soc/intel/baytrail/lpe.c
M src/soc/intel/baytrail/lpss.c
M src/soc/intel/baytrail/northcluster.c
M src/soc/intel/baytrail/pcie.c
M src/soc/intel/baytrail/sata.c
M src/soc/intel/baytrail/sd.c
M src/soc/intel/baytrail/southcluster.c
M src/soc/intel/baytrail/xhci.c
M src/soc/intel/braswell/emmc.c
M src/soc/intel/braswell/gfx.c
M src/soc/intel/braswell/lpe.c
M src/soc/intel/braswell/lpss.c
M src/soc/intel/braswell/northcluster.c
M src/soc/intel/braswell/pcie.c
M src/soc/intel/braswell/sata.c
M src/soc/intel/braswell/sd.c
M src/soc/intel/braswell/southcluster.c
M src/soc/intel/braswell/xhci.c
M src/soc/intel/broadwell/gma.c
M src/soc/intel/broadwell/minihd.c
M src/soc/intel/broadwell/northbridge.c
M src/soc/intel/broadwell/pch/adsp.c
M src/soc/intel/broadwell/pch/hda.c
M src/soc/intel/broadwell/pch/lpc.c
M src/soc/intel/broadwell/pch/me.c
M src/soc/intel/broadwell/pch/pcie.c
M src/soc/intel/broadwell/pch/sata.c
M src/soc/intel/broadwell/pch/serialio.c
M src/soc/intel/broadwell/pch/usb_ehci.c
M src/soc/intel/broadwell/pch/usb_xhci.c
M src/soc/intel/cannonlake/bootblock/report_platform.c
M src/soc/intel/cannonlake/vr_config.c
M src/soc/intel/common/block/cnvi/cnvi.c
M src/soc/intel/common/block/cse/cse.c
M src/soc/intel/common/block/dsp/dsp.c
M src/soc/intel/common/block/dtt/dtt.c
M src/soc/intel/common/block/graphics/graphics.c
M src/soc/intel/common/block/hda/hda.c
M src/soc/intel/common/block/i2c/i2c.c
M src/soc/intel/common/block/ipu/ipu.c
M src/soc/intel/common/block/lpc/lpc.c
M src/soc/intel/common/block/p2sb/p2sb.c
M src/soc/intel/common/block/pcie/pcie.c
M src/soc/intel/common/block/pmc/pmc.c
M src/soc/intel/common/block/sata/sata.c
M src/soc/intel/common/block/scs/mmc.c
M src/soc/intel/common/block/scs/sd.c
M src/soc/intel/common/block/smbus/smbus.c
M src/soc/intel/common/block/spi/spi.c
M src/soc/intel/common/block/sram/sram.c
M src/soc/intel/common/block/systemagent/systemagent.c
M src/soc/intel/common/block/uart/uart.c
M src/soc/intel/common/block/usb4/usb4.c
M src/soc/intel/common/block/usb4/xhci.c
M src/soc/intel/common/block/xdci/xdci.c
M src/soc/intel/common/block/xhci/xhci.c
M src/soc/intel/denverton_ns/csme_ie_kt.c
M src/soc/intel/denverton_ns/lpc.c
M src/soc/intel/denverton_ns/npk.c
M src/soc/intel/denverton_ns/pmc.c
M src/soc/intel/denverton_ns/sata.c
M src/soc/intel/denverton_ns/systemagent.c
M src/soc/intel/denverton_ns/uart.c
M src/soc/intel/denverton_ns/xhci.c
M src/soc/intel/elkhartlake/bootblock/report_platform.c
M src/soc/intel/icelake/bootblock/report_platform.c
M src/soc/intel/jasperlake/bootblock/report_platform.c
M src/soc/intel/quark/ehci.c
M src/soc/intel/quark/gpio_i2c.c
M src/soc/intel/quark/lpc.c
M src/soc/intel/quark/northcluster.c
M src/soc/intel/quark/sd.c
M src/soc/intel/quark/spi.c
M src/soc/intel/quark/uart.c
M src/soc/intel/skylake/bootblock/report_platform.c
M src/soc/intel/skylake/graphics.c
M src/soc/intel/skylake/vr_config.c
M src/soc/intel/tigerlake/bootblock/report_platform.c
M src/soc/intel/tigerlake/lpm.c
M src/soc/intel/tigerlake/systemagent.c
M src/soc/intel/xeon_sp/cpx/chip.c
M src/soc/intel/xeon_sp/uncore.c
M src/southbridge/amd/agesa/hudson/hda.c
M src/southbridge/amd/agesa/hudson/hudson.c
M src/southbridge/amd/agesa/hudson/ide.c
M src/southbridge/amd/agesa/hudson/lpc.c
M src/southbridge/amd/agesa/hudson/pci.c
M src/southbridge/amd/agesa/hudson/pcie.c
M src/southbridge/amd/agesa/hudson/sata.c
M src/southbridge/amd/agesa/hudson/sd.c
M src/southbridge/amd/agesa/hudson/sm.c
M src/southbridge/amd/agesa/hudson/usb.c
M src/southbridge/amd/cimx/sb800/late.c
M src/southbridge/amd/pi/hudson/hda.c
M src/southbridge/amd/pi/hudson/hudson.c
M src/southbridge/amd/pi/hudson/ide.c
M src/southbridge/amd/pi/hudson/lpc.c
M src/southbridge/amd/pi/hudson/pci.c
M src/southbridge/amd/pi/hudson/pcie.c
M src/southbridge/amd/pi/hudson/sata.c
M src/southbridge/amd/pi/hudson/sd.c
M src/southbridge/amd/pi/hudson/sm.c
M src/southbridge/amd/pi/hudson/usb.c
M src/southbridge/intel/bd82x6x/azalia.c
M src/southbridge/intel/bd82x6x/lpc.c
M src/southbridge/intel/bd82x6x/me.c
M src/southbridge/intel/bd82x6x/me_8.x.c
M src/southbridge/intel/bd82x6x/pci.c
M src/southbridge/intel/bd82x6x/pcie.c
M src/southbridge/intel/bd82x6x/sata.c
M src/southbridge/intel/bd82x6x/smbus.c
M src/southbridge/intel/bd82x6x/usb_ehci.c
M src/southbridge/intel/bd82x6x/usb_xhci.c
M src/southbridge/intel/common/early_smbus.c
M src/southbridge/intel/i82371eb/bootblock.c
M src/southbridge/intel/i82371eb/early_pm.c
M src/southbridge/intel/i82371eb/early_smbus.c
M src/southbridge/intel/i82371eb/ide.c
M src/southbridge/intel/i82371eb/isa.c
M src/southbridge/intel/i82371eb/smbus.c
M src/southbridge/intel/i82371eb/usb.c
M src/southbridge/intel/i82801dx/ac97.c
M src/southbridge/intel/i82801dx/ide.c
M src/southbridge/intel/i82801dx/lpc.c
M src/southbridge/intel/i82801dx/pci.c
M src/southbridge/intel/i82801dx/usb.c
M src/southbridge/intel/i82801dx/usb2.c
M src/southbridge/intel/i82801gx/ac97.c
M src/southbridge/intel/i82801gx/azalia.c
M src/southbridge/intel/i82801gx/ide.c
M src/southbridge/intel/i82801gx/lpc.c
M src/southbridge/intel/i82801gx/pci.c
M src/southbridge/intel/i82801gx/pcie.c
M src/southbridge/intel/i82801gx/sata.c
M src/southbridge/intel/i82801gx/smbus.c
M src/southbridge/intel/i82801gx/usb.c
M src/southbridge/intel/i82801gx/usb_ehci.c
M src/southbridge/intel/i82801ix/azalia.c
M src/southbridge/intel/i82801ix/lpc.c
M src/southbridge/intel/i82801ix/pci.c
M src/southbridge/intel/i82801ix/pcie.c
M src/southbridge/intel/i82801ix/sata.c
M src/southbridge/intel/i82801ix/smbus.c
M src/southbridge/intel/i82801ix/thermal.c
M src/southbridge/intel/i82801ix/usb_ehci.c
M src/southbridge/intel/i82801jx/azalia.c
M src/southbridge/intel/i82801jx/lpc.c
M src/southbridge/intel/i82801jx/pci.c
M src/southbridge/intel/i82801jx/pcie.c
M src/southbridge/intel/i82801jx/sata.c
M src/southbridge/intel/i82801jx/smbus.c
M src/southbridge/intel/i82801jx/thermal.c
M src/southbridge/intel/i82801jx/usb_ehci.c
M src/southbridge/intel/i82870/ioapic.c
M src/southbridge/intel/i82870/pcibridge.c
M src/southbridge/intel/ibexpeak/azalia.c
M src/southbridge/intel/ibexpeak/lpc.c
M src/southbridge/intel/ibexpeak/me.c
M src/southbridge/intel/ibexpeak/sata.c
M src/southbridge/intel/ibexpeak/smbus.c
M src/southbridge/intel/ibexpeak/thermal.c
M src/southbridge/intel/ibexpeak/usb_ehci.c
M src/southbridge/intel/lynxpoint/azalia.c
M src/southbridge/intel/lynxpoint/lpc.c
M src/southbridge/intel/lynxpoint/me.c
M src/southbridge/intel/lynxpoint/pcie.c
M src/southbridge/intel/lynxpoint/sata.c
M src/southbridge/intel/lynxpoint/serialio.c
M src/southbridge/intel/lynxpoint/smbus.c
M src/southbridge/intel/lynxpoint/usb_ehci.c
M src/southbridge/intel/lynxpoint/usb_xhci.c
M src/southbridge/ricoh/rl5c476/rl5c476.c
M src/southbridge/ti/pci1x2x/pci1x2x.c
M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Pci22.h
M src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/IndustryStandard/Pci22.h
254 files changed, 6,446 insertions(+), 6,446 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/39331/7

[build bot (Jenkins) (Code Review)]

Attention is currently required from: Raul Rangel, Patrick Rudolph, Mariusz Szafrański, Jonathan Zhang, Jason Glenesk, Anjaneya "Reddy" Chagam, Marshall Dawson, Johnny Lin, Tim Wawrzynczak, Christian Walter, Suresh Bellampalli, Michal Motyl, Tim Chu.
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39331 )

Change subject: src/*: Make PCI ID macro names shorter
......................................................................

Patch Set 7:

(10 comments)

File src/include/device/pci_ids.h:

Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133896):
https://review.coreboot.org/c/coreboot/+/39331/comment/9198a5e0_e4e3b639 
PS7, Line 150: #define PCI_DID_COMPAQ_TRIFLEX_IDE 	0xae33
please, no space before tabs

Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133896):
https://review.coreboot.org/c/coreboot/+/39331/comment/114a2ff8_dc7e90b5 
PS7, Line 1863: #define PCI_DID_CBOARDS_DAS1602_16 	0x0001
please, no space before tabs

Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133896):
https://review.coreboot.org/c/coreboot/+/39331/comment/b25afc8e_10d989ec 
PS7, Line 1945: #define PCI_DID_APPLICOM_PCIGENERIC 	0x0001
please, no space before tabs

Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133896):
https://review.coreboot.org/c/coreboot/+/39331/comment/795304d8_aeb68465 
PS7, Line 1947: #define PCI_DID_APPLICOM_PCI2000PFB 	0x0003
please, no space before tabs

Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133896):
https://review.coreboot.org/c/coreboot/+/39331/comment/6414571b_37923190 
PS7, Line 2097: #define PCI_VID_AKS		0x416c
'AKS' may be misspelled - perhaps 'ASK'?

Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133896):
https://review.coreboot.org/c/coreboot/+/39331/comment/2fd0e307_c3a8c181 
PS7, Line 2098: #define PCI_DID_AKS_ALADDINCARD	0x0100
'AKS' may be misspelled - perhaps 'ASK'?

Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133896):
https://review.coreboot.org/c/coreboot/+/39331/comment/124e1e5f_4b4b0c2d 
PS7, Line 2099: #define PCI_DID_AKS_CPC		0x0200
'AKS' may be misspelled - perhaps 'ASK'?

File src/soc/intel/skylake/vr_config.c:

Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133896):
https://review.coreboot.org/c/coreboot/+/39331/comment/5e9b6744_77e514fd 
PS7, Line 215: 		         (igd_id == PCI_DID_INTEL_KBL_GT3E_SULTM_2)) {
code indent should use tabs where possible

File src/southbridge/amd/agesa/hudson/hudson.c:

Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133896):
https://review.coreboot.org/c/coreboot/+/39331/comment/a80f5f18_557fb51a 
PS7, Line 66: 			else if (sd_device_id == PCI_DID_AMD_YANGTZE_SD) {
else should follow close brace '}'

File src/southbridge/amd/pi/hudson/hudson.c:

Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133896):
https://review.coreboot.org/c/coreboot/+/39331/comment/cd2bf9c0_6cf0e824 
PS7, Line 41: 			else if (sd_device_id == PCI_DID_AMD_YANGTZE_SD) {
else should follow close brace '}'

[Michael Niewöhner (Code Review)]

Attention is currently required from:  Felix Singer, Raul Rangel, Patrick Rudolph, Mariusz Szafrański, Jonathan Zhang, Jason Glenesk, Anjaneya "Reddy" Chagam, Marshall Dawson, Johnny Lin, Tim Wawrzynczak, Christian Walter, Suresh Bellampalli, Michal Motyl, Tim Chu.
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39331 )

Change subject: src/*: Make PCI ID macro names shorter
......................................................................

Patch Set 7: Code-Review+2

(1 comment)

Patchset:

PS7: 
Actually, I don't have a strong opinion on this

[build bot (Jenkins) (Code Review)]

Attention is currently required from: Raul Rangel, Patrick Rudolph, Mariusz Szafrański, Jonathan Zhang, Jason Glenesk, Anjaneya "Reddy" Chagam, Marshall Dawson, Johnny Lin, Tim Wawrzynczak, Christian Walter, Suresh Bellampalli, Michal Motyl, Tim Chu.
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39331 )

Change subject: src/*: Make PCI ID macro names shorter
......................................................................

Patch Set 8:

(10 comments)

File src/include/device/pci_ids.h:

Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133938):
https://review.coreboot.org/c/coreboot/+/39331/comment/08ca0b00_d475b74b 
PS8, Line 150: #define PCI_DID_COMPAQ_TRIFLEX_IDE 	0xae33
please, no space before tabs

Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133938):
https://review.coreboot.org/c/coreboot/+/39331/comment/4ff8018e_3590b0be 
PS8, Line 1863: #define PCI_DID_CBOARDS_DAS1602_16 	0x0001
please, no space before tabs

Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133938):
https://review.coreboot.org/c/coreboot/+/39331/comment/659b14da_adcd6bca 
PS8, Line 1945: #define PCI_DID_APPLICOM_PCIGENERIC 	0x0001
please, no space before tabs

Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133938):
https://review.coreboot.org/c/coreboot/+/39331/comment/48579d44_a85cbe61 
PS8, Line 1947: #define PCI_DID_APPLICOM_PCI2000PFB 	0x0003
please, no space before tabs

Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133938):
https://review.coreboot.org/c/coreboot/+/39331/comment/c8fb01ed_36f8f887 
PS8, Line 2097: #define PCI_VID_AKS		0x416c
'AKS' may be misspelled - perhaps 'ASK'?

Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133938):
https://review.coreboot.org/c/coreboot/+/39331/comment/e302c94d_afec166e 
PS8, Line 2098: #define PCI_DID_AKS_ALADDINCARD	0x0100
'AKS' may be misspelled - perhaps 'ASK'?

Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133938):
https://review.coreboot.org/c/coreboot/+/39331/comment/8efe9445_f4ac6b25 
PS8, Line 2099: #define PCI_DID_AKS_CPC		0x0200
'AKS' may be misspelled - perhaps 'ASK'?

File src/soc/intel/skylake/vr_config.c:

Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133938):
https://review.coreboot.org/c/coreboot/+/39331/comment/3297b751_8676279c 
PS8, Line 215: 		         (igd_id == PCI_DID_INTEL_KBL_GT3E_SULTM_2)) {
code indent should use tabs where possible

File src/southbridge/amd/agesa/hudson/hudson.c:

Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133938):
https://review.coreboot.org/c/coreboot/+/39331/comment/c9bc0f1b_10968985 
PS8, Line 66: 			else if (sd_device_id == PCI_DID_AMD_YANGTZE_SD) {
else should follow close brace '}'

File src/southbridge/amd/pi/hudson/hudson.c:

Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133938):
https://review.coreboot.org/c/coreboot/+/39331/comment/192ec1e6_7e597bbc 
PS8, Line 41: 			else if (sd_device_id == PCI_DID_AMD_YANGTZE_SD) {
else should follow close brace '}'

[Felix Singer (Code Review)]

Attention is currently required from: Raul Rangel, Patrick Rudolph, Mariusz Szafrański, Jonathan Zhang, Jason Glenesk, Anjaneya "Reddy" Chagam, Martin Roth, Marshall Dawson, Johnny Lin, Tim Wawrzynczak, Christian Walter, Suresh Bellampalli, Michal Motyl, Felix Held, Tim Chu.
 Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39331 )

Change subject: src/*: Make PCI ID macro names shorter
......................................................................

Patch Set 8:

(2 comments)

Commit Message:

https://review.coreboot.org/c/coreboot/+/39331/comment/09658a65_9183abd0 
PS1, Line 8: 
           : This patch shortens macro names containing PCI_{DEVICE,VENDOR}_ID_
           : with PCI_{DID,VID}_.
> Sounds like a good idea. […]

Done

File src/include/device/pci_ids.h:

PS5:
> since 6 chars get removed, the tab-alignement of the values is broken in some places. […]

I have tried to re-align them, but I think there is still much to do. IMO we should do a separate patch for that, so that this one can be merged.

[Angel Pons (Code Review)]

Attention is currently required from:  Felix Singer, Raul Rangel, Patrick Rudolph, Mariusz Szafrański, Jonathan Zhang, Paul Menzel, Jason Glenesk, Anjaneya "Reddy" Chagam, Martin Roth, Marshall Dawson, Johnny Lin, Tim Wawrzynczak, Christian Walter, Suresh Bellampalli, Michal Motyl, Felix Held, Tim Chu.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39331 )

Change subject: src/*: Make PCI ID macro names shorter
......................................................................

Patch Set 8:

(1 comment)

Patchset:

PS5:
> Yes, that’d be great.

As this is a treewide change, I'd bring it up in the ML and/or leadership meeting.

[Martin Roth (Code Review)]

Attention is currently required from: Felix Singer, Raul Rangel, Patrick Rudolph, Mariusz Szafrański, Jonathan Zhang, Paul Menzel, Angel Pons, Jason Glenesk, Anjaneya "Reddy" Chagam, Marshall Dawson, Johnny Lin, Tim Wawrzynczak, Christian Walter, Suresh Bellampalli, Michal Motyl, Felix Held, Tim Chu.
Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39331 )

Change subject: src/*: Make PCI ID macro names shorter
......................................................................

Patch Set 8:

(1 comment)

Patchset:

PS5:
> As this is a treewide change, I'd bring it up in the ML and/or leadership meeting.

This was agreed to in the leadership meeting.  Do you still plan on merging it?

[Felix Singer (Code Review)]

Attention is currently required from: Felix Singer, Raul Rangel, Patrick Rudolph, Mariusz Szafrański, Jonathan Zhang, Paul Menzel, Angel Pons, Jason Glenesk, Anjaneya "Reddy" Chagam, Marshall Dawson, Johnny Lin, Tim Wawrzynczak, Christian Walter, Suresh Bellampalli, Michal Motyl, Felix Held, Tim Chu.
Hello build bot (Jenkins), Raul Rangel, Patrick Rudolph, Mariusz Szafrański, Jonathan Zhang, Arthur Heymans, Andrey Petrov, Patrick Rudolph, Anjaneya "Reddy" Chagam, Nico Huber, David Guckian, Johnny Lin, Christian Walter, Suresh Bellampalli, Michal Motyl, Alexander Couzens, Werner Zeh, Tim Chu, Felix Held, Angel Pons, Michael Niewöhner, Jason Glenesk, Damien Zammit, Marshall Dawson, Tim Wawrzynczak, Vanessa Eusebio, David Guckian,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/39331

to look at the new patch set (#9).

Change subject: src/*: Make PCI ID macro names shorter
......................................................................

src/*: Make PCI ID macro names shorter

This patch shortens macro names containing PCI_{DEVICE,VENDOR}_ID_
with PCI_{DID,VID}_.

Used commands:
find -type f -exec sed -i 's/PCI_DEVICE_ID_/PCI_DID_/g' {} +
find -type f -exec sed -i 's/PCI_VENDOR_ID_/PCI_VID_/g' {} +

Change-Id: If9027700f53b6d0d3964c26a41a1f9b8f62be178
Signed-off-by: Felix Singer 
---
M src/device/pci_rom.c
M src/drivers/aspeed/ast2050/ast2050.c
M src/drivers/broadcom/bcm57xx_aspm_disable.c
M src/drivers/generic/bayhub/bh720.c
M src/drivers/generic/bayhub_lv2/lv2.c
M src/drivers/genesyslogic/gl9750/gl9750.c
M src/drivers/genesyslogic/gl9755/gl9755.c
M src/drivers/genesyslogic/gl9763e/gl9763e.c
M src/drivers/intel/gma/opregion.c
M src/drivers/intel/i210/i210.c
M src/drivers/intel/ish/ish.c
M src/drivers/net/r8168.c
M src/drivers/ricoh/rce822/rce822.c
M src/drivers/siemens/nc_fpga/nc_fpga.c
M src/drivers/siemens/nc_fpga/nc_fpga_early.c
M src/drivers/usb/pci_xhci/pci_xhci.c
M src/drivers/wifi/generic/acpi.c
M src/drivers/wifi/generic/generic.c
M src/drivers/wifi/generic/smbios.c
M src/include/device/pci_ids.h
M src/mainboard/google/brya/variants/brask/ramstage.c
M src/mainboard/google/brya/variants/brya0/ramstage.c
M src/mainboard/google/brya/variants/brya4es/ramstage.c
M src/mainboard/google/brya/variants/kano/ramstage.c
M src/mainboard/google/hatch/variants/baseboard/mainboard.c
M src/mainboard/google/poppy/variants/atlas/mainboard.c
M src/mainboard/google/poppy/variants/nocturne/mainboard.c
M src/mainboard/intel/adlrvp/ramstage.c
M src/mainboard/lenovo/x60/mainboard.c
M src/mainboard/prodrive/hermes/devicetree.cb
M src/mainboard/siemens/mc_apl1/mainboard.c
M src/mainboard/siemens/mc_apl1/variants/mc_apl1/mainboard.c
M src/mainboard/siemens/mc_apl1/variants/mc_apl2/mainboard.c
M src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c
M src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c
M src/mainboard/siemens/mc_apl1/variants/mc_apl6/mainboard.c
M src/mainboard/siemens/mc_ehl/mainboard.c
M src/northbridge/amd/agesa/family14/northbridge.c
M src/northbridge/amd/agesa/family15tn/iommu.c
M src/northbridge/amd/agesa/family15tn/northbridge.c
M src/northbridge/amd/agesa/family16kb/northbridge.c
M src/northbridge/amd/pi/00730F01/iommu.c
M src/northbridge/amd/pi/00730F01/northbridge.c
M src/northbridge/intel/gm45/gma.c
M src/northbridge/intel/haswell/gma.c
M src/northbridge/intel/haswell/minihd.c
M src/northbridge/intel/haswell/northbridge.c
M src/northbridge/intel/haswell/pcie.c
M src/northbridge/intel/i440bx/northbridge.c
M src/northbridge/intel/i945/gma.c
M src/northbridge/intel/i945/northbridge.c
M src/northbridge/intel/ironlake/gma.c
M src/northbridge/intel/ironlake/northbridge.c
M src/northbridge/intel/pineview/gma.c
M src/northbridge/intel/sandybridge/gma.c
M src/northbridge/intel/sandybridge/northbridge.c
M src/northbridge/intel/sandybridge/pcie.c
M src/northbridge/intel/x4x/gma.c
M src/soc/amd/cezanne/data_fabric.c
M src/soc/amd/cezanne/root_complex.c
M src/soc/amd/common/block/acp/acp.c
M src/soc/amd/common/block/graphics/graphics.c
M src/soc/amd/common/block/hda/hda.c
M src/soc/amd/common/block/iommu/iommu.c
M src/soc/amd/common/block/lpc/lpc.c
M src/soc/amd/common/block/pci/pcie_gpp.c
M src/soc/amd/common/block/sata/sata.c
M src/soc/amd/common/block/smbus/sm.c
M src/soc/amd/picasso/data_fabric.c
M src/soc/amd/picasso/root_complex.c
M src/soc/amd/sabrina/data_fabric.c
M src/soc/amd/sabrina/root_complex.c
M src/soc/amd/stoneyridge/include/soc/pci_devs.h
M src/soc/amd/stoneyridge/northbridge.c
M src/soc/amd/stoneyridge/usb.c
M src/soc/cavium/common/pci/uart.c
M src/soc/intel/alderlake/bootblock/report_platform.c
M src/soc/intel/alderlake/chip.h
M src/soc/intel/alderlake/cpu.c
M src/soc/intel/alderlake/fsp_params.c
M src/soc/intel/alderlake/vr_config.c
M src/soc/intel/apollolake/report_platform.c
M src/soc/intel/baytrail/ehci.c
M src/soc/intel/baytrail/emmc.c
M src/soc/intel/baytrail/gfx.c
M src/soc/intel/baytrail/hda.c
M src/soc/intel/baytrail/lpe.c
M src/soc/intel/baytrail/lpss.c
M src/soc/intel/baytrail/northcluster.c
M src/soc/intel/baytrail/pcie.c
M src/soc/intel/baytrail/sata.c
M src/soc/intel/baytrail/sd.c
M src/soc/intel/baytrail/southcluster.c
M src/soc/intel/baytrail/xhci.c
M src/soc/intel/braswell/emmc.c
M src/soc/intel/braswell/gfx.c
M src/soc/intel/braswell/lpe.c
M src/soc/intel/braswell/lpss.c
M src/soc/intel/braswell/northcluster.c
M src/soc/intel/braswell/pcie.c
M src/soc/intel/braswell/sata.c
M src/soc/intel/braswell/sd.c
M src/soc/intel/braswell/southcluster.c
M src/soc/intel/braswell/xhci.c
M src/soc/intel/broadwell/gma.c
M src/soc/intel/broadwell/minihd.c
M src/soc/intel/broadwell/northbridge.c
M src/soc/intel/broadwell/pch/adsp.c
M src/soc/intel/broadwell/pch/hda.c
M src/soc/intel/broadwell/pch/lpc.c
M src/soc/intel/broadwell/pch/me.c
M src/soc/intel/broadwell/pch/pcie.c
M src/soc/intel/broadwell/pch/sata.c
M src/soc/intel/broadwell/pch/serialio.c
M src/soc/intel/broadwell/pch/usb_ehci.c
M src/soc/intel/broadwell/pch/usb_xhci.c
M src/soc/intel/cannonlake/bootblock/report_platform.c
M src/soc/intel/cannonlake/vr_config.c
M src/soc/intel/common/block/cnvi/cnvi.c
M src/soc/intel/common/block/cse/cse.c
M src/soc/intel/common/block/dsp/dsp.c
M src/soc/intel/common/block/dtt/dtt.c
M src/soc/intel/common/block/graphics/graphics.c
M src/soc/intel/common/block/hda/hda.c
M src/soc/intel/common/block/i2c/i2c.c
M src/soc/intel/common/block/ipu/ipu.c
M src/soc/intel/common/block/lpc/lpc.c
M src/soc/intel/common/block/p2sb/p2sb.c
M src/soc/intel/common/block/pcie/pcie.c
M src/soc/intel/common/block/pmc/pmc.c
M src/soc/intel/common/block/sata/sata.c
M src/soc/intel/common/block/scs/mmc.c
M src/soc/intel/common/block/scs/sd.c
M src/soc/intel/common/block/smbus/smbus.c
M src/soc/intel/common/block/spi/spi.c
M src/soc/intel/common/block/sram/sram.c
M src/soc/intel/common/block/systemagent/systemagent.c
M src/soc/intel/common/block/uart/uart.c
M src/soc/intel/common/block/usb4/usb4.c
M src/soc/intel/common/block/usb4/xhci.c
M src/soc/intel/common/block/xdci/xdci.c
M src/soc/intel/common/block/xhci/xhci.c
M src/soc/intel/denverton_ns/csme_ie_kt.c
M src/soc/intel/denverton_ns/lpc.c
M src/soc/intel/denverton_ns/npk.c
M src/soc/intel/denverton_ns/pmc.c
M src/soc/intel/denverton_ns/sata.c
M src/soc/intel/denverton_ns/systemagent.c
M src/soc/intel/denverton_ns/uart.c
M src/soc/intel/denverton_ns/xhci.c
M src/soc/intel/elkhartlake/bootblock/report_platform.c
M src/soc/intel/icelake/bootblock/report_platform.c
M src/soc/intel/jasperlake/bootblock/report_platform.c
M src/soc/intel/quark/ehci.c
M src/soc/intel/quark/gpio_i2c.c
M src/soc/intel/quark/lpc.c
M src/soc/intel/quark/northcluster.c
M src/soc/intel/quark/sd.c
M src/soc/intel/quark/spi.c
M src/soc/intel/quark/uart.c
M src/soc/intel/skylake/bootblock/report_platform.c
M src/soc/intel/skylake/graphics.c
M src/soc/intel/skylake/vr_config.c
M src/soc/intel/tigerlake/bootblock/report_platform.c
M src/soc/intel/tigerlake/lpm.c
M src/soc/intel/tigerlake/systemagent.c
M src/soc/intel/xeon_sp/cpx/chip.c
M src/soc/intel/xeon_sp/uncore.c
M src/southbridge/amd/agesa/hudson/hda.c
M src/southbridge/amd/agesa/hudson/hudson.c
M src/southbridge/amd/agesa/hudson/ide.c
M src/southbridge/amd/agesa/hudson/lpc.c
M src/southbridge/amd/agesa/hudson/pci.c
M src/southbridge/amd/agesa/hudson/pcie.c
M src/southbridge/amd/agesa/hudson/sata.c
M src/southbridge/amd/agesa/hudson/sd.c
M src/southbridge/amd/agesa/hudson/sm.c
M src/southbridge/amd/agesa/hudson/usb.c
M src/southbridge/amd/cimx/sb800/late.c
M src/southbridge/amd/pi/hudson/hda.c
M src/southbridge/amd/pi/hudson/hudson.c
M src/southbridge/amd/pi/hudson/ide.c
M src/southbridge/amd/pi/hudson/lpc.c
M src/southbridge/amd/pi/hudson/pci.c
M src/southbridge/amd/pi/hudson/pcie.c
M src/southbridge/amd/pi/hudson/sata.c
M src/southbridge/amd/pi/hudson/sd.c
M src/southbridge/amd/pi/hudson/sm.c
M src/southbridge/amd/pi/hudson/usb.c
M src/southbridge/intel/bd82x6x/azalia.c
M src/southbridge/intel/bd82x6x/lpc.c
M src/southbridge/intel/bd82x6x/me.c
M src/southbridge/intel/bd82x6x/me_8.x.c
M src/southbridge/intel/bd82x6x/pci.c
M src/southbridge/intel/bd82x6x/pcie.c
M src/southbridge/intel/bd82x6x/sata.c
M src/southbridge/intel/bd82x6x/smbus.c
M src/southbridge/intel/bd82x6x/usb_ehci.c
M src/southbridge/intel/bd82x6x/usb_xhci.c
M src/southbridge/intel/common/early_smbus.c
M src/southbridge/intel/i82371eb/bootblock.c
M src/southbridge/intel/i82371eb/early_pm.c
M src/southbridge/intel/i82371eb/early_smbus.c
M src/southbridge/intel/i82371eb/ide.c
M src/southbridge/intel/i82371eb/isa.c
M src/southbridge/intel/i82371eb/smbus.c
M src/southbridge/intel/i82371eb/usb.c
M src/southbridge/intel/i82801dx/ac97.c
M src/southbridge/intel/i82801dx/ide.c
M src/southbridge/intel/i82801dx/lpc.c
M src/southbridge/intel/i82801dx/pci.c
M src/southbridge/intel/i82801dx/usb.c
M src/southbridge/intel/i82801dx/usb2.c
M src/southbridge/intel/i82801gx/ac97.c
M src/southbridge/intel/i82801gx/azalia.c
M src/southbridge/intel/i82801gx/ide.c
M src/southbridge/intel/i82801gx/lpc.c
M src/southbridge/intel/i82801gx/pci.c
M src/southbridge/intel/i82801gx/pcie.c
M src/southbridge/intel/i82801gx/sata.c
M src/southbridge/intel/i82801gx/smbus.c
M src/southbridge/intel/i82801gx/usb.c
M src/southbridge/intel/i82801gx/usb_ehci.c
M src/southbridge/intel/i82801ix/azalia.c
M src/southbridge/intel/i82801ix/lpc.c
M src/southbridge/intel/i82801ix/pci.c
M src/southbridge/intel/i82801ix/pcie.c
M src/southbridge/intel/i82801ix/sata.c
M src/southbridge/intel/i82801ix/smbus.c
M src/southbridge/intel/i82801ix/thermal.c
M src/southbridge/intel/i82801ix/usb_ehci.c
M src/southbridge/intel/i82801jx/azalia.c
M src/southbridge/intel/i82801jx/lpc.c
M src/southbridge/intel/i82801jx/pci.c
M src/southbridge/intel/i82801jx/pcie.c
M src/southbridge/intel/i82801jx/sata.c
M src/southbridge/intel/i82801jx/smbus.c
M src/southbridge/intel/i82801jx/thermal.c
M src/southbridge/intel/i82801jx/usb_ehci.c
M src/southbridge/intel/i82870/ioapic.c
M src/southbridge/intel/i82870/pcibridge.c
M src/southbridge/intel/ibexpeak/azalia.c
M src/southbridge/intel/ibexpeak/lpc.c
M src/southbridge/intel/ibexpeak/me.c
M src/southbridge/intel/ibexpeak/sata.c
M src/southbridge/intel/ibexpeak/smbus.c
M src/southbridge/intel/ibexpeak/thermal.c
M src/southbridge/intel/ibexpeak/usb_ehci.c
M src/southbridge/intel/lynxpoint/azalia.c
M src/southbridge/intel/lynxpoint/lpc.c
M src/southbridge/intel/lynxpoint/me.c
M src/southbridge/intel/lynxpoint/pcie.c
M src/southbridge/intel/lynxpoint/sata.c
M src/southbridge/intel/lynxpoint/serialio.c
M src/southbridge/intel/lynxpoint/smbus.c
M src/southbridge/intel/lynxpoint/usb_ehci.c
M src/southbridge/intel/lynxpoint/usb_xhci.c
M src/southbridge/ricoh/rl5c476/rl5c476.c
M src/southbridge/ti/pci1x2x/pci1x2x.c
M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Pci22.h
M src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/IndustryStandard/Pci22.h
M src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/Pci22.h
262 files changed, 6,614 insertions(+), 6,614 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/39331/9

[Felix Singer (Code Review)]

Attention is currently required from: Raul Rangel, Patrick Rudolph, Mariusz Szafrański, Jonathan Zhang, Paul Menzel, Angel Pons, Jason Glenesk, Anjaneya "Reddy" Chagam, Martin Roth, Marshall Dawson, Johnny Lin, Tim Wawrzynczak, Christian Walter, Suresh Bellampalli, Michal Motyl, Felix Held, Tim Chu.
Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39331 )

Change subject: src/*: Make PCI ID macro names shorter
......................................................................

Patch Set 9:

(1 comment)

Patchset:

PS5:
> This was agreed to in the leadership meeting. […]

Yes, just updated. I will create a follow-up patch to fix the indentations of pci_ids.h.

[Felix Singer (Code Review)]

Attention is currently required from: Raul Rangel, Patrick Rudolph, Mariusz Szafrański, Jonathan Zhang, Paul Menzel, Angel Pons, Jason Glenesk, Anjaneya "Reddy" Chagam, Martin Roth, Marshall Dawson, Johnny Lin, Tim Wawrzynczak, Christian Walter, Suresh Bellampalli, Michal Motyl, Felix Held, Tim Chu.
Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39331 )

Change subject: src/*: Make PCI ID macro names shorter
......................................................................

Patch Set 9:

(1 comment)

File src/include/device/pci_ids.h:

PS5:
> I have tried to re-align them, but I think there is still much to do. […]

I have created a follow-up patch to fix the indentations. Let's discuss it there CB:61531.

[build bot (Jenkins) (Code Review)]

Attention is currently required from: Raul Rangel, Patrick Rudolph, Mariusz Szafrański, Jonathan Zhang, Paul Menzel, Angel Pons, Jason Glenesk, Anjaneya "Reddy" Chagam, Martin Roth, Marshall Dawson, Johnny Lin, Tim Wawrzynczak, Christian Walter, Suresh Bellampalli, Michal Motyl, Felix Held, Tim Chu.
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39331 )

Change subject: src/*: Make PCI ID macro names shorter
......................................................................

Patch Set 9:

(6 comments)

File src/include/device/pci_ids.h:

Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-139657):
https://review.coreboot.org/c/coreboot/+/39331/comment/c12bcf09_35fcea35 
PS9, Line 2116: #define PCI_VID_AKS		0x416c
'AKS' may be misspelled - perhaps 'ASK'?

Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-139657):
https://review.coreboot.org/c/coreboot/+/39331/comment/d1b45eb8_365bb9e7 
PS9, Line 2117: #define PCI_DID_AKS_ALADDINCARD	0x0100
'AKS' may be misspelled - perhaps 'ASK'?

Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-139657):
https://review.coreboot.org/c/coreboot/+/39331/comment/d7521bab_01cca605 
PS9, Line 2118: #define PCI_DID_AKS_CPC		0x0200
'AKS' may be misspelled - perhaps 'ASK'?

File src/soc/intel/skylake/vr_config.c:

Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-139657):
https://review.coreboot.org/c/coreboot/+/39331/comment/0ddd92ae_9fde0859 
PS9, Line 215: 		         (igd_id == PCI_DID_INTEL_KBL_GT3E_SULTM_2)) {
code indent should use tabs where possible

File src/southbridge/amd/agesa/hudson/hudson.c:

Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-139657):
https://review.coreboot.org/c/coreboot/+/39331/comment/2b658efa_247bcfed 
PS9, Line 66: 			else if (sd_device_id == PCI_DID_AMD_YANGTZE_SD) {
else should follow close brace '}'

File src/southbridge/amd/pi/hudson/hudson.c:

Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-139657):
https://review.coreboot.org/c/coreboot/+/39331/comment/d0cf3cf4_5ed246c4 
PS9, Line 41: 			else if (sd_device_id == PCI_DID_AMD_YANGTZE_SD) {
else should follow close brace '}'

Change in coreboot[master]: src/*: Make PCI ID define names shorter

[Felix Singer (Code Review)]

Attention is currently required from: Raul Rangel, Patrick Rudolph, Mariusz Szafrański, Jonathan Zhang, Paul Menzel, Angel Pons, Jason Glenesk, Anjaneya "Reddy" Chagam, Martin Roth, Marshall Dawson, Johnny Lin, Tim Wawrzynczak, Christian Walter, Suresh Bellampalli, Michal Motyl, Felix Held, Tim Chu.
Hello build bot (Jenkins), Raul Rangel, Patrick Rudolph, Mariusz Szafrański, Jonathan Zhang, Arthur Heymans, Andrey Petrov, Patrick Rudolph, Anjaneya "Reddy" Chagam, Nico Huber, David Guckian, Johnny Lin, Christian Walter, Suresh Bellampalli, Michal Motyl, Alexander Couzens, Werner Zeh, Tim Chu, Felix Held, Angel Pons, Michael Niewöhner, Jason Glenesk, Damien Zammit, Marshall Dawson, Tim Wawrzynczak, Vanessa Eusebio, David Guckian,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/39331

to look at the new patch set (#10).

Change subject: src/*: Make PCI ID define names shorter
......................................................................

src/*: Make PCI ID define names shorter

This patch shortens macro names containing PCI_{DEVICE,VENDOR}_ID_
with PCI_{DID,VID}_.

Used commands:
find -type f -exec sed -i 's/PCI_DEVICE_ID_/PCI_DID_/g' {} +
find -type f -exec sed -i 's/PCI_VENDOR_ID_/PCI_VID_/g' {} +

Change-Id: If9027700f53b6d0d3964c26a41a1f9b8f62be178
Signed-off-by: Felix Singer 
---
M src/device/pci_rom.c
M src/drivers/aspeed/ast2050/ast2050.c
M src/drivers/broadcom/bcm57xx_aspm_disable.c
M src/drivers/generic/bayhub/bh720.c
M src/drivers/generic/bayhub_lv2/lv2.c
M src/drivers/genesyslogic/gl9750/gl9750.c
M src/drivers/genesyslogic/gl9755/gl9755.c
M src/drivers/genesyslogic/gl9763e/gl9763e.c
M src/drivers/intel/gma/opregion.c
M src/drivers/intel/i210/i210.c
M src/drivers/intel/ish/ish.c
M src/drivers/net/r8168.c
M src/drivers/ricoh/rce822/rce822.c
M src/drivers/siemens/nc_fpga/nc_fpga.c
M src/drivers/siemens/nc_fpga/nc_fpga_early.c
M src/drivers/usb/pci_xhci/pci_xhci.c
M src/drivers/wifi/generic/acpi.c
M src/drivers/wifi/generic/generic.c
M src/drivers/wifi/generic/smbios.c
M src/include/device/pci_ids.h
M src/mainboard/google/brya/variants/brask/ramstage.c
M src/mainboard/google/brya/variants/brya0/ramstage.c
M src/mainboard/google/brya/variants/brya4es/ramstage.c
M src/mainboard/google/brya/variants/kano/ramstage.c
M src/mainboard/google/hatch/variants/baseboard/mainboard.c
M src/mainboard/google/poppy/variants/atlas/mainboard.c
M src/mainboard/google/poppy/variants/nocturne/mainboard.c
M src/mainboard/intel/adlrvp/ramstage.c
M src/mainboard/lenovo/x60/mainboard.c
M src/mainboard/prodrive/hermes/devicetree.cb
M src/mainboard/siemens/mc_apl1/mainboard.c
M src/mainboard/siemens/mc_apl1/variants/mc_apl1/mainboard.c
M src/mainboard/siemens/mc_apl1/variants/mc_apl2/mainboard.c
M src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c
M src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c
M src/mainboard/siemens/mc_apl1/variants/mc_apl6/mainboard.c
M src/mainboard/siemens/mc_ehl/mainboard.c
M src/northbridge/amd/agesa/family14/northbridge.c
M src/northbridge/amd/agesa/family15tn/iommu.c
M src/northbridge/amd/agesa/family15tn/northbridge.c
M src/northbridge/amd/agesa/family16kb/northbridge.c
M src/northbridge/amd/pi/00730F01/iommu.c
M src/northbridge/amd/pi/00730F01/northbridge.c
M src/northbridge/intel/gm45/gma.c
M src/northbridge/intel/haswell/gma.c
M src/northbridge/intel/haswell/minihd.c
M src/northbridge/intel/haswell/northbridge.c
M src/northbridge/intel/haswell/pcie.c
M src/northbridge/intel/i440bx/northbridge.c
M src/northbridge/intel/i945/gma.c
M src/northbridge/intel/i945/northbridge.c
M src/northbridge/intel/ironlake/gma.c
M src/northbridge/intel/ironlake/northbridge.c
M src/northbridge/intel/pineview/gma.c
M src/northbridge/intel/sandybridge/gma.c
M src/northbridge/intel/sandybridge/northbridge.c
M src/northbridge/intel/sandybridge/pcie.c
M src/northbridge/intel/x4x/gma.c
M src/soc/amd/cezanne/data_fabric.c
M src/soc/amd/cezanne/root_complex.c
M src/soc/amd/common/block/acp/acp.c
M src/soc/amd/common/block/graphics/graphics.c
M src/soc/amd/common/block/hda/hda.c
M src/soc/amd/common/block/iommu/iommu.c
M src/soc/amd/common/block/lpc/lpc.c
M src/soc/amd/common/block/pci/pcie_gpp.c
M src/soc/amd/common/block/sata/sata.c
M src/soc/amd/common/block/smbus/sm.c
M src/soc/amd/picasso/data_fabric.c
M src/soc/amd/picasso/root_complex.c
M src/soc/amd/sabrina/data_fabric.c
M src/soc/amd/sabrina/root_complex.c
M src/soc/amd/stoneyridge/include/soc/pci_devs.h
M src/soc/amd/stoneyridge/northbridge.c
M src/soc/amd/stoneyridge/usb.c
M src/soc/cavium/common/pci/uart.c
M src/soc/intel/alderlake/bootblock/report_platform.c
M src/soc/intel/alderlake/chip.h
M src/soc/intel/alderlake/cpu.c
M src/soc/intel/alderlake/fsp_params.c
M src/soc/intel/alderlake/vr_config.c
M src/soc/intel/apollolake/report_platform.c
M src/soc/intel/baytrail/ehci.c
M src/soc/intel/baytrail/emmc.c
M src/soc/intel/baytrail/gfx.c
M src/soc/intel/baytrail/hda.c
M src/soc/intel/baytrail/lpe.c
M src/soc/intel/baytrail/lpss.c
M src/soc/intel/baytrail/northcluster.c
M src/soc/intel/baytrail/pcie.c
M src/soc/intel/baytrail/sata.c
M src/soc/intel/baytrail/sd.c
M src/soc/intel/baytrail/southcluster.c
M src/soc/intel/baytrail/xhci.c
M src/soc/intel/braswell/emmc.c
M src/soc/intel/braswell/gfx.c
M src/soc/intel/braswell/lpe.c
M src/soc/intel/braswell/lpss.c
M src/soc/intel/braswell/northcluster.c
M src/soc/intel/braswell/pcie.c
M src/soc/intel/braswell/sata.c
M src/soc/intel/braswell/sd.c
M src/soc/intel/braswell/southcluster.c
M src/soc/intel/braswell/xhci.c
M src/soc/intel/broadwell/gma.c
M src/soc/intel/broadwell/minihd.c
M src/soc/intel/broadwell/northbridge.c
M src/soc/intel/broadwell/pch/adsp.c
M src/soc/intel/broadwell/pch/hda.c
M src/soc/intel/broadwell/pch/lpc.c
M src/soc/intel/broadwell/pch/me.c
M src/soc/intel/broadwell/pch/pcie.c
M src/soc/intel/broadwell/pch/sata.c
M src/soc/intel/broadwell/pch/serialio.c
M src/soc/intel/broadwell/pch/usb_ehci.c
M src/soc/intel/broadwell/pch/usb_xhci.c
M src/soc/intel/cannonlake/bootblock/report_platform.c
M src/soc/intel/cannonlake/vr_config.c
M src/soc/intel/common/block/cnvi/cnvi.c
M src/soc/intel/common/block/cse/cse.c
M src/soc/intel/common/block/dsp/dsp.c
M src/soc/intel/common/block/dtt/dtt.c
M src/soc/intel/common/block/graphics/graphics.c
M src/soc/intel/common/block/hda/hda.c
M src/soc/intel/common/block/i2c/i2c.c
M src/soc/intel/common/block/ipu/ipu.c
M src/soc/intel/common/block/lpc/lpc.c
M src/soc/intel/common/block/p2sb/p2sb.c
M src/soc/intel/common/block/pcie/pcie.c
M src/soc/intel/common/block/pmc/pmc.c
M src/soc/intel/common/block/sata/sata.c
M src/soc/intel/common/block/scs/mmc.c
M src/soc/intel/common/block/scs/sd.c
M src/soc/intel/common/block/smbus/smbus.c
M src/soc/intel/common/block/spi/spi.c
M src/soc/intel/common/block/sram/sram.c
M src/soc/intel/common/block/systemagent/systemagent.c
M src/soc/intel/common/block/uart/uart.c
M src/soc/intel/common/block/usb4/usb4.c
M src/soc/intel/common/block/usb4/xhci.c
M src/soc/intel/common/block/xdci/xdci.c
M src/soc/intel/common/block/xhci/xhci.c
M src/soc/intel/denverton_ns/csme_ie_kt.c
M src/soc/intel/denverton_ns/lpc.c
M src/soc/intel/denverton_ns/npk.c
M src/soc/intel/denverton_ns/pmc.c
M src/soc/intel/denverton_ns/sata.c
M src/soc/intel/denverton_ns/systemagent.c
M src/soc/intel/denverton_ns/uart.c
M src/soc/intel/denverton_ns/xhci.c
M src/soc/intel/elkhartlake/bootblock/report_platform.c
M src/soc/intel/icelake/bootblock/report_platform.c
M src/soc/intel/jasperlake/bootblock/report_platform.c
M src/soc/intel/quark/ehci.c
M src/soc/intel/quark/gpio_i2c.c
M src/soc/intel/quark/lpc.c
M src/soc/intel/quark/northcluster.c
M src/soc/intel/quark/sd.c
M src/soc/intel/quark/spi.c
M src/soc/intel/quark/uart.c
M src/soc/intel/skylake/bootblock/report_platform.c
M src/soc/intel/skylake/graphics.c
M src/soc/intel/skylake/vr_config.c
M src/soc/intel/tigerlake/bootblock/report_platform.c
M src/soc/intel/tigerlake/lpm.c
M src/soc/intel/tigerlake/systemagent.c
M src/soc/intel/xeon_sp/cpx/chip.c
M src/soc/intel/xeon_sp/uncore.c
M src/southbridge/amd/agesa/hudson/hda.c
M src/southbridge/amd/agesa/hudson/hudson.c
M src/southbridge/amd/agesa/hudson/ide.c
M src/southbridge/amd/agesa/hudson/lpc.c
M src/southbridge/amd/agesa/hudson/pci.c
M src/southbridge/amd/agesa/hudson/pcie.c
M src/southbridge/amd/agesa/hudson/sata.c
M src/southbridge/amd/agesa/hudson/sd.c
M src/southbridge/amd/agesa/hudson/sm.c
M src/southbridge/amd/agesa/hudson/usb.c
M src/southbridge/amd/cimx/sb800/late.c
M src/southbridge/amd/pi/hudson/hda.c
M src/southbridge/amd/pi/hudson/hudson.c
M src/southbridge/amd/pi/hudson/ide.c
M src/southbridge/amd/pi/hudson/lpc.c
M src/southbridge/amd/pi/hudson/pci.c
M src/southbridge/amd/pi/hudson/pcie.c
M src/southbridge/amd/pi/hudson/sata.c
M src/southbridge/amd/pi/hudson/sd.c
M src/southbridge/amd/pi/hudson/sm.c
M src/southbridge/amd/pi/hudson/usb.c
M src/southbridge/intel/bd82x6x/azalia.c
M src/southbridge/intel/bd82x6x/lpc.c
M src/southbridge/intel/bd82x6x/me.c
M src/southbridge/intel/bd82x6x/me_8.x.c
M src/southbridge/intel/bd82x6x/pci.c
M src/southbridge/intel/bd82x6x/pcie.c
M src/southbridge/intel/bd82x6x/sata.c
M src/southbridge/intel/bd82x6x/smbus.c
M src/southbridge/intel/bd82x6x/usb_ehci.c
M src/southbridge/intel/bd82x6x/usb_xhci.c
M src/southbridge/intel/common/early_smbus.c
M src/southbridge/intel/i82371eb/bootblock.c
M src/southbridge/intel/i82371eb/early_pm.c
M src/southbridge/intel/i82371eb/early_smbus.c
M src/southbridge/intel/i82371eb/ide.c
M src/southbridge/intel/i82371eb/isa.c
M src/southbridge/intel/i82371eb/smbus.c
M src/southbridge/intel/i82371eb/usb.c
M src/southbridge/intel/i82801dx/ac97.c
M src/southbridge/intel/i82801dx/ide.c
M src/southbridge/intel/i82801dx/lpc.c
M src/southbridge/intel/i82801dx/pci.c
M src/southbridge/intel/i82801dx/usb.c
M src/southbridge/intel/i82801dx/usb2.c
M src/southbridge/intel/i82801gx/ac97.c
M src/southbridge/intel/i82801gx/azalia.c
M src/southbridge/intel/i82801gx/ide.c
M src/southbridge/intel/i82801gx/lpc.c
M src/southbridge/intel/i82801gx/pci.c
M src/southbridge/intel/i82801gx/pcie.c
M src/southbridge/intel/i82801gx/sata.c
M src/southbridge/intel/i82801gx/smbus.c
M src/southbridge/intel/i82801gx/usb.c
M src/southbridge/intel/i82801gx/usb_ehci.c
M src/southbridge/intel/i82801ix/azalia.c
M src/southbridge/intel/i82801ix/lpc.c
M src/southbridge/intel/i82801ix/pci.c
M src/southbridge/intel/i82801ix/pcie.c
M src/southbridge/intel/i82801ix/sata.c
M src/southbridge/intel/i82801ix/smbus.c
M src/southbridge/intel/i82801ix/thermal.c
M src/southbridge/intel/i82801ix/usb_ehci.c
M src/southbridge/intel/i82801jx/azalia.c
M src/southbridge/intel/i82801jx/lpc.c
M src/southbridge/intel/i82801jx/pci.c
M src/southbridge/intel/i82801jx/pcie.c
M src/southbridge/intel/i82801jx/sata.c
M src/southbridge/intel/i82801jx/smbus.c
M src/southbridge/intel/i82801jx/thermal.c
M src/southbridge/intel/i82801jx/usb_ehci.c
M src/southbridge/intel/i82870/ioapic.c
M src/southbridge/intel/i82870/pcibridge.c
M src/southbridge/intel/ibexpeak/azalia.c
M src/southbridge/intel/ibexpeak/lpc.c
M src/southbridge/intel/ibexpeak/me.c
M src/southbridge/intel/ibexpeak/sata.c
M src/southbridge/intel/ibexpeak/smbus.c
M src/southbridge/intel/ibexpeak/thermal.c
M src/southbridge/intel/ibexpeak/usb_ehci.c
M src/southbridge/intel/lynxpoint/azalia.c
M src/southbridge/intel/lynxpoint/lpc.c
M src/southbridge/intel/lynxpoint/me.c
M src/southbridge/intel/lynxpoint/pcie.c
M src/southbridge/intel/lynxpoint/sata.c
M src/southbridge/intel/lynxpoint/serialio.c
M src/southbridge/intel/lynxpoint/smbus.c
M src/southbridge/intel/lynxpoint/usb_ehci.c
M src/southbridge/intel/lynxpoint/usb_xhci.c
M src/southbridge/ricoh/rl5c476/rl5c476.c
M src/southbridge/ti/pci1x2x/pci1x2x.c
M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Pci22.h
M src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/IndustryStandard/Pci22.h
M src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/Pci22.h
262 files changed, 6,614 insertions(+), 6,614 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/39331/10

Change in coreboot[master]: src: Make PCI ID define names shorter

[Felix Singer (Code Review)]

Attention is currently required from: Raul Rangel, Patrick Rudolph, Mariusz Szafrański, Jonathan Zhang, Paul Menzel, Angel Pons, Jason Glenesk, Anjaneya "Reddy" Chagam, Martin Roth, Marshall Dawson, Johnny Lin, Tim Wawrzynczak, Christian Walter, Suresh Bellampalli, Michal Motyl, Felix Held, Tim Chu.
Hello build bot (Jenkins), Raul Rangel, Patrick Rudolph, Mariusz Szafrański, Jonathan Zhang, Arthur Heymans, Andrey Petrov, Patrick Rudolph, Anjaneya "Reddy" Chagam, Nico Huber, David Guckian, Johnny Lin, Christian Walter, Suresh Bellampalli, Michal Motyl, Alexander Couzens, Werner Zeh, Tim Chu, Felix Held, Angel Pons, Michael Niewöhner, Jason Glenesk, Damien Zammit, Marshall Dawson, Tim Wawrzynczak, Vanessa Eusebio, David Guckian,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/39331

to look at the new patch set (#11).

Change subject: src: Make PCI ID define names shorter
......................................................................

src: Make PCI ID define names shorter

This patch shortens macro names containing PCI_{DEVICE,VENDOR}_ID_
with PCI_{DID,VID}_.

Used commands:
find -type f -exec sed -i 's/PCI_DEVICE_ID_/PCI_DID_/g' {} +
find -type f -exec sed -i 's/PCI_VENDOR_ID_/PCI_VID_/g' {} +

Change-Id: If9027700f53b6d0d3964c26a41a1f9b8f62be178
Signed-off-by: Felix Singer 
---
M src/device/pci_rom.c
M src/drivers/aspeed/ast2050/ast2050.c
M src/drivers/broadcom/bcm57xx_aspm_disable.c
M src/drivers/generic/bayhub/bh720.c
M src/drivers/generic/bayhub_lv2/lv2.c
M src/drivers/genesyslogic/gl9750/gl9750.c
M src/drivers/genesyslogic/gl9755/gl9755.c
M src/drivers/genesyslogic/gl9763e/gl9763e.c
M src/drivers/intel/gma/opregion.c
M src/drivers/intel/i210/i210.c
M src/drivers/intel/ish/ish.c
M src/drivers/net/r8168.c
M src/drivers/ricoh/rce822/rce822.c
M src/drivers/siemens/nc_fpga/nc_fpga.c
M src/drivers/siemens/nc_fpga/nc_fpga_early.c
M src/drivers/usb/pci_xhci/pci_xhci.c
M src/drivers/wifi/generic/acpi.c
M src/drivers/wifi/generic/generic.c
M src/drivers/wifi/generic/smbios.c
M src/include/device/pci_ids.h
M src/mainboard/google/brya/variants/brask/ramstage.c
M src/mainboard/google/brya/variants/brya0/ramstage.c
M src/mainboard/google/brya/variants/brya4es/ramstage.c
M src/mainboard/google/brya/variants/kano/ramstage.c
M src/mainboard/google/hatch/variants/baseboard/mainboard.c
M src/mainboard/google/poppy/variants/atlas/mainboard.c
M src/mainboard/google/poppy/variants/nocturne/mainboard.c
M src/mainboard/intel/adlrvp/ramstage.c
M src/mainboard/lenovo/x60/mainboard.c
M src/mainboard/prodrive/hermes/devicetree.cb
M src/mainboard/siemens/mc_apl1/mainboard.c
M src/mainboard/siemens/mc_apl1/variants/mc_apl1/mainboard.c
M src/mainboard/siemens/mc_apl1/variants/mc_apl2/mainboard.c
M src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c
M src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c
M src/mainboard/siemens/mc_apl1/variants/mc_apl6/mainboard.c
M src/mainboard/siemens/mc_ehl/mainboard.c
M src/northbridge/amd/agesa/family14/northbridge.c
M src/northbridge/amd/agesa/family15tn/iommu.c
M src/northbridge/amd/agesa/family15tn/northbridge.c
M src/northbridge/amd/agesa/family16kb/northbridge.c
M src/northbridge/amd/pi/00730F01/iommu.c
M src/northbridge/amd/pi/00730F01/northbridge.c
M src/northbridge/intel/gm45/gma.c
M src/northbridge/intel/haswell/gma.c
M src/northbridge/intel/haswell/minihd.c
M src/northbridge/intel/haswell/northbridge.c
M src/northbridge/intel/haswell/pcie.c
M src/northbridge/intel/i440bx/northbridge.c
M src/northbridge/intel/i945/gma.c
M src/northbridge/intel/i945/northbridge.c
M src/northbridge/intel/ironlake/gma.c
M src/northbridge/intel/ironlake/northbridge.c
M src/northbridge/intel/pineview/gma.c
M src/northbridge/intel/sandybridge/gma.c
M src/northbridge/intel/sandybridge/northbridge.c
M src/northbridge/intel/sandybridge/pcie.c
M src/northbridge/intel/x4x/gma.c
M src/soc/amd/cezanne/data_fabric.c
M src/soc/amd/cezanne/root_complex.c
M src/soc/amd/common/block/acp/acp.c
M src/soc/amd/common/block/graphics/graphics.c
M src/soc/amd/common/block/hda/hda.c
M src/soc/amd/common/block/iommu/iommu.c
M src/soc/amd/common/block/lpc/lpc.c
M src/soc/amd/common/block/pci/pcie_gpp.c
M src/soc/amd/common/block/sata/sata.c
M src/soc/amd/common/block/smbus/sm.c
M src/soc/amd/picasso/data_fabric.c
M src/soc/amd/picasso/root_complex.c
M src/soc/amd/sabrina/data_fabric.c
M src/soc/amd/sabrina/root_complex.c
M src/soc/amd/stoneyridge/include/soc/pci_devs.h
M src/soc/amd/stoneyridge/northbridge.c
M src/soc/amd/stoneyridge/usb.c
M src/soc/cavium/common/pci/uart.c
M src/soc/intel/alderlake/bootblock/report_platform.c
M src/soc/intel/alderlake/chip.h
M src/soc/intel/alderlake/cpu.c
M src/soc/intel/alderlake/fsp_params.c
M src/soc/intel/alderlake/vr_config.c
M src/soc/intel/apollolake/report_platform.c
M src/soc/intel/baytrail/ehci.c
M src/soc/intel/baytrail/emmc.c
M src/soc/intel/baytrail/gfx.c
M src/soc/intel/baytrail/hda.c
M src/soc/intel/baytrail/lpe.c
M src/soc/intel/baytrail/lpss.c
M src/soc/intel/baytrail/northcluster.c
M src/soc/intel/baytrail/pcie.c
M src/soc/intel/baytrail/sata.c
M src/soc/intel/baytrail/sd.c
M src/soc/intel/baytrail/southcluster.c
M src/soc/intel/baytrail/xhci.c
M src/soc/intel/braswell/emmc.c
M src/soc/intel/braswell/gfx.c
M src/soc/intel/braswell/lpe.c
M src/soc/intel/braswell/lpss.c
M src/soc/intel/braswell/northcluster.c
M src/soc/intel/braswell/pcie.c
M src/soc/intel/braswell/sata.c
M src/soc/intel/braswell/sd.c
M src/soc/intel/braswell/southcluster.c
M src/soc/intel/braswell/xhci.c
M src/soc/intel/broadwell/gma.c
M src/soc/intel/broadwell/minihd.c
M src/soc/intel/broadwell/northbridge.c
M src/soc/intel/broadwell/pch/adsp.c
M src/soc/intel/broadwell/pch/hda.c
M src/soc/intel/broadwell/pch/lpc.c
M src/soc/intel/broadwell/pch/me.c
M src/soc/intel/broadwell/pch/pcie.c
M src/soc/intel/broadwell/pch/sata.c
M src/soc/intel/broadwell/pch/serialio.c
M src/soc/intel/broadwell/pch/usb_ehci.c
M src/soc/intel/broadwell/pch/usb_xhci.c
M src/soc/intel/cannonlake/bootblock/report_platform.c
M src/soc/intel/cannonlake/vr_config.c
M src/soc/intel/common/block/cnvi/cnvi.c
M src/soc/intel/common/block/cse/cse.c
M src/soc/intel/common/block/dsp/dsp.c
M src/soc/intel/common/block/dtt/dtt.c
M src/soc/intel/common/block/graphics/graphics.c
M src/soc/intel/common/block/hda/hda.c
M src/soc/intel/common/block/i2c/i2c.c
M src/soc/intel/common/block/ipu/ipu.c
M src/soc/intel/common/block/lpc/lpc.c
M src/soc/intel/common/block/p2sb/p2sb.c
M src/soc/intel/common/block/pcie/pcie.c
M src/soc/intel/common/block/pmc/pmc.c
M src/soc/intel/common/block/sata/sata.c
M src/soc/intel/common/block/scs/mmc.c
M src/soc/intel/common/block/scs/sd.c
M src/soc/intel/common/block/smbus/smbus.c
M src/soc/intel/common/block/spi/spi.c
M src/soc/intel/common/block/sram/sram.c
M src/soc/intel/common/block/systemagent/systemagent.c
M src/soc/intel/common/block/uart/uart.c
M src/soc/intel/common/block/usb4/usb4.c
M src/soc/intel/common/block/usb4/xhci.c
M src/soc/intel/common/block/xdci/xdci.c
M src/soc/intel/common/block/xhci/xhci.c
M src/soc/intel/denverton_ns/csme_ie_kt.c
M src/soc/intel/denverton_ns/lpc.c
M src/soc/intel/denverton_ns/npk.c
M src/soc/intel/denverton_ns/pmc.c
M src/soc/intel/denverton_ns/sata.c
M src/soc/intel/denverton_ns/systemagent.c
M src/soc/intel/denverton_ns/uart.c
M src/soc/intel/denverton_ns/xhci.c
M src/soc/intel/elkhartlake/bootblock/report_platform.c
M src/soc/intel/icelake/bootblock/report_platform.c
M src/soc/intel/jasperlake/bootblock/report_platform.c
M src/soc/intel/quark/ehci.c
M src/soc/intel/quark/gpio_i2c.c
M src/soc/intel/quark/lpc.c
M src/soc/intel/quark/northcluster.c
M src/soc/intel/quark/sd.c
M src/soc/intel/quark/spi.c
M src/soc/intel/quark/uart.c
M src/soc/intel/skylake/bootblock/report_platform.c
M src/soc/intel/skylake/graphics.c
M src/soc/intel/skylake/vr_config.c
M src/soc/intel/tigerlake/bootblock/report_platform.c
M src/soc/intel/tigerlake/lpm.c
M src/soc/intel/tigerlake/systemagent.c
M src/soc/intel/xeon_sp/cpx/chip.c
M src/soc/intel/xeon_sp/uncore.c
M src/southbridge/amd/agesa/hudson/hda.c
M src/southbridge/amd/agesa/hudson/hudson.c
M src/southbridge/amd/agesa/hudson/ide.c
M src/southbridge/amd/agesa/hudson/lpc.c
M src/southbridge/amd/agesa/hudson/pci.c
M src/southbridge/amd/agesa/hudson/pcie.c
M src/southbridge/amd/agesa/hudson/sata.c
M src/southbridge/amd/agesa/hudson/sd.c
M src/southbridge/amd/agesa/hudson/sm.c
M src/southbridge/amd/agesa/hudson/usb.c
M src/southbridge/amd/cimx/sb800/late.c
M src/southbridge/amd/pi/hudson/hda.c
M src/southbridge/amd/pi/hudson/hudson.c
M src/southbridge/amd/pi/hudson/ide.c
M src/southbridge/amd/pi/hudson/lpc.c
M src/southbridge/amd/pi/hudson/pci.c
M src/southbridge/amd/pi/hudson/pcie.c
M src/southbridge/amd/pi/hudson/sata.c
M src/southbridge/amd/pi/hudson/sd.c
M src/southbridge/amd/pi/hudson/sm.c
M src/southbridge/amd/pi/hudson/usb.c
M src/southbridge/intel/bd82x6x/azalia.c
M src/southbridge/intel/bd82x6x/lpc.c
M src/southbridge/intel/bd82x6x/me.c
M src/southbridge/intel/bd82x6x/me_8.x.c
M src/southbridge/intel/bd82x6x/pci.c
M src/southbridge/intel/bd82x6x/pcie.c
M src/southbridge/intel/bd82x6x/sata.c
M src/southbridge/intel/bd82x6x/smbus.c
M src/southbridge/intel/bd82x6x/usb_ehci.c
M src/southbridge/intel/bd82x6x/usb_xhci.c
M src/southbridge/intel/common/early_smbus.c
M src/southbridge/intel/i82371eb/bootblock.c
M src/southbridge/intel/i82371eb/early_pm.c
M src/southbridge/intel/i82371eb/early_smbus.c
M src/southbridge/intel/i82371eb/ide.c
M src/southbridge/intel/i82371eb/isa.c
M src/southbridge/intel/i82371eb/smbus.c
M src/southbridge/intel/i82371eb/usb.c
M src/southbridge/intel/i82801dx/ac97.c
M src/southbridge/intel/i82801dx/ide.c
M src/southbridge/intel/i82801dx/lpc.c
M src/southbridge/intel/i82801dx/pci.c
M src/southbridge/intel/i82801dx/usb.c
M src/southbridge/intel/i82801dx/usb2.c
M src/southbridge/intel/i82801gx/ac97.c
M src/southbridge/intel/i82801gx/azalia.c
M src/southbridge/intel/i82801gx/ide.c
M src/southbridge/intel/i82801gx/lpc.c
M src/southbridge/intel/i82801gx/pci.c
M src/southbridge/intel/i82801gx/pcie.c
M src/southbridge/intel/i82801gx/sata.c
M src/southbridge/intel/i82801gx/smbus.c
M src/southbridge/intel/i82801gx/usb.c
M src/southbridge/intel/i82801gx/usb_ehci.c
M src/southbridge/intel/i82801ix/azalia.c
M src/southbridge/intel/i82801ix/lpc.c
M src/southbridge/intel/i82801ix/pci.c
M src/southbridge/intel/i82801ix/pcie.c
M src/southbridge/intel/i82801ix/sata.c
M src/southbridge/intel/i82801ix/smbus.c
M src/southbridge/intel/i82801ix/thermal.c
M src/southbridge/intel/i82801ix/usb_ehci.c
M src/southbridge/intel/i82801jx/azalia.c
M src/southbridge/intel/i82801jx/lpc.c
M src/southbridge/intel/i82801jx/pci.c
M src/southbridge/intel/i82801jx/pcie.c
M src/southbridge/intel/i82801jx/sata.c
M src/southbridge/intel/i82801jx/smbus.c
M src/southbridge/intel/i82801jx/thermal.c
M src/southbridge/intel/i82801jx/usb_ehci.c
M src/southbridge/intel/i82870/ioapic.c
M src/southbridge/intel/i82870/pcibridge.c
M src/southbridge/intel/ibexpeak/azalia.c
M src/southbridge/intel/ibexpeak/lpc.c
M src/southbridge/intel/ibexpeak/me.c
M src/southbridge/intel/ibexpeak/sata.c
M src/southbridge/intel/ibexpeak/smbus.c
M src/southbridge/intel/ibexpeak/thermal.c
M src/southbridge/intel/ibexpeak/usb_ehci.c
M src/southbridge/intel/lynxpoint/azalia.c
M src/southbridge/intel/lynxpoint/lpc.c
M src/southbridge/intel/lynxpoint/me.c
M src/southbridge/intel/lynxpoint/pcie.c
M src/southbridge/intel/lynxpoint/sata.c
M src/southbridge/intel/lynxpoint/serialio.c
M src/southbridge/intel/lynxpoint/smbus.c
M src/southbridge/intel/lynxpoint/usb_ehci.c
M src/southbridge/intel/lynxpoint/usb_xhci.c
M src/southbridge/ricoh/rl5c476/rl5c476.c
M src/southbridge/ti/pci1x2x/pci1x2x.c
M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Pci22.h
M src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/IndustryStandard/Pci22.h
M src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/Pci22.h
262 files changed, 6,614 insertions(+), 6,614 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/39331/11

Change in coreboot[master]: src: Make PCI ID define names shorter

[Felix Singer (Code Review)]

Attention is currently required from: Raul Rangel, Patrick Rudolph, Mariusz Szafrański, Jonathan Zhang, Paul Menzel, Angel Pons, Jason Glenesk, Anjaneya "Reddy" Chagam, Martin Roth, Marshall Dawson, Johnny Lin, Tim Wawrzynczak, Christian Walter, Suresh Bellampalli, Michal Motyl, Felix Held, Tim Chu.
Hello build bot (Jenkins), Raul Rangel, Patrick Rudolph, Mariusz Szafrański, Jonathan Zhang, Arthur Heymans, Andrey Petrov, Patrick Rudolph, Anjaneya "Reddy" Chagam, Nico Huber, David Guckian, Johnny Lin, Christian Walter, Suresh Bellampalli, Michal Motyl, Alexander Couzens, Werner Zeh, Tim Chu, Felix Held, Angel Pons, Michael Niewöhner, Jason Glenesk, Damien Zammit, Marshall Dawson, Tim Wawrzynczak, Vanessa Eusebio, David Guckian,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/39331

to look at the new patch set (#12).

Change subject: src: Make PCI ID define names shorter
......................................................................

src: Make PCI ID define names shorter

This patch shortens define names containing PCI_{DEVICE,VENDOR}_ID_
with PCI_{DID,VID}_.

Used commands:
find -type f -exec sed -i 's/PCI_DEVICE_ID_/PCI_DID_/g' {} +
find -type f -exec sed -i 's/PCI_VENDOR_ID_/PCI_VID_/g' {} +

Change-Id: If9027700f53b6d0d3964c26a41a1f9b8f62be178
Signed-off-by: Felix Singer 
---
M src/device/pci_rom.c
M src/drivers/aspeed/ast2050/ast2050.c
M src/drivers/broadcom/bcm57xx_aspm_disable.c
M src/drivers/generic/bayhub/bh720.c
M src/drivers/generic/bayhub_lv2/lv2.c
M src/drivers/genesyslogic/gl9750/gl9750.c
M src/drivers/genesyslogic/gl9755/gl9755.c
M src/drivers/genesyslogic/gl9763e/gl9763e.c
M src/drivers/intel/gma/opregion.c
M src/drivers/intel/i210/i210.c
M src/drivers/intel/ish/ish.c
M src/drivers/net/r8168.c
M src/drivers/ricoh/rce822/rce822.c
M src/drivers/siemens/nc_fpga/nc_fpga.c
M src/drivers/siemens/nc_fpga/nc_fpga_early.c
M src/drivers/usb/pci_xhci/pci_xhci.c
M src/drivers/wifi/generic/acpi.c
M src/drivers/wifi/generic/generic.c
M src/drivers/wifi/generic/smbios.c
M src/include/device/pci_ids.h
M src/mainboard/google/brya/variants/brask/ramstage.c
M src/mainboard/google/brya/variants/brya0/ramstage.c
M src/mainboard/google/brya/variants/brya4es/ramstage.c
M src/mainboard/google/brya/variants/kano/ramstage.c
M src/mainboard/google/hatch/variants/baseboard/mainboard.c
M src/mainboard/google/poppy/variants/atlas/mainboard.c
M src/mainboard/google/poppy/variants/nocturne/mainboard.c
M src/mainboard/intel/adlrvp/ramstage.c
M src/mainboard/lenovo/x60/mainboard.c
M src/mainboard/prodrive/hermes/devicetree.cb
M src/mainboard/siemens/mc_apl1/mainboard.c
M src/mainboard/siemens/mc_apl1/variants/mc_apl1/mainboard.c
M src/mainboard/siemens/mc_apl1/variants/mc_apl2/mainboard.c
M src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c
M src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c
M src/mainboard/siemens/mc_apl1/variants/mc_apl6/mainboard.c
M src/mainboard/siemens/mc_ehl/mainboard.c
M src/northbridge/amd/agesa/family14/northbridge.c
M src/northbridge/amd/agesa/family15tn/iommu.c
M src/northbridge/amd/agesa/family15tn/northbridge.c
M src/northbridge/amd/agesa/family16kb/northbridge.c
M src/northbridge/amd/pi/00730F01/iommu.c
M src/northbridge/amd/pi/00730F01/northbridge.c
M src/northbridge/intel/gm45/gma.c
M src/northbridge/intel/haswell/gma.c
M src/northbridge/intel/haswell/minihd.c
M src/northbridge/intel/haswell/northbridge.c
M src/northbridge/intel/haswell/pcie.c
M src/northbridge/intel/i440bx/northbridge.c
M src/northbridge/intel/i945/gma.c
M src/northbridge/intel/i945/northbridge.c
M src/northbridge/intel/ironlake/gma.c
M src/northbridge/intel/ironlake/northbridge.c
M src/northbridge/intel/pineview/gma.c
M src/northbridge/intel/sandybridge/gma.c
M src/northbridge/intel/sandybridge/northbridge.c
M src/northbridge/intel/sandybridge/pcie.c
M src/northbridge/intel/x4x/gma.c
M src/soc/amd/cezanne/data_fabric.c
M src/soc/amd/cezanne/root_complex.c
M src/soc/amd/common/block/acp/acp.c
M src/soc/amd/common/block/graphics/graphics.c
M src/soc/amd/common/block/hda/hda.c
M src/soc/amd/common/block/iommu/iommu.c
M src/soc/amd/common/block/lpc/lpc.c
M src/soc/amd/common/block/pci/pcie_gpp.c
M src/soc/amd/common/block/sata/sata.c
M src/soc/amd/common/block/smbus/sm.c
M src/soc/amd/picasso/data_fabric.c
M src/soc/amd/picasso/root_complex.c
M src/soc/amd/sabrina/data_fabric.c
M src/soc/amd/sabrina/root_complex.c
M src/soc/amd/stoneyridge/include/soc/pci_devs.h
M src/soc/amd/stoneyridge/northbridge.c
M src/soc/amd/stoneyridge/usb.c
M src/soc/cavium/common/pci/uart.c
M src/soc/intel/alderlake/bootblock/report_platform.c
M src/soc/intel/alderlake/chip.h
M src/soc/intel/alderlake/cpu.c
M src/soc/intel/alderlake/fsp_params.c
M src/soc/intel/alderlake/vr_config.c
M src/soc/intel/apollolake/report_platform.c
M src/soc/intel/baytrail/ehci.c
M src/soc/intel/baytrail/emmc.c
M src/soc/intel/baytrail/gfx.c
M src/soc/intel/baytrail/hda.c
M src/soc/intel/baytrail/lpe.c
M src/soc/intel/baytrail/lpss.c
M src/soc/intel/baytrail/northcluster.c
M src/soc/intel/baytrail/pcie.c
M src/soc/intel/baytrail/sata.c
M src/soc/intel/baytrail/sd.c
M src/soc/intel/baytrail/southcluster.c
M src/soc/intel/baytrail/xhci.c
M src/soc/intel/braswell/emmc.c
M src/soc/intel/braswell/gfx.c
M src/soc/intel/braswell/lpe.c
M src/soc/intel/braswell/lpss.c
M src/soc/intel/braswell/northcluster.c
M src/soc/intel/braswell/pcie.c
M src/soc/intel/braswell/sata.c
M src/soc/intel/braswell/sd.c
M src/soc/intel/braswell/southcluster.c
M src/soc/intel/braswell/xhci.c
M src/soc/intel/broadwell/gma.c
M src/soc/intel/broadwell/minihd.c
M src/soc/intel/broadwell/northbridge.c
M src/soc/intel/broadwell/pch/adsp.c
M src/soc/intel/broadwell/pch/hda.c
M src/soc/intel/broadwell/pch/lpc.c
M src/soc/intel/broadwell/pch/me.c
M src/soc/intel/broadwell/pch/pcie.c
M src/soc/intel/broadwell/pch/sata.c
M src/soc/intel/broadwell/pch/serialio.c
M src/soc/intel/broadwell/pch/usb_ehci.c
M src/soc/intel/broadwell/pch/usb_xhci.c
M src/soc/intel/cannonlake/bootblock/report_platform.c
M src/soc/intel/cannonlake/vr_config.c
M src/soc/intel/common/block/cnvi/cnvi.c
M src/soc/intel/common/block/cse/cse.c
M src/soc/intel/common/block/dsp/dsp.c
M src/soc/intel/common/block/dtt/dtt.c
M src/soc/intel/common/block/graphics/graphics.c
M src/soc/intel/common/block/hda/hda.c
M src/soc/intel/common/block/i2c/i2c.c
M src/soc/intel/common/block/ipu/ipu.c
M src/soc/intel/common/block/lpc/lpc.c
M src/soc/intel/common/block/p2sb/p2sb.c
M src/soc/intel/common/block/pcie/pcie.c
M src/soc/intel/common/block/pmc/pmc.c
M src/soc/intel/common/block/sata/sata.c
M src/soc/intel/common/block/scs/mmc.c
M src/soc/intel/common/block/scs/sd.c
M src/soc/intel/common/block/smbus/smbus.c
M src/soc/intel/common/block/spi/spi.c
M src/soc/intel/common/block/sram/sram.c
M src/soc/intel/common/block/systemagent/systemagent.c
M src/soc/intel/common/block/uart/uart.c
M src/soc/intel/common/block/usb4/usb4.c
M src/soc/intel/common/block/usb4/xhci.c
M src/soc/intel/common/block/xdci/xdci.c
M src/soc/intel/common/block/xhci/xhci.c
M src/soc/intel/denverton_ns/csme_ie_kt.c
M src/soc/intel/denverton_ns/lpc.c
M src/soc/intel/denverton_ns/npk.c
M src/soc/intel/denverton_ns/pmc.c
M src/soc/intel/denverton_ns/sata.c
M src/soc/intel/denverton_ns/systemagent.c
M src/soc/intel/denverton_ns/uart.c
M src/soc/intel/denverton_ns/xhci.c
M src/soc/intel/elkhartlake/bootblock/report_platform.c
M src/soc/intel/icelake/bootblock/report_platform.c
M src/soc/intel/jasperlake/bootblock/report_platform.c
M src/soc/intel/quark/ehci.c
M src/soc/intel/quark/gpio_i2c.c
M src/soc/intel/quark/lpc.c
M src/soc/intel/quark/northcluster.c
M src/soc/intel/quark/sd.c
M src/soc/intel/quark/spi.c
M src/soc/intel/quark/uart.c
M src/soc/intel/skylake/bootblock/report_platform.c
M src/soc/intel/skylake/graphics.c
M src/soc/intel/skylake/vr_config.c
M src/soc/intel/tigerlake/bootblock/report_platform.c
M src/soc/intel/tigerlake/lpm.c
M src/soc/intel/tigerlake/systemagent.c
M src/soc/intel/xeon_sp/cpx/chip.c
M src/soc/intel/xeon_sp/uncore.c
M src/southbridge/amd/agesa/hudson/hda.c
M src/southbridge/amd/agesa/hudson/hudson.c
M src/southbridge/amd/agesa/hudson/ide.c
M src/southbridge/amd/agesa/hudson/lpc.c
M src/southbridge/amd/agesa/hudson/pci.c
M src/southbridge/amd/agesa/hudson/pcie.c
M src/southbridge/amd/agesa/hudson/sata.c
M src/southbridge/amd/agesa/hudson/sd.c
M src/southbridge/amd/agesa/hudson/sm.c
M src/southbridge/amd/agesa/hudson/usb.c
M src/southbridge/amd/cimx/sb800/late.c
M src/southbridge/amd/pi/hudson/hda.c
M src/southbridge/amd/pi/hudson/hudson.c
M src/southbridge/amd/pi/hudson/ide.c
M src/southbridge/amd/pi/hudson/lpc.c
M src/southbridge/amd/pi/hudson/pci.c
M src/southbridge/amd/pi/hudson/pcie.c
M src/southbridge/amd/pi/hudson/sata.c
M src/southbridge/amd/pi/hudson/sd.c
M src/southbridge/amd/pi/hudson/sm.c
M src/southbridge/amd/pi/hudson/usb.c
M src/southbridge/intel/bd82x6x/azalia.c
M src/southbridge/intel/bd82x6x/lpc.c
M src/southbridge/intel/bd82x6x/me.c
M src/southbridge/intel/bd82x6x/me_8.x.c
M src/southbridge/intel/bd82x6x/pci.c
M src/southbridge/intel/bd82x6x/pcie.c
M src/southbridge/intel/bd82x6x/sata.c
M src/southbridge/intel/bd82x6x/smbus.c
M src/southbridge/intel/bd82x6x/usb_ehci.c
M src/southbridge/intel/bd82x6x/usb_xhci.c
M src/southbridge/intel/common/early_smbus.c
M src/southbridge/intel/i82371eb/bootblock.c
M src/southbridge/intel/i82371eb/early_pm.c
M src/southbridge/intel/i82371eb/early_smbus.c
M src/southbridge/intel/i82371eb/ide.c
M src/southbridge/intel/i82371eb/isa.c
M src/southbridge/intel/i82371eb/smbus.c
M src/southbridge/intel/i82371eb/usb.c
M src/southbridge/intel/i82801dx/ac97.c
M src/southbridge/intel/i82801dx/ide.c
M src/southbridge/intel/i82801dx/lpc.c
M src/southbridge/intel/i82801dx/pci.c
M src/southbridge/intel/i82801dx/usb.c
M src/southbridge/intel/i82801dx/usb2.c
M src/southbridge/intel/i82801gx/ac97.c
M src/southbridge/intel/i82801gx/azalia.c
M src/southbridge/intel/i82801gx/ide.c
M src/southbridge/intel/i82801gx/lpc.c
M src/southbridge/intel/i82801gx/pci.c
M src/southbridge/intel/i82801gx/pcie.c
M src/southbridge/intel/i82801gx/sata.c
M src/southbridge/intel/i82801gx/smbus.c
M src/southbridge/intel/i82801gx/usb.c
M src/southbridge/intel/i82801gx/usb_ehci.c
M src/southbridge/intel/i82801ix/azalia.c
M src/southbridge/intel/i82801ix/lpc.c
M src/southbridge/intel/i82801ix/pci.c
M src/southbridge/intel/i82801ix/pcie.c
M src/southbridge/intel/i82801ix/sata.c
M src/southbridge/intel/i82801ix/smbus.c
M src/southbridge/intel/i82801ix/thermal.c
M src/southbridge/intel/i82801ix/usb_ehci.c
M src/southbridge/intel/i82801jx/azalia.c
M src/southbridge/intel/i82801jx/lpc.c
M src/southbridge/intel/i82801jx/pci.c
M src/southbridge/intel/i82801jx/pcie.c
M src/southbridge/intel/i82801jx/sata.c
M src/southbridge/intel/i82801jx/smbus.c
M src/southbridge/intel/i82801jx/thermal.c
M src/southbridge/intel/i82801jx/usb_ehci.c
M src/southbridge/intel/i82870/ioapic.c
M src/southbridge/intel/i82870/pcibridge.c
M src/southbridge/intel/ibexpeak/azalia.c
M src/southbridge/intel/ibexpeak/lpc.c
M src/southbridge/intel/ibexpeak/me.c
M src/southbridge/intel/ibexpeak/sata.c
M src/southbridge/intel/ibexpeak/smbus.c
M src/southbridge/intel/ibexpeak/thermal.c
M src/southbridge/intel/ibexpeak/usb_ehci.c
M src/southbridge/intel/lynxpoint/azalia.c
M src/southbridge/intel/lynxpoint/lpc.c
M src/southbridge/intel/lynxpoint/me.c
M src/southbridge/intel/lynxpoint/pcie.c
M src/southbridge/intel/lynxpoint/sata.c
M src/southbridge/intel/lynxpoint/serialio.c
M src/southbridge/intel/lynxpoint/smbus.c
M src/southbridge/intel/lynxpoint/usb_ehci.c
M src/southbridge/intel/lynxpoint/usb_xhci.c
M src/southbridge/ricoh/rl5c476/rl5c476.c
M src/southbridge/ti/pci1x2x/pci1x2x.c
M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Pci22.h
M src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/IndustryStandard/Pci22.h
M src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/Pci22.h
262 files changed, 6,614 insertions(+), 6,614 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/39331/12

Change in coreboot[master]: src: Make PCI ID define names shorter

[HAOUAS Elyes (Code Review)]

Attention is currently required from: Felix Singer, Raul Rangel, Patrick Rudolph, Mariusz Szafrański, Jonathan Zhang, Paul Menzel, Angel Pons, Jason Glenesk, Anjaneya "Reddy" Chagam, Martin Roth, Marshall Dawson, Johnny Lin, Tim Wawrzynczak, Christian Walter, Suresh Bellampalli, Michal Motyl, Felix Held, Tim Chu.
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39331 )

Change subject: src: Make PCI ID define names shorter
......................................................................

Patch Set 12: Code-Review+2

Change in coreboot[master]: src: Make PCI ID define names shorter

[Nico Huber (Code Review)]

Attention is currently required from: Felix Singer, Raul Rangel, Patrick Rudolph, Mariusz Szafrański, Jonathan Zhang, Paul Menzel, Angel Pons, Jason Glenesk, Anjaneya "Reddy" Chagam, Martin Roth, Marshall Dawson, Johnny Lin, Tim Wawrzynczak, Christian Walter, Suresh Bellampalli, Michal Motyl, Felix Held, Tim Chu.
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39331 )

Change subject: src: Make PCI ID define names shorter
......................................................................

Patch Set 12:

(1 comment)

Commit Message:

https://review.coreboot.org/c/coreboot/+/39331/comment/687fcef3_95718134 
PS12, Line 14: find -type f -exec sed -i 's/PCI_VENDOR_ID_/PCI_VID_/g' {} +
I would prefer to keep things aligned automatically. The easiest way is
to add a tab where things would get misaligned (i.e. when the identifier
length modulo 8 is smaller than 6):

git grep -l 'PCI_(DEVICE|VENDOR)_ID' src/ | xargs \
    sed -i 's/PCI_([DV])(EVICE|ENDOR)_ID_([_0-9A-Za-z]{2}([_0-9A-Za-z]{8})*[_0-9A-Za-z]{0,5})\t/PCI_\1ID_\3\t\t/g'

then replace the rest

git grep -l 'PCI_(DEVICE|VENDOR)_ID' src/ | xargs \
    sed -i 's/PCI_([DV])(EVICE|ENDOR)_ID_([_0-9A-Za-z]*)/PCI_\1ID_\3/g'

Removing excessive margin (i.e. when a whole block uses more tabs than
necessary) could still be done later.

Change in coreboot[master]: src: Make PCI ID define names shorter

[Elyes Haouas (Code Review)]

Attention is currently required from: Felix Singer, Raul Rangel, Patrick Rudolph, Mariusz Szafrański, Jonathan Zhang, Paul Menzel, Angel Pons, Jason Glenesk, Nico Huber, Anjaneya "Reddy" Chagam, Martin Roth, Marshall Dawson, Johnny Lin, Tim Wawrzynczak, Christian Walter, Suresh Bellampalli, Michal Motyl, Felix Held, Tim Chu.
Elyes Haouas has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39331 )

Change subject: src: Make PCI ID define names shorter
......................................................................

Patch Set 12:

(1 comment)

Commit Message:

https://review.coreboot.org/c/coreboot/+/39331/comment/92ab0aca_786d14c9 
PS12, Line 14: find -type f -exec sed -i 's/PCI_VENDOR_ID_/PCI_VID_/g' {} +
> I would prefer to keep things aligned automatically. The easiest way is […]

Done

Change in coreboot[master]: src: Make PCI ID define names shorter

[Elyes Haouas (Code Review)]

Attention is currently required from: Felix Singer, Raul Rangel, Patrick Rudolph, Mariusz Szafrański, Jonathan Zhang, Paul Menzel, Angel Pons, Jason Glenesk, Nico Huber, Anjaneya "Reddy" Chagam, Martin Roth, Marshall Dawson, Johnny Lin, Tim Wawrzynczak, Christian Walter, Suresh Bellampalli, Michal Motyl, Felix Held, Tim Chu.
Elyes Haouas has uploaded a new patch set (#13) to the change originally created by Felix Singer. ( https://review.coreboot.org/c/coreboot/+/39331 )

Change subject: src: Make PCI ID define names shorter
......................................................................

src: Make PCI ID define names shorter

This patch shortens define names containing PCI_{DEVICE,VENDOR}_ID_
with PCI_{DID,VID}_.

Used commands:
find -type f -exec sed -i 's/PCI_([DV])(EVICE|ENDOR)_ID_([_0-9A-Za-z]{2}([_0-9A-Za-z]{8})*[_0-9A-Za-z]{0,5})\t/PCI_\1ID_\3\t\t/g'
find -type f -exec sed -i 's/PCI_([DV])(EVICE|ENDOR)_ID_([_0-9A-Za-z]*)/PCI_\1ID_\3/g'

Change-Id: If9027700f53b6d0d3964c26a41a1f9b8f62be178
Signed-off-by: Felix Singer 
Signed-off-by: Elyes Haouas 
---
M src/soc/intel/skylake/vr_config.c
M src/southbridge/amd/agesa/hudson/hudson.c
M src/southbridge/amd/pi/hudson/hudson.c
3 files changed, 3 insertions(+), 5 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/39331/13

Change in coreboot[master]: src: Make PCI ID define names shorter

[Elyes Haouas (Code Review)]

Attention is currently required from: Raul Rangel, Patrick Rudolph, Mariusz Szafrański, Jonathan Zhang, Paul Menzel, Angel Pons, Jason Glenesk, Nico Huber, Anjaneya "Reddy" Chagam, Martin Roth, Marshall Dawson, Johnny Lin, Tim Wawrzynczak, Christian Walter, Suresh Bellampalli, Michal Motyl, Elyes Haouas, Felix Held, Tim Chu.
Elyes Haouas has uploaded a new patch set (#14) to the change originally created by Felix Singer. ( https://review.coreboot.org/c/coreboot/+/39331 )

Change subject: src: Make PCI ID define names shorter
......................................................................

src: Make PCI ID define names shorter

This patch shortens define names containing PCI_{DEVICE,VENDOR}_ID_
with PCI_{DID,VID}_.

Used commands:
find -type f -exec sed -i 's/PCI_([DV])(EVICE|ENDOR)_ID_([_0-9A-Za-z]{2}([_0-9A-Za-z]{8})*[_0-9A-Za-z]{0,5})\t/PCI_\1ID_\3\t\t/g'
find -type f -exec sed -i 's/PCI_([DV])(EVICE|ENDOR)_ID_([_0-9A-Za-z]*)/PCI_\1ID_\3/g'

Change-Id: If9027700f53b6d0d3964c26a41a1f9b8f62be178
Signed-off-by: Felix Singer 
Signed-off-by: Elyes Haouas 
---
M src/device/pci_rom.c
M src/drivers/aspeed/ast2050/ast2050.c
M src/drivers/broadcom/bcm57xx_aspm_disable.c
M src/drivers/generic/bayhub/bh720.c
M src/drivers/generic/bayhub_lv2/lv2.c
M src/drivers/genesyslogic/gl9750/gl9750.c
M src/drivers/genesyslogic/gl9755/gl9755.c
M src/drivers/genesyslogic/gl9763e/gl9763e.c
M src/drivers/intel/gma/opregion.c
M src/drivers/intel/i210/i210.c
M src/drivers/intel/ish/ish.c
M src/drivers/net/r8168.c
M src/drivers/ricoh/rce822/rce822.c
M src/drivers/siemens/nc_fpga/nc_fpga.c
M src/drivers/siemens/nc_fpga/nc_fpga_early.c
M src/drivers/usb/pci_xhci/pci_xhci.c
M src/drivers/wifi/generic/acpi.c
M src/drivers/wifi/generic/generic.c
M src/drivers/wifi/generic/smbios.c
M src/include/device/pci_ids.h
M src/mainboard/google/brya/variants/brask/ramstage.c
M src/mainboard/google/brya/variants/brya0/ramstage.c
M src/mainboard/google/brya/variants/brya4es/ramstage.c
M src/mainboard/google/brya/variants/kano/ramstage.c
M src/mainboard/google/hatch/variants/baseboard/mainboard.c
M src/mainboard/google/poppy/variants/atlas/mainboard.c
M src/mainboard/google/poppy/variants/nocturne/mainboard.c
M src/mainboard/intel/adlrvp/ramstage.c
M src/mainboard/lenovo/x60/mainboard.c
M src/mainboard/prodrive/hermes/devicetree.cb
M src/mainboard/siemens/mc_apl1/mainboard.c
M src/mainboard/siemens/mc_apl1/variants/mc_apl1/mainboard.c
M src/mainboard/siemens/mc_apl1/variants/mc_apl2/mainboard.c
M src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c
M src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c
M src/mainboard/siemens/mc_apl1/variants/mc_apl6/mainboard.c
M src/mainboard/siemens/mc_ehl/mainboard.c
M src/northbridge/amd/agesa/family14/northbridge.c
M src/northbridge/amd/agesa/family15tn/iommu.c
M src/northbridge/amd/agesa/family15tn/northbridge.c
M src/northbridge/amd/agesa/family16kb/northbridge.c
M src/northbridge/amd/pi/00730F01/iommu.c
M src/northbridge/amd/pi/00730F01/northbridge.c
M src/northbridge/intel/gm45/gma.c
M src/northbridge/intel/haswell/gma.c
M src/northbridge/intel/haswell/minihd.c
M src/northbridge/intel/haswell/northbridge.c
M src/northbridge/intel/haswell/pcie.c
M src/northbridge/intel/i440bx/northbridge.c
M src/northbridge/intel/i945/gma.c
M src/northbridge/intel/i945/northbridge.c
M src/northbridge/intel/ironlake/gma.c
M src/northbridge/intel/ironlake/northbridge.c
M src/northbridge/intel/pineview/gma.c
M src/northbridge/intel/sandybridge/gma.c
M src/northbridge/intel/sandybridge/northbridge.c
M src/northbridge/intel/sandybridge/pcie.c
M src/northbridge/intel/x4x/gma.c
M src/soc/amd/cezanne/data_fabric.c
M src/soc/amd/cezanne/root_complex.c
M src/soc/amd/common/block/acp/acp.c
M src/soc/amd/common/block/graphics/graphics.c
M src/soc/amd/common/block/hda/hda.c
M src/soc/amd/common/block/iommu/iommu.c
M src/soc/amd/common/block/lpc/lpc.c
M src/soc/amd/common/block/pci/pcie_gpp.c
M src/soc/amd/common/block/sata/sata.c
M src/soc/amd/common/block/smbus/sm.c
M src/soc/amd/picasso/data_fabric.c
M src/soc/amd/picasso/root_complex.c
M src/soc/amd/sabrina/data_fabric.c
M src/soc/amd/sabrina/root_complex.c
M src/soc/amd/sabrina/xhci.c
M src/soc/amd/stoneyridge/include/soc/pci_devs.h
M src/soc/amd/stoneyridge/northbridge.c
M src/soc/amd/stoneyridge/usb.c
M src/soc/cavium/common/pci/uart.c
M src/soc/intel/alderlake/bootblock/report_platform.c
M src/soc/intel/alderlake/chip.h
M src/soc/intel/alderlake/cpu.c
M src/soc/intel/alderlake/fsp_params.c
M src/soc/intel/alderlake/vr_config.c
M src/soc/intel/apollolake/report_platform.c
M src/soc/intel/baytrail/ehci.c
M src/soc/intel/baytrail/emmc.c
M src/soc/intel/baytrail/gfx.c
M src/soc/intel/baytrail/hda.c
M src/soc/intel/baytrail/lpe.c
M src/soc/intel/baytrail/lpss.c
M src/soc/intel/baytrail/northcluster.c
M src/soc/intel/baytrail/pcie.c
M src/soc/intel/baytrail/sata.c
M src/soc/intel/baytrail/sd.c
M src/soc/intel/baytrail/southcluster.c
M src/soc/intel/baytrail/xhci.c
M src/soc/intel/braswell/emmc.c
M src/soc/intel/braswell/gfx.c
M src/soc/intel/braswell/lpe.c
M src/soc/intel/braswell/lpss.c
M src/soc/intel/braswell/northcluster.c
M src/soc/intel/braswell/pcie.c
M src/soc/intel/braswell/sata.c
M src/soc/intel/braswell/sd.c
M src/soc/intel/braswell/southcluster.c
M src/soc/intel/braswell/xhci.c
M src/soc/intel/broadwell/gma.c
M src/soc/intel/broadwell/minihd.c
M src/soc/intel/broadwell/northbridge.c
M src/soc/intel/broadwell/pch/adsp.c
M src/soc/intel/broadwell/pch/hda.c
M src/soc/intel/broadwell/pch/lpc.c
M src/soc/intel/broadwell/pch/me.c
M src/soc/intel/broadwell/pch/pcie.c
M src/soc/intel/broadwell/pch/sata.c
M src/soc/intel/broadwell/pch/serialio.c
M src/soc/intel/broadwell/pch/usb_ehci.c
M src/soc/intel/broadwell/pch/usb_xhci.c
M src/soc/intel/cannonlake/bootblock/report_platform.c
M src/soc/intel/cannonlake/vr_config.c
M src/soc/intel/common/block/cnvi/cnvi.c
M src/soc/intel/common/block/cse/cse.c
M src/soc/intel/common/block/dsp/dsp.c
M src/soc/intel/common/block/dtt/dtt.c
M src/soc/intel/common/block/graphics/graphics.c
M src/soc/intel/common/block/hda/hda.c
M src/soc/intel/common/block/i2c/i2c.c
M src/soc/intel/common/block/ipu/ipu.c
M src/soc/intel/common/block/lpc/lpc.c
M src/soc/intel/common/block/p2sb/p2sb.c
M src/soc/intel/common/block/p2sb/p2sblib.c
M src/soc/intel/common/block/pcie/pcie.c
M src/soc/intel/common/block/pmc/pmc.c
M src/soc/intel/common/block/sata/sata.c
M src/soc/intel/common/block/scs/mmc.c
M src/soc/intel/common/block/scs/sd.c
M src/soc/intel/common/block/smbus/smbus.c
M src/soc/intel/common/block/spi/spi.c
M src/soc/intel/common/block/sram/sram.c
M src/soc/intel/common/block/systemagent/systemagent.c
M src/soc/intel/common/block/uart/uart.c
M src/soc/intel/common/block/usb4/usb4.c
M src/soc/intel/common/block/usb4/xhci.c
M src/soc/intel/common/block/xdci/xdci.c
M src/soc/intel/common/block/xhci/xhci.c
M src/soc/intel/denverton_ns/csme_ie_kt.c
M src/soc/intel/denverton_ns/lpc.c
M src/soc/intel/denverton_ns/npk.c
M src/soc/intel/denverton_ns/sata.c
M src/soc/intel/denverton_ns/systemagent.c
M src/soc/intel/denverton_ns/uart.c
M src/soc/intel/denverton_ns/xhci.c
M src/soc/intel/elkhartlake/bootblock/report_platform.c
M src/soc/intel/icelake/bootblock/report_platform.c
M src/soc/intel/jasperlake/bootblock/report_platform.c
M src/soc/intel/quark/ehci.c
M src/soc/intel/quark/gpio_i2c.c
M src/soc/intel/quark/lpc.c
M src/soc/intel/quark/northcluster.c
M src/soc/intel/quark/sd.c
M src/soc/intel/quark/spi.c
M src/soc/intel/quark/uart.c
M src/soc/intel/skylake/bootblock/report_platform.c
M src/soc/intel/skylake/graphics.c
M src/soc/intel/skylake/vr_config.c
M src/soc/intel/tigerlake/bootblock/report_platform.c
M src/soc/intel/tigerlake/lpm.c
M src/soc/intel/tigerlake/systemagent.c
M src/soc/intel/xeon_sp/cpx/chip.c
M src/soc/intel/xeon_sp/uncore.c
M src/southbridge/amd/agesa/hudson/hda.c
M src/southbridge/amd/agesa/hudson/hudson.c
M src/southbridge/amd/agesa/hudson/ide.c
M src/southbridge/amd/agesa/hudson/lpc.c
M src/southbridge/amd/agesa/hudson/pci.c
M src/southbridge/amd/agesa/hudson/pcie.c
M src/southbridge/amd/agesa/hudson/sata.c
M src/southbridge/amd/agesa/hudson/sd.c
M src/southbridge/amd/agesa/hudson/sm.c
M src/southbridge/amd/agesa/hudson/usb.c
M src/southbridge/amd/cimx/sb800/late.c
M src/southbridge/amd/pi/hudson/hda.c
M src/southbridge/amd/pi/hudson/hudson.c
M src/southbridge/amd/pi/hudson/ide.c
M src/southbridge/amd/pi/hudson/lpc.c
M src/southbridge/amd/pi/hudson/pci.c
M src/southbridge/amd/pi/hudson/pcie.c
M src/southbridge/amd/pi/hudson/sata.c
M src/southbridge/amd/pi/hudson/sd.c
M src/southbridge/amd/pi/hudson/sm.c
M src/southbridge/amd/pi/hudson/usb.c
M src/southbridge/intel/bd82x6x/azalia.c
M src/southbridge/intel/bd82x6x/lpc.c
M src/southbridge/intel/bd82x6x/me.c
M src/southbridge/intel/bd82x6x/me_8.x.c
M src/southbridge/intel/bd82x6x/pci.c
M src/southbridge/intel/bd82x6x/pcie.c
M src/southbridge/intel/bd82x6x/sata.c
M src/southbridge/intel/bd82x6x/smbus.c
M src/southbridge/intel/bd82x6x/usb_ehci.c
M src/southbridge/intel/bd82x6x/usb_xhci.c
M src/southbridge/intel/common/early_smbus.c
M src/southbridge/intel/i82371eb/bootblock.c
M src/southbridge/intel/i82371eb/early_pm.c
M src/southbridge/intel/i82371eb/early_smbus.c
M src/southbridge/intel/i82371eb/ide.c
M src/southbridge/intel/i82371eb/isa.c
M src/southbridge/intel/i82371eb/smbus.c
M src/southbridge/intel/i82371eb/usb.c
M src/southbridge/intel/i82801dx/ac97.c
M src/southbridge/intel/i82801dx/ide.c
M src/southbridge/intel/i82801dx/lpc.c
M src/southbridge/intel/i82801dx/pci.c
M src/southbridge/intel/i82801dx/usb.c
M src/southbridge/intel/i82801dx/usb2.c
M src/southbridge/intel/i82801gx/ac97.c
M src/southbridge/intel/i82801gx/azalia.c
M src/southbridge/intel/i82801gx/ide.c
M src/southbridge/intel/i82801gx/lpc.c
M src/southbridge/intel/i82801gx/pci.c
M src/southbridge/intel/i82801gx/pcie.c
M src/southbridge/intel/i82801gx/sata.c
M src/southbridge/intel/i82801gx/smbus.c
M src/southbridge/intel/i82801gx/usb.c
M src/southbridge/intel/i82801gx/usb_ehci.c
M src/southbridge/intel/i82801ix/azalia.c
M src/southbridge/intel/i82801ix/lpc.c
M src/southbridge/intel/i82801ix/pci.c
M src/southbridge/intel/i82801ix/pcie.c
M src/southbridge/intel/i82801ix/sata.c
M src/southbridge/intel/i82801ix/smbus.c
M src/southbridge/intel/i82801ix/thermal.c
M src/southbridge/intel/i82801ix/usb_ehci.c
M src/southbridge/intel/i82801jx/azalia.c
M src/southbridge/intel/i82801jx/lpc.c
M src/southbridge/intel/i82801jx/pci.c
M src/southbridge/intel/i82801jx/pcie.c
M src/southbridge/intel/i82801jx/sata.c
M src/southbridge/intel/i82801jx/smbus.c
M src/southbridge/intel/i82801jx/thermal.c
M src/southbridge/intel/i82801jx/usb_ehci.c
M src/southbridge/intel/i82870/ioapic.c
M src/southbridge/intel/i82870/pcibridge.c
M src/southbridge/intel/ibexpeak/azalia.c
M src/southbridge/intel/ibexpeak/lpc.c
M src/southbridge/intel/ibexpeak/me.c
M src/southbridge/intel/ibexpeak/sata.c
M src/southbridge/intel/ibexpeak/smbus.c
M src/southbridge/intel/ibexpeak/thermal.c
M src/southbridge/intel/ibexpeak/usb_ehci.c
M src/southbridge/intel/lynxpoint/azalia.c
M src/southbridge/intel/lynxpoint/lpc.c
M src/southbridge/intel/lynxpoint/me.c
M src/southbridge/intel/lynxpoint/pcie.c
M src/southbridge/intel/lynxpoint/sata.c
M src/southbridge/intel/lynxpoint/serialio.c
M src/southbridge/intel/lynxpoint/smbus.c
M src/southbridge/intel/lynxpoint/usb_ehci.c
M src/southbridge/intel/lynxpoint/usb_xhci.c
M src/southbridge/ricoh/rl5c476/rl5c476.c
M src/southbridge/ti/pci1x2x/pci1x2x.c
M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Pci22.h
M src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/IndustryStandard/Pci22.h
M src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/Pci22.h
263 files changed, 6,620 insertions(+), 6,622 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/39331/14

Change in coreboot[master]: src: Make PCI ID define names shorter

[build bot (Jenkins) (Code Review)]

Attention is currently required from: Raul Rangel, Patrick Rudolph, Mariusz Szafrański, Jonathan Zhang, Paul Menzel, Angel Pons, Jason Glenesk, Nico Huber, Anjaneya "Reddy" Chagam, Martin Roth, Marshall Dawson, Johnny Lin, Tim Wawrzynczak, Christian Walter, Suresh Bellampalli, Michal Motyl, Fred Reitberger, Elyes Haouas, Felix Held, Tim Chu.
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39331 )

Change subject: src: Make PCI ID define names shorter
......................................................................

Patch Set 14:

(3 comments)

File src/include/device/pci_ids.h:

Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-143237):
https://review.coreboot.org/c/coreboot/+/39331/comment/5eaff477_82e25f47 
PS14, Line 2117: #define PCI_VID_AKS			0x416c
'AKS' may be misspelled - perhaps 'ASK'?

Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-143237):
https://review.coreboot.org/c/coreboot/+/39331/comment/3d4c7bfc_34ca832f 
PS14, Line 2118: #define PCI_DID_AKS_ALADDINCARD		0x0100
'AKS' may be misspelled - perhaps 'ASK'?

Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-143237):
https://review.coreboot.org/c/coreboot/+/39331/comment/aac9afa6_d3580547 
PS14, Line 2119: #define PCI_DID_AKS_CPC			0x0200
'AKS' may be misspelled - perhaps 'ASK'?

Change in coreboot[master]: src: Make PCI ID define names shorter

[Felix Singer (Code Review)]

Attention is currently required from: Raul Rangel, Patrick Rudolph, Mariusz Szafrański, Jonathan Zhang, Paul Menzel, Angel Pons, Jason Glenesk, Nico Huber, Anjaneya "Reddy" Chagam, Martin Roth, Marshall Dawson, Johnny Lin, Tim Wawrzynczak, Christian Walter, Suresh Bellampalli, Michal Motyl, Fred Reitberger, Felix Held, Tim Chu.
Hello build bot (Jenkins), Raul Rangel, Patrick Rudolph, Mariusz Szafrański, Jonathan Zhang, Arthur Heymans, Andrey Petrov, Patrick Rudolph, Anjaneya "Reddy" Chagam, Nico Huber, David Guckian, Johnny Lin, Christian Walter, Suresh Bellampalli, Michal Motyl, Fred Reitberger, Alexander Couzens, Werner Zeh, Tim Chu, Felix Held, Angel Pons, Michael Niewöhner, Jason Glenesk, Damien Zammit, Marshall Dawson, Tim Wawrzynczak, Vanessa Eusebio, Elyes Haouas, David Guckian,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/39331

to look at the new patch set (#15).

Change subject: src: Make PCI ID define names shorter
......................................................................

src: Make PCI ID define names shorter

Shorten define names containing PCI_{DEVICE,VENDOR}_ID_ with
PCI_{DID,VID}_. Also, try to fix some spacing issues using the commands
below. An additional clean up of pci_ids.h is done in CB:61531.

* find -type f -exec sed -i 's/PCI_([DV])(EVICE|ENDOR)_ID_([_0-9A-Za-z]{2}([_0-9A-Za-z]{8})*[_0-9A-Za-z]{0,5})\t/PCI_\1ID_\3\t\t/g'

* find -type f -exec sed -i 's/PCI_([DV])(EVICE|ENDOR)_ID_([_0-9A-Za-z]*)/PCI_\1ID_\3/g'

Change-Id: If9027700f53b6d0d3964c26a41a1f9b8f62be178
Signed-off-by: Felix Singer 
Signed-off-by: Elyes Haouas 
---
M src/device/pci_rom.c
M src/drivers/aspeed/ast2050/ast2050.c
M src/drivers/broadcom/bcm57xx_aspm_disable.c
M src/drivers/generic/bayhub/bh720.c
M src/drivers/generic/bayhub_lv2/lv2.c
M src/drivers/genesyslogic/gl9750/gl9750.c
M src/drivers/genesyslogic/gl9755/gl9755.c
M src/drivers/genesyslogic/gl9763e/gl9763e.c
M src/drivers/intel/gma/opregion.c
M src/drivers/intel/i210/i210.c
M src/drivers/intel/ish/ish.c
M src/drivers/net/r8168.c
M src/drivers/ricoh/rce822/rce822.c
M src/drivers/siemens/nc_fpga/nc_fpga.c
M src/drivers/siemens/nc_fpga/nc_fpga_early.c
M src/drivers/usb/pci_xhci/pci_xhci.c
M src/drivers/wifi/generic/acpi.c
M src/drivers/wifi/generic/generic.c
M src/drivers/wifi/generic/smbios.c
M src/include/device/pci_ids.h
M src/mainboard/google/brya/variants/brask/ramstage.c
M src/mainboard/google/brya/variants/brya0/ramstage.c
M src/mainboard/google/brya/variants/brya4es/ramstage.c
M src/mainboard/google/brya/variants/kano/ramstage.c
M src/mainboard/google/hatch/variants/baseboard/mainboard.c
M src/mainboard/google/poppy/variants/atlas/mainboard.c
M src/mainboard/google/poppy/variants/nocturne/mainboard.c
M src/mainboard/intel/adlrvp/ramstage.c
M src/mainboard/lenovo/x60/mainboard.c
M src/mainboard/prodrive/hermes/devicetree.cb
M src/mainboard/siemens/mc_apl1/mainboard.c
M src/mainboard/siemens/mc_apl1/variants/mc_apl1/mainboard.c
M src/mainboard/siemens/mc_apl1/variants/mc_apl2/mainboard.c
M src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c
M src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c
M src/mainboard/siemens/mc_apl1/variants/mc_apl6/mainboard.c
M src/mainboard/siemens/mc_ehl/mainboard.c
M src/northbridge/amd/agesa/family14/northbridge.c
M src/northbridge/amd/agesa/family15tn/iommu.c
M src/northbridge/amd/agesa/family15tn/northbridge.c
M src/northbridge/amd/agesa/family16kb/northbridge.c
M src/northbridge/amd/pi/00730F01/iommu.c
M src/northbridge/amd/pi/00730F01/northbridge.c
M src/northbridge/intel/gm45/gma.c
M src/northbridge/intel/haswell/gma.c
M src/northbridge/intel/haswell/minihd.c
M src/northbridge/intel/haswell/northbridge.c
M src/northbridge/intel/haswell/pcie.c
M src/northbridge/intel/i440bx/northbridge.c
M src/northbridge/intel/i945/gma.c
M src/northbridge/intel/i945/northbridge.c
M src/northbridge/intel/ironlake/gma.c
M src/northbridge/intel/ironlake/northbridge.c
M src/northbridge/intel/pineview/gma.c
M src/northbridge/intel/sandybridge/gma.c
M src/northbridge/intel/sandybridge/northbridge.c
M src/northbridge/intel/sandybridge/pcie.c
M src/northbridge/intel/x4x/gma.c
M src/soc/amd/cezanne/data_fabric.c
M src/soc/amd/cezanne/root_complex.c
M src/soc/amd/common/block/acp/acp.c
M src/soc/amd/common/block/graphics/graphics.c
M src/soc/amd/common/block/hda/hda.c
M src/soc/amd/common/block/iommu/iommu.c
M src/soc/amd/common/block/lpc/lpc.c
M src/soc/amd/common/block/pci/pcie_gpp.c
M src/soc/amd/common/block/sata/sata.c
M src/soc/amd/common/block/smbus/sm.c
M src/soc/amd/picasso/data_fabric.c
M src/soc/amd/picasso/root_complex.c
M src/soc/amd/sabrina/data_fabric.c
M src/soc/amd/sabrina/root_complex.c
M src/soc/amd/sabrina/xhci.c
M src/soc/amd/stoneyridge/include/soc/pci_devs.h
M src/soc/amd/stoneyridge/northbridge.c
M src/soc/amd/stoneyridge/usb.c
M src/soc/cavium/common/pci/uart.c
M src/soc/intel/alderlake/bootblock/report_platform.c
M src/soc/intel/alderlake/chip.h
M src/soc/intel/alderlake/cpu.c
M src/soc/intel/alderlake/fsp_params.c
M src/soc/intel/alderlake/vr_config.c
M src/soc/intel/apollolake/report_platform.c
M src/soc/intel/baytrail/ehci.c
M src/soc/intel/baytrail/emmc.c
M src/soc/intel/baytrail/gfx.c
M src/soc/intel/baytrail/hda.c
M src/soc/intel/baytrail/lpe.c
M src/soc/intel/baytrail/lpss.c
M src/soc/intel/baytrail/northcluster.c
M src/soc/intel/baytrail/pcie.c
M src/soc/intel/baytrail/sata.c
M src/soc/intel/baytrail/sd.c
M src/soc/intel/baytrail/southcluster.c
M src/soc/intel/baytrail/xhci.c
M src/soc/intel/braswell/emmc.c
M src/soc/intel/braswell/gfx.c
M src/soc/intel/braswell/lpe.c
M src/soc/intel/braswell/lpss.c
M src/soc/intel/braswell/northcluster.c
M src/soc/intel/braswell/pcie.c
M src/soc/intel/braswell/sata.c
M src/soc/intel/braswell/sd.c
M src/soc/intel/braswell/southcluster.c
M src/soc/intel/braswell/xhci.c
M src/soc/intel/broadwell/gma.c
M src/soc/intel/broadwell/minihd.c
M src/soc/intel/broadwell/northbridge.c
M src/soc/intel/broadwell/pch/adsp.c
M src/soc/intel/broadwell/pch/hda.c
M src/soc/intel/broadwell/pch/lpc.c
M src/soc/intel/broadwell/pch/me.c
M src/soc/intel/broadwell/pch/pcie.c
M src/soc/intel/broadwell/pch/sata.c
M src/soc/intel/broadwell/pch/serialio.c
M src/soc/intel/broadwell/pch/usb_ehci.c
M src/soc/intel/broadwell/pch/usb_xhci.c
M src/soc/intel/cannonlake/bootblock/report_platform.c
M src/soc/intel/cannonlake/vr_config.c
M src/soc/intel/common/block/cnvi/cnvi.c
M src/soc/intel/common/block/cse/cse.c
M src/soc/intel/common/block/dsp/dsp.c
M src/soc/intel/common/block/dtt/dtt.c
M src/soc/intel/common/block/graphics/graphics.c
M src/soc/intel/common/block/hda/hda.c
M src/soc/intel/common/block/i2c/i2c.c
M src/soc/intel/common/block/ipu/ipu.c
M src/soc/intel/common/block/lpc/lpc.c
M src/soc/intel/common/block/p2sb/p2sb.c
M src/soc/intel/common/block/p2sb/p2sblib.c
M src/soc/intel/common/block/pcie/pcie.c
M src/soc/intel/common/block/pmc/pmc.c
M src/soc/intel/common/block/sata/sata.c
M src/soc/intel/common/block/scs/mmc.c
M src/soc/intel/common/block/scs/sd.c
M src/soc/intel/common/block/smbus/smbus.c
M src/soc/intel/common/block/spi/spi.c
M src/soc/intel/common/block/sram/sram.c
M src/soc/intel/common/block/systemagent/systemagent.c
M src/soc/intel/common/block/uart/uart.c
M src/soc/intel/common/block/usb4/usb4.c
M src/soc/intel/common/block/usb4/xhci.c
M src/soc/intel/common/block/xdci/xdci.c
M src/soc/intel/common/block/xhci/xhci.c
M src/soc/intel/denverton_ns/csme_ie_kt.c
M src/soc/intel/denverton_ns/lpc.c
M src/soc/intel/denverton_ns/npk.c
M src/soc/intel/denverton_ns/sata.c
M src/soc/intel/denverton_ns/systemagent.c
M src/soc/intel/denverton_ns/uart.c
M src/soc/intel/denverton_ns/xhci.c
M src/soc/intel/elkhartlake/bootblock/report_platform.c
M src/soc/intel/icelake/bootblock/report_platform.c
M src/soc/intel/jasperlake/bootblock/report_platform.c
M src/soc/intel/quark/ehci.c
M src/soc/intel/quark/gpio_i2c.c
M src/soc/intel/quark/lpc.c
M src/soc/intel/quark/northcluster.c
M src/soc/intel/quark/sd.c
M src/soc/intel/quark/spi.c
M src/soc/intel/quark/uart.c
M src/soc/intel/skylake/bootblock/report_platform.c
M src/soc/intel/skylake/graphics.c
M src/soc/intel/skylake/vr_config.c
M src/soc/intel/tigerlake/bootblock/report_platform.c
M src/soc/intel/tigerlake/lpm.c
M src/soc/intel/tigerlake/systemagent.c
M src/soc/intel/xeon_sp/cpx/chip.c
M src/soc/intel/xeon_sp/uncore.c
M src/southbridge/amd/agesa/hudson/hda.c
M src/southbridge/amd/agesa/hudson/hudson.c
M src/southbridge/amd/agesa/hudson/ide.c
M src/southbridge/amd/agesa/hudson/lpc.c
M src/southbridge/amd/agesa/hudson/pci.c
M src/southbridge/amd/agesa/hudson/pcie.c
M src/southbridge/amd/agesa/hudson/sata.c
M src/southbridge/amd/agesa/hudson/sd.c
M src/southbridge/amd/agesa/hudson/sm.c
M src/southbridge/amd/agesa/hudson/usb.c
M src/southbridge/amd/cimx/sb800/late.c
M src/southbridge/amd/pi/hudson/hda.c
M src/southbridge/amd/pi/hudson/hudson.c
M src/southbridge/amd/pi/hudson/ide.c
M src/southbridge/amd/pi/hudson/lpc.c
M src/southbridge/amd/pi/hudson/pci.c
M src/southbridge/amd/pi/hudson/pcie.c
M src/southbridge/amd/pi/hudson/sata.c
M src/southbridge/amd/pi/hudson/sd.c
M src/southbridge/amd/pi/hudson/sm.c
M src/southbridge/amd/pi/hudson/usb.c
M src/southbridge/intel/bd82x6x/azalia.c
M src/southbridge/intel/bd82x6x/lpc.c
M src/southbridge/intel/bd82x6x/me.c
M src/southbridge/intel/bd82x6x/me_8.x.c
M src/southbridge/intel/bd82x6x/pci.c
M src/southbridge/intel/bd82x6x/pcie.c
M src/southbridge/intel/bd82x6x/sata.c
M src/southbridge/intel/bd82x6x/smbus.c
M src/southbridge/intel/bd82x6x/usb_ehci.c
M src/southbridge/intel/bd82x6x/usb_xhci.c
M src/southbridge/intel/common/early_smbus.c
M src/southbridge/intel/i82371eb/bootblock.c
M src/southbridge/intel/i82371eb/early_pm.c
M src/southbridge/intel/i82371eb/early_smbus.c
M src/southbridge/intel/i82371eb/ide.c
M src/southbridge/intel/i82371eb/isa.c
M src/southbridge/intel/i82371eb/smbus.c
M src/southbridge/intel/i82371eb/usb.c
M src/southbridge/intel/i82801dx/ac97.c
M src/southbridge/intel/i82801dx/ide.c
M src/southbridge/intel/i82801dx/lpc.c
M src/southbridge/intel/i82801dx/pci.c
M src/southbridge/intel/i82801dx/usb.c
M src/southbridge/intel/i82801dx/usb2.c
M src/southbridge/intel/i82801gx/ac97.c
M src/southbridge/intel/i82801gx/azalia.c
M src/southbridge/intel/i82801gx/ide.c
M src/southbridge/intel/i82801gx/lpc.c
M src/southbridge/intel/i82801gx/pci.c
M src/southbridge/intel/i82801gx/pcie.c
M src/southbridge/intel/i82801gx/sata.c
M src/southbridge/intel/i82801gx/smbus.c
M src/southbridge/intel/i82801gx/usb.c
M src/southbridge/intel/i82801gx/usb_ehci.c
M src/southbridge/intel/i82801ix/azalia.c
M src/southbridge/intel/i82801ix/lpc.c
M src/southbridge/intel/i82801ix/pci.c
M src/southbridge/intel/i82801ix/pcie.c
M src/southbridge/intel/i82801ix/sata.c
M src/southbridge/intel/i82801ix/smbus.c
M src/southbridge/intel/i82801ix/thermal.c
M src/southbridge/intel/i82801ix/usb_ehci.c
M src/southbridge/intel/i82801jx/azalia.c
M src/southbridge/intel/i82801jx/lpc.c
M src/southbridge/intel/i82801jx/pci.c
M src/southbridge/intel/i82801jx/pcie.c
M src/southbridge/intel/i82801jx/sata.c
M src/southbridge/intel/i82801jx/smbus.c
M src/southbridge/intel/i82801jx/thermal.c
M src/southbridge/intel/i82801jx/usb_ehci.c
M src/southbridge/intel/i82870/ioapic.c
M src/southbridge/intel/i82870/pcibridge.c
M src/southbridge/intel/ibexpeak/azalia.c
M src/southbridge/intel/ibexpeak/lpc.c
M src/southbridge/intel/ibexpeak/me.c
M src/southbridge/intel/ibexpeak/sata.c
M src/southbridge/intel/ibexpeak/smbus.c
M src/southbridge/intel/ibexpeak/thermal.c
M src/southbridge/intel/ibexpeak/usb_ehci.c
M src/southbridge/intel/lynxpoint/azalia.c
M src/southbridge/intel/lynxpoint/lpc.c
M src/southbridge/intel/lynxpoint/me.c
M src/southbridge/intel/lynxpoint/pcie.c
M src/southbridge/intel/lynxpoint/sata.c
M src/southbridge/intel/lynxpoint/serialio.c
M src/southbridge/intel/lynxpoint/smbus.c
M src/southbridge/intel/lynxpoint/usb_ehci.c
M src/southbridge/intel/lynxpoint/usb_xhci.c
M src/southbridge/ricoh/rl5c476/rl5c476.c
M src/southbridge/ti/pci1x2x/pci1x2x.c
M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Pci22.h
M src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/IndustryStandard/Pci22.h
M src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/Pci22.h
263 files changed, 6,620 insertions(+), 6,622 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/39331/15

Change in coreboot[master]: src: Make PCI ID define names shorter

[Felix Singer (Code Review)]

Attention is currently required from: Raul Rangel, Patrick Rudolph, Mariusz Szafrański, Jonathan Zhang, Paul Menzel, Angel Pons, Jason Glenesk, Nico Huber, Anjaneya "Reddy" Chagam, Martin Roth, Marshall Dawson, Johnny Lin, Tim Wawrzynczak, Christian Walter, Suresh Bellampalli, Michal Motyl, Fred Reitberger, Felix Held, Tim Chu.
Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39331 )

Change subject: src: Make PCI ID define names shorter
......................................................................

Patch Set 15:

(1 comment)

Patchset:

PS15: 
Elyes, please ping me before you do any changes to my patches.

Change in coreboot[master]: src: Make PCI ID define names shorter

[Felix Singer (Code Review)]

Attention is currently required from: Raul Rangel, Patrick Rudolph, Mariusz Szafrański, Jonathan Zhang, Paul Menzel, Angel Pons, Jason Glenesk, Nico Huber, Anjaneya "Reddy" Chagam, Martin Roth, Marshall Dawson, Johnny Lin, Tim Wawrzynczak, Christian Walter, Suresh Bellampalli, Michal Motyl, Fred Reitberger, Felix Held, Tim Chu.
Hello build bot (Jenkins), Raul Rangel, Patrick Rudolph, Mariusz Szafrański, Jonathan Zhang, Arthur Heymans, Andrey Petrov, Patrick Rudolph, Anjaneya "Reddy" Chagam, Nico Huber, David Guckian, Johnny Lin, Christian Walter, Suresh Bellampalli, Michal Motyl, Fred Reitberger, Alexander Couzens, Werner Zeh, Tim Chu, Felix Held, Angel Pons, Michael Niewöhner, Jason Glenesk, Damien Zammit, Marshall Dawson, Tim Wawrzynczak, Vanessa Eusebio, David Guckian,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/39331

to look at the new patch set (#16).

Change subject: src: Make PCI ID define names shorter
......................................................................

src: Make PCI ID define names shorter

Shorten define names containing PCI_{DEVICE,VENDOR}_ID_ with
PCI_{DID,VID}_. Also, try to fix some spacing issues using the commands
below. An additional clean up of pci_ids.h is done in CB:61531.

* find -type f -exec sed -i 's/PCI_([DV])(EVICE|ENDOR)_ID_([_0-9A-Za-z]{2}([_0-9A-Za-z]{8})*[_0-9A-Za-z]{0,5})\t/PCI_\1ID_\3\t\t/g'

* find -type f -exec sed -i 's/PCI_([DV])(EVICE|ENDOR)_ID_([_0-9A-Za-z]*)/PCI_\1ID_\3/g'

Change-Id: If9027700f53b6d0d3964c26a41a1f9b8f62be178
Signed-off-by: Felix Singer 
---
M src/device/pci_rom.c
M src/drivers/aspeed/ast2050/ast2050.c
M src/drivers/broadcom/bcm57xx_aspm_disable.c
M src/drivers/generic/bayhub/bh720.c
M src/drivers/generic/bayhub_lv2/lv2.c
M src/drivers/genesyslogic/gl9750/gl9750.c
M src/drivers/genesyslogic/gl9755/gl9755.c
M src/drivers/genesyslogic/gl9763e/gl9763e.c
M src/drivers/intel/gma/opregion.c
M src/drivers/intel/i210/i210.c
M src/drivers/intel/ish/ish.c
M src/drivers/net/r8168.c
M src/drivers/ricoh/rce822/rce822.c
M src/drivers/siemens/nc_fpga/nc_fpga.c
M src/drivers/siemens/nc_fpga/nc_fpga_early.c
M src/drivers/usb/pci_xhci/pci_xhci.c
M src/drivers/wifi/generic/acpi.c
M src/drivers/wifi/generic/generic.c
M src/drivers/wifi/generic/smbios.c
M src/include/device/pci_ids.h
M src/mainboard/google/brya/variants/brask/ramstage.c
M src/mainboard/google/brya/variants/brya0/ramstage.c
M src/mainboard/google/brya/variants/brya4es/ramstage.c
M src/mainboard/google/brya/variants/kano/ramstage.c
M src/mainboard/google/hatch/variants/baseboard/mainboard.c
M src/mainboard/google/poppy/variants/atlas/mainboard.c
M src/mainboard/google/poppy/variants/nocturne/mainboard.c
M src/mainboard/intel/adlrvp/ramstage.c
M src/mainboard/lenovo/x60/mainboard.c
M src/mainboard/prodrive/hermes/devicetree.cb
M src/mainboard/siemens/mc_apl1/mainboard.c
M src/mainboard/siemens/mc_apl1/variants/mc_apl1/mainboard.c
M src/mainboard/siemens/mc_apl1/variants/mc_apl2/mainboard.c
M src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c
M src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c
M src/mainboard/siemens/mc_apl1/variants/mc_apl6/mainboard.c
M src/mainboard/siemens/mc_ehl/mainboard.c
M src/northbridge/amd/agesa/family14/northbridge.c
M src/northbridge/amd/agesa/family15tn/iommu.c
M src/northbridge/amd/agesa/family15tn/northbridge.c
M src/northbridge/amd/agesa/family16kb/northbridge.c
M src/northbridge/amd/pi/00730F01/iommu.c
M src/northbridge/amd/pi/00730F01/northbridge.c
M src/northbridge/intel/gm45/gma.c
M src/northbridge/intel/haswell/gma.c
M src/northbridge/intel/haswell/minihd.c
M src/northbridge/intel/haswell/northbridge.c
M src/northbridge/intel/haswell/pcie.c
M src/northbridge/intel/i440bx/northbridge.c
M src/northbridge/intel/i945/gma.c
M src/northbridge/intel/i945/northbridge.c
M src/northbridge/intel/ironlake/gma.c
M src/northbridge/intel/ironlake/northbridge.c
M src/northbridge/intel/pineview/gma.c
M src/northbridge/intel/sandybridge/gma.c
M src/northbridge/intel/sandybridge/northbridge.c
M src/northbridge/intel/sandybridge/pcie.c
M src/northbridge/intel/x4x/gma.c
M src/soc/amd/cezanne/data_fabric.c
M src/soc/amd/cezanne/root_complex.c
M src/soc/amd/common/block/acp/acp.c
M src/soc/amd/common/block/graphics/graphics.c
M src/soc/amd/common/block/hda/hda.c
M src/soc/amd/common/block/iommu/iommu.c
M src/soc/amd/common/block/lpc/lpc.c
M src/soc/amd/common/block/pci/pcie_gpp.c
M src/soc/amd/common/block/sata/sata.c
M src/soc/amd/common/block/smbus/sm.c
M src/soc/amd/picasso/data_fabric.c
M src/soc/amd/picasso/root_complex.c
M src/soc/amd/sabrina/data_fabric.c
M src/soc/amd/sabrina/root_complex.c
M src/soc/amd/sabrina/xhci.c
M src/soc/amd/stoneyridge/include/soc/pci_devs.h
M src/soc/amd/stoneyridge/northbridge.c
M src/soc/amd/stoneyridge/usb.c
M src/soc/cavium/common/pci/uart.c
M src/soc/intel/alderlake/bootblock/report_platform.c
M src/soc/intel/alderlake/chip.h
M src/soc/intel/alderlake/cpu.c
M src/soc/intel/alderlake/fsp_params.c
M src/soc/intel/alderlake/vr_config.c
M src/soc/intel/apollolake/report_platform.c
M src/soc/intel/baytrail/ehci.c
M src/soc/intel/baytrail/emmc.c
M src/soc/intel/baytrail/gfx.c
M src/soc/intel/baytrail/hda.c
M src/soc/intel/baytrail/lpe.c
M src/soc/intel/baytrail/lpss.c
M src/soc/intel/baytrail/northcluster.c
M src/soc/intel/baytrail/pcie.c
M src/soc/intel/baytrail/sata.c
M src/soc/intel/baytrail/sd.c
M src/soc/intel/baytrail/southcluster.c
M src/soc/intel/baytrail/xhci.c
M src/soc/intel/braswell/emmc.c
M src/soc/intel/braswell/gfx.c
M src/soc/intel/braswell/lpe.c
M src/soc/intel/braswell/lpss.c
M src/soc/intel/braswell/northcluster.c
M src/soc/intel/braswell/pcie.c
M src/soc/intel/braswell/sata.c
M src/soc/intel/braswell/sd.c
M src/soc/intel/braswell/southcluster.c
M src/soc/intel/braswell/xhci.c
M src/soc/intel/broadwell/gma.c
M src/soc/intel/broadwell/minihd.c
M src/soc/intel/broadwell/northbridge.c
M src/soc/intel/broadwell/pch/adsp.c
M src/soc/intel/broadwell/pch/hda.c
M src/soc/intel/broadwell/pch/lpc.c
M src/soc/intel/broadwell/pch/me.c
M src/soc/intel/broadwell/pch/pcie.c
M src/soc/intel/broadwell/pch/sata.c
M src/soc/intel/broadwell/pch/serialio.c
M src/soc/intel/broadwell/pch/usb_ehci.c
M src/soc/intel/broadwell/pch/usb_xhci.c
M src/soc/intel/cannonlake/bootblock/report_platform.c
M src/soc/intel/cannonlake/vr_config.c
M src/soc/intel/common/block/cnvi/cnvi.c
M src/soc/intel/common/block/cse/cse.c
M src/soc/intel/common/block/dsp/dsp.c
M src/soc/intel/common/block/dtt/dtt.c
M src/soc/intel/common/block/graphics/graphics.c
M src/soc/intel/common/block/hda/hda.c
M src/soc/intel/common/block/i2c/i2c.c
M src/soc/intel/common/block/ipu/ipu.c
M src/soc/intel/common/block/lpc/lpc.c
M src/soc/intel/common/block/p2sb/p2sb.c
M src/soc/intel/common/block/p2sb/p2sblib.c
M src/soc/intel/common/block/pcie/pcie.c
M src/soc/intel/common/block/pmc/pmc.c
M src/soc/intel/common/block/sata/sata.c
M src/soc/intel/common/block/scs/mmc.c
M src/soc/intel/common/block/scs/sd.c
M src/soc/intel/common/block/smbus/smbus.c
M src/soc/intel/common/block/spi/spi.c
M src/soc/intel/common/block/sram/sram.c
M src/soc/intel/common/block/systemagent/systemagent.c
M src/soc/intel/common/block/uart/uart.c
M src/soc/intel/common/block/usb4/usb4.c
M src/soc/intel/common/block/usb4/xhci.c
M src/soc/intel/common/block/xdci/xdci.c
M src/soc/intel/common/block/xhci/xhci.c
M src/soc/intel/denverton_ns/csme_ie_kt.c
M src/soc/intel/denverton_ns/lpc.c
M src/soc/intel/denverton_ns/npk.c
M src/soc/intel/denverton_ns/sata.c
M src/soc/intel/denverton_ns/systemagent.c
M src/soc/intel/denverton_ns/uart.c
M src/soc/intel/denverton_ns/xhci.c
M src/soc/intel/elkhartlake/bootblock/report_platform.c
M src/soc/intel/icelake/bootblock/report_platform.c
M src/soc/intel/jasperlake/bootblock/report_platform.c
M src/soc/intel/quark/ehci.c
M src/soc/intel/quark/gpio_i2c.c
M src/soc/intel/quark/lpc.c
M src/soc/intel/quark/northcluster.c
M src/soc/intel/quark/sd.c
M src/soc/intel/quark/spi.c
M src/soc/intel/quark/uart.c
M src/soc/intel/skylake/bootblock/report_platform.c
M src/soc/intel/skylake/graphics.c
M src/soc/intel/skylake/vr_config.c
M src/soc/intel/tigerlake/bootblock/report_platform.c
M src/soc/intel/tigerlake/lpm.c
M src/soc/intel/tigerlake/systemagent.c
M src/soc/intel/xeon_sp/cpx/chip.c
M src/soc/intel/xeon_sp/uncore.c
M src/southbridge/amd/agesa/hudson/hda.c
M src/southbridge/amd/agesa/hudson/hudson.c
M src/southbridge/amd/agesa/hudson/ide.c
M src/southbridge/amd/agesa/hudson/lpc.c
M src/southbridge/amd/agesa/hudson/pci.c
M src/southbridge/amd/agesa/hudson/pcie.c
M src/southbridge/amd/agesa/hudson/sata.c
M src/southbridge/amd/agesa/hudson/sd.c
M src/southbridge/amd/agesa/hudson/sm.c
M src/southbridge/amd/agesa/hudson/usb.c
M src/southbridge/amd/cimx/sb800/late.c
M src/southbridge/amd/pi/hudson/hda.c
M src/southbridge/amd/pi/hudson/hudson.c
M src/southbridge/amd/pi/hudson/ide.c
M src/southbridge/amd/pi/hudson/lpc.c
M src/southbridge/amd/pi/hudson/pci.c
M src/southbridge/amd/pi/hudson/pcie.c
M src/southbridge/amd/pi/hudson/sata.c
M src/southbridge/amd/pi/hudson/sd.c
M src/southbridge/amd/pi/hudson/sm.c
M src/southbridge/amd/pi/hudson/usb.c
M src/southbridge/intel/bd82x6x/azalia.c
M src/southbridge/intel/bd82x6x/lpc.c
M src/southbridge/intel/bd82x6x/me.c
M src/southbridge/intel/bd82x6x/me_8.x.c
M src/southbridge/intel/bd82x6x/pci.c
M src/southbridge/intel/bd82x6x/pcie.c
M src/southbridge/intel/bd82x6x/sata.c
M src/southbridge/intel/bd82x6x/smbus.c
M src/southbridge/intel/bd82x6x/usb_ehci.c
M src/southbridge/intel/bd82x6x/usb_xhci.c
M src/southbridge/intel/common/early_smbus.c
M src/southbridge/intel/i82371eb/bootblock.c
M src/southbridge/intel/i82371eb/early_pm.c
M src/southbridge/intel/i82371eb/early_smbus.c
M src/southbridge/intel/i82371eb/ide.c
M src/southbridge/intel/i82371eb/isa.c
M src/southbridge/intel/i82371eb/smbus.c
M src/southbridge/intel/i82371eb/usb.c
M src/southbridge/intel/i82801dx/ac97.c
M src/southbridge/intel/i82801dx/ide.c
M src/southbridge/intel/i82801dx/lpc.c
M src/southbridge/intel/i82801dx/pci.c
M src/southbridge/intel/i82801dx/usb.c
M src/southbridge/intel/i82801dx/usb2.c
M src/southbridge/intel/i82801gx/ac97.c
M src/southbridge/intel/i82801gx/azalia.c
M src/southbridge/intel/i82801gx/ide.c
M src/southbridge/intel/i82801gx/lpc.c
M src/southbridge/intel/i82801gx/pci.c
M src/southbridge/intel/i82801gx/pcie.c
M src/southbridge/intel/i82801gx/sata.c
M src/southbridge/intel/i82801gx/smbus.c
M src/southbridge/intel/i82801gx/usb.c
M src/southbridge/intel/i82801gx/usb_ehci.c
M src/southbridge/intel/i82801ix/azalia.c
M src/southbridge/intel/i82801ix/lpc.c
M src/southbridge/intel/i82801ix/pci.c
M src/southbridge/intel/i82801ix/pcie.c
M src/southbridge/intel/i82801ix/sata.c
M src/southbridge/intel/i82801ix/smbus.c
M src/southbridge/intel/i82801ix/thermal.c
M src/southbridge/intel/i82801ix/usb_ehci.c
M src/southbridge/intel/i82801jx/azalia.c
M src/southbridge/intel/i82801jx/lpc.c
M src/southbridge/intel/i82801jx/pci.c
M src/southbridge/intel/i82801jx/pcie.c
M src/southbridge/intel/i82801jx/sata.c
M src/southbridge/intel/i82801jx/smbus.c
M src/southbridge/intel/i82801jx/thermal.c
M src/southbridge/intel/i82801jx/usb_ehci.c
M src/southbridge/intel/i82870/ioapic.c
M src/southbridge/intel/i82870/pcibridge.c
M src/southbridge/intel/ibexpeak/azalia.c
M src/southbridge/intel/ibexpeak/lpc.c
M src/southbridge/intel/ibexpeak/me.c
M src/southbridge/intel/ibexpeak/sata.c
M src/southbridge/intel/ibexpeak/smbus.c
M src/southbridge/intel/ibexpeak/thermal.c
M src/southbridge/intel/ibexpeak/usb_ehci.c
M src/southbridge/intel/lynxpoint/azalia.c
M src/southbridge/intel/lynxpoint/lpc.c
M src/southbridge/intel/lynxpoint/me.c
M src/southbridge/intel/lynxpoint/pcie.c
M src/southbridge/intel/lynxpoint/sata.c
M src/southbridge/intel/lynxpoint/serialio.c
M src/southbridge/intel/lynxpoint/smbus.c
M src/southbridge/intel/lynxpoint/usb_ehci.c
M src/southbridge/intel/lynxpoint/usb_xhci.c
M src/southbridge/ricoh/rl5c476/rl5c476.c
M src/southbridge/ti/pci1x2x/pci1x2x.c
M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Pci22.h
M src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/IndustryStandard/Pci22.h
M src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/Pci22.h
263 files changed, 6,620 insertions(+), 6,622 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/39331/16

Change in coreboot[master]: src: Make PCI ID define names shorter

[Felix Singer (Code Review)]

Attention is currently required from: Raul Rangel, Patrick Rudolph, Mariusz Szafrański, Jonathan Zhang, Paul Menzel, Angel Pons, Jason Glenesk, Nico Huber, Anjaneya "Reddy" Chagam, Martin Roth, Marshall Dawson, Johnny Lin, Tim Wawrzynczak, Christian Walter, Suresh Bellampalli, Michal Motyl, Fred Reitberger, Felix Held, Tim Chu.
Hello build bot (Jenkins), Raul Rangel, Patrick Rudolph, Mariusz Szafrański, Jonathan Zhang, Arthur Heymans, Andrey Petrov, Patrick Rudolph, Anjaneya "Reddy" Chagam, Nico Huber, David Guckian, Johnny Lin, Christian Walter, Suresh Bellampalli, Michal Motyl, Fred Reitberger, Alexander Couzens, Werner Zeh, Tim Chu, Felix Held, Angel Pons, Michael Niewöhner, Jason Glenesk, Damien Zammit, Marshall Dawson, Tim Wawrzynczak, Vanessa Eusebio, David Guckian,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/39331

to look at the new patch set (#17).

Change subject: src: Make PCI ID define names shorter
......................................................................

src: Make PCI ID define names shorter

Shorten define names containing PCI_{DEVICE,VENDOR}_ID_ with
PCI_{DID,VID}_ using the commands below, which also take care of some
spacing issues. An additional clean up of pci_ids.h is done in
CB:61531.

Used commands:
* find -type f -exec sed -i 's/PCI_([DV])(EVICE|ENDOR)_ID_([_0-9A-Za-z]{2}([_0-9A-Za-z]{8})*[_0-9A-Za-z]{0,5})\t/PCI_\1ID_\3\t\t/g'

* find -type f -exec sed -i 's/PCI_([DV])(EVICE|ENDOR)_ID_([_0-9A-Za-z]*)/PCI_\1ID_\3/g'

Change-Id: If9027700f53b6d0d3964c26a41a1f9b8f62be178
Signed-off-by: Felix Singer 
---
M src/device/pci_rom.c
M src/drivers/aspeed/ast2050/ast2050.c
M src/drivers/broadcom/bcm57xx_aspm_disable.c
M src/drivers/generic/bayhub/bh720.c
M src/drivers/generic/bayhub_lv2/lv2.c
M src/drivers/genesyslogic/gl9750/gl9750.c
M src/drivers/genesyslogic/gl9755/gl9755.c
M src/drivers/genesyslogic/gl9763e/gl9763e.c
M src/drivers/intel/gma/opregion.c
M src/drivers/intel/i210/i210.c
M src/drivers/intel/ish/ish.c
M src/drivers/net/r8168.c
M src/drivers/ricoh/rce822/rce822.c
M src/drivers/siemens/nc_fpga/nc_fpga.c
M src/drivers/siemens/nc_fpga/nc_fpga_early.c
M src/drivers/usb/pci_xhci/pci_xhci.c
M src/drivers/wifi/generic/acpi.c
M src/drivers/wifi/generic/generic.c
M src/drivers/wifi/generic/smbios.c
M src/include/device/pci_ids.h
M src/mainboard/google/brya/variants/brask/ramstage.c
M src/mainboard/google/brya/variants/brya0/ramstage.c
M src/mainboard/google/brya/variants/brya4es/ramstage.c
M src/mainboard/google/brya/variants/kano/ramstage.c
M src/mainboard/google/hatch/variants/baseboard/mainboard.c
M src/mainboard/google/poppy/variants/atlas/mainboard.c
M src/mainboard/google/poppy/variants/nocturne/mainboard.c
M src/mainboard/intel/adlrvp/ramstage.c
M src/mainboard/lenovo/x60/mainboard.c
M src/mainboard/prodrive/hermes/devicetree.cb
M src/mainboard/siemens/mc_apl1/mainboard.c
M src/mainboard/siemens/mc_apl1/variants/mc_apl1/mainboard.c
M src/mainboard/siemens/mc_apl1/variants/mc_apl2/mainboard.c
M src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c
M src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c
M src/mainboard/siemens/mc_apl1/variants/mc_apl6/mainboard.c
M src/mainboard/siemens/mc_ehl/mainboard.c
M src/northbridge/amd/agesa/family14/northbridge.c
M src/northbridge/amd/agesa/family15tn/iommu.c
M src/northbridge/amd/agesa/family15tn/northbridge.c
M src/northbridge/amd/agesa/family16kb/northbridge.c
M src/northbridge/amd/pi/00730F01/iommu.c
M src/northbridge/amd/pi/00730F01/northbridge.c
M src/northbridge/intel/gm45/gma.c
M src/northbridge/intel/haswell/gma.c
M src/northbridge/intel/haswell/minihd.c
M src/northbridge/intel/haswell/northbridge.c
M src/northbridge/intel/haswell/pcie.c
M src/northbridge/intel/i440bx/northbridge.c
M src/northbridge/intel/i945/gma.c
M src/northbridge/intel/i945/northbridge.c
M src/northbridge/intel/ironlake/gma.c
M src/northbridge/intel/ironlake/northbridge.c
M src/northbridge/intel/pineview/gma.c
M src/northbridge/intel/sandybridge/gma.c
M src/northbridge/intel/sandybridge/northbridge.c
M src/northbridge/intel/sandybridge/pcie.c
M src/northbridge/intel/x4x/gma.c
M src/soc/amd/cezanne/data_fabric.c
M src/soc/amd/cezanne/root_complex.c
M src/soc/amd/common/block/acp/acp.c
M src/soc/amd/common/block/graphics/graphics.c
M src/soc/amd/common/block/hda/hda.c
M src/soc/amd/common/block/iommu/iommu.c
M src/soc/amd/common/block/lpc/lpc.c
M src/soc/amd/common/block/pci/pcie_gpp.c
M src/soc/amd/common/block/sata/sata.c
M src/soc/amd/common/block/smbus/sm.c
M src/soc/amd/picasso/data_fabric.c
M src/soc/amd/picasso/root_complex.c
M src/soc/amd/sabrina/data_fabric.c
M src/soc/amd/sabrina/root_complex.c
M src/soc/amd/sabrina/xhci.c
M src/soc/amd/stoneyridge/include/soc/pci_devs.h
M src/soc/amd/stoneyridge/northbridge.c
M src/soc/amd/stoneyridge/usb.c
M src/soc/cavium/common/pci/uart.c
M src/soc/intel/alderlake/bootblock/report_platform.c
M src/soc/intel/alderlake/chip.h
M src/soc/intel/alderlake/cpu.c
M src/soc/intel/alderlake/fsp_params.c
M src/soc/intel/alderlake/vr_config.c
M src/soc/intel/apollolake/report_platform.c
M src/soc/intel/baytrail/ehci.c
M src/soc/intel/baytrail/emmc.c
M src/soc/intel/baytrail/gfx.c
M src/soc/intel/baytrail/hda.c
M src/soc/intel/baytrail/lpe.c
M src/soc/intel/baytrail/lpss.c
M src/soc/intel/baytrail/northcluster.c
M src/soc/intel/baytrail/pcie.c
M src/soc/intel/baytrail/sata.c
M src/soc/intel/baytrail/sd.c
M src/soc/intel/baytrail/southcluster.c
M src/soc/intel/baytrail/xhci.c
M src/soc/intel/braswell/emmc.c
M src/soc/intel/braswell/gfx.c
M src/soc/intel/braswell/lpe.c
M src/soc/intel/braswell/lpss.c
M src/soc/intel/braswell/northcluster.c
M src/soc/intel/braswell/pcie.c
M src/soc/intel/braswell/sata.c
M src/soc/intel/braswell/sd.c
M src/soc/intel/braswell/southcluster.c
M src/soc/intel/braswell/xhci.c
M src/soc/intel/broadwell/gma.c
M src/soc/intel/broadwell/minihd.c
M src/soc/intel/broadwell/northbridge.c
M src/soc/intel/broadwell/pch/adsp.c
M src/soc/intel/broadwell/pch/hda.c
M src/soc/intel/broadwell/pch/lpc.c
M src/soc/intel/broadwell/pch/me.c
M src/soc/intel/broadwell/pch/pcie.c
M src/soc/intel/broadwell/pch/sata.c
M src/soc/intel/broadwell/pch/serialio.c
M src/soc/intel/broadwell/pch/usb_ehci.c
M src/soc/intel/broadwell/pch/usb_xhci.c
M src/soc/intel/cannonlake/bootblock/report_platform.c
M src/soc/intel/cannonlake/vr_config.c
M src/soc/intel/common/block/cnvi/cnvi.c
M src/soc/intel/common/block/cse/cse.c
M src/soc/intel/common/block/dsp/dsp.c
M src/soc/intel/common/block/dtt/dtt.c
M src/soc/intel/common/block/graphics/graphics.c
M src/soc/intel/common/block/hda/hda.c
M src/soc/intel/common/block/i2c/i2c.c
M src/soc/intel/common/block/ipu/ipu.c
M src/soc/intel/common/block/lpc/lpc.c
M src/soc/intel/common/block/p2sb/p2sb.c
M src/soc/intel/common/block/p2sb/p2sblib.c
M src/soc/intel/common/block/pcie/pcie.c
M src/soc/intel/common/block/pmc/pmc.c
M src/soc/intel/common/block/sata/sata.c
M src/soc/intel/common/block/scs/mmc.c
M src/soc/intel/common/block/scs/sd.c
M src/soc/intel/common/block/smbus/smbus.c
M src/soc/intel/common/block/spi/spi.c
M src/soc/intel/common/block/sram/sram.c
M src/soc/intel/common/block/systemagent/systemagent.c
M src/soc/intel/common/block/uart/uart.c
M src/soc/intel/common/block/usb4/usb4.c
M src/soc/intel/common/block/usb4/xhci.c
M src/soc/intel/common/block/xdci/xdci.c
M src/soc/intel/common/block/xhci/xhci.c
M src/soc/intel/denverton_ns/csme_ie_kt.c
M src/soc/intel/denverton_ns/lpc.c
M src/soc/intel/denverton_ns/npk.c
M src/soc/intel/denverton_ns/sata.c
M src/soc/intel/denverton_ns/systemagent.c
M src/soc/intel/denverton_ns/uart.c
M src/soc/intel/denverton_ns/xhci.c
M src/soc/intel/elkhartlake/bootblock/report_platform.c
M src/soc/intel/icelake/bootblock/report_platform.c
M src/soc/intel/jasperlake/bootblock/report_platform.c
M src/soc/intel/quark/ehci.c
M src/soc/intel/quark/gpio_i2c.c
M src/soc/intel/quark/lpc.c
M src/soc/intel/quark/northcluster.c
M src/soc/intel/quark/sd.c
M src/soc/intel/quark/spi.c
M src/soc/intel/quark/uart.c
M src/soc/intel/skylake/bootblock/report_platform.c
M src/soc/intel/skylake/graphics.c
M src/soc/intel/skylake/vr_config.c
M src/soc/intel/tigerlake/bootblock/report_platform.c
M src/soc/intel/tigerlake/lpm.c
M src/soc/intel/tigerlake/systemagent.c
M src/soc/intel/xeon_sp/cpx/chip.c
M src/soc/intel/xeon_sp/uncore.c
M src/southbridge/amd/agesa/hudson/hda.c
M src/southbridge/amd/agesa/hudson/hudson.c
M src/southbridge/amd/agesa/hudson/ide.c
M src/southbridge/amd/agesa/hudson/lpc.c
M src/southbridge/amd/agesa/hudson/pci.c
M src/southbridge/amd/agesa/hudson/pcie.c
M src/southbridge/amd/agesa/hudson/sata.c
M src/southbridge/amd/agesa/hudson/sd.c
M src/southbridge/amd/agesa/hudson/sm.c
M src/southbridge/amd/agesa/hudson/usb.c
M src/southbridge/amd/cimx/sb800/late.c
M src/southbridge/amd/pi/hudson/hda.c
M src/southbridge/amd/pi/hudson/hudson.c
M src/southbridge/amd/pi/hudson/ide.c
M src/southbridge/amd/pi/hudson/lpc.c
M src/southbridge/amd/pi/hudson/pci.c
M src/southbridge/amd/pi/hudson/pcie.c
M src/southbridge/amd/pi/hudson/sata.c
M src/southbridge/amd/pi/hudson/sd.c
M src/southbridge/amd/pi/hudson/sm.c
M src/southbridge/amd/pi/hudson/usb.c
M src/southbridge/intel/bd82x6x/azalia.c
M src/southbridge/intel/bd82x6x/lpc.c
M src/southbridge/intel/bd82x6x/me.c
M src/southbridge/intel/bd82x6x/me_8.x.c
M src/southbridge/intel/bd82x6x/pci.c
M src/southbridge/intel/bd82x6x/pcie.c
M src/southbridge/intel/bd82x6x/sata.c
M src/southbridge/intel/bd82x6x/smbus.c
M src/southbridge/intel/bd82x6x/usb_ehci.c
M src/southbridge/intel/bd82x6x/usb_xhci.c
M src/southbridge/intel/common/early_smbus.c
M src/southbridge/intel/i82371eb/bootblock.c
M src/southbridge/intel/i82371eb/early_pm.c
M src/southbridge/intel/i82371eb/early_smbus.c
M src/southbridge/intel/i82371eb/ide.c
M src/southbridge/intel/i82371eb/isa.c
M src/southbridge/intel/i82371eb/smbus.c
M src/southbridge/intel/i82371eb/usb.c
M src/southbridge/intel/i82801dx/ac97.c
M src/southbridge/intel/i82801dx/ide.c
M src/southbridge/intel/i82801dx/lpc.c
M src/southbridge/intel/i82801dx/pci.c
M src/southbridge/intel/i82801dx/usb.c
M src/southbridge/intel/i82801dx/usb2.c
M src/southbridge/intel/i82801gx/ac97.c
M src/southbridge/intel/i82801gx/azalia.c
M src/southbridge/intel/i82801gx/ide.c
M src/southbridge/intel/i82801gx/lpc.c
M src/southbridge/intel/i82801gx/pci.c
M src/southbridge/intel/i82801gx/pcie.c
M src/southbridge/intel/i82801gx/sata.c
M src/southbridge/intel/i82801gx/smbus.c
M src/southbridge/intel/i82801gx/usb.c
M src/southbridge/intel/i82801gx/usb_ehci.c
M src/southbridge/intel/i82801ix/azalia.c
M src/southbridge/intel/i82801ix/lpc.c
M src/southbridge/intel/i82801ix/pci.c
M src/southbridge/intel/i82801ix/pcie.c
M src/southbridge/intel/i82801ix/sata.c
M src/southbridge/intel/i82801ix/smbus.c
M src/southbridge/intel/i82801ix/thermal.c
M src/southbridge/intel/i82801ix/usb_ehci.c
M src/southbridge/intel/i82801jx/azalia.c
M src/southbridge/intel/i82801jx/lpc.c
M src/southbridge/intel/i82801jx/pci.c
M src/southbridge/intel/i82801jx/pcie.c
M src/southbridge/intel/i82801jx/sata.c
M src/southbridge/intel/i82801jx/smbus.c
M src/southbridge/intel/i82801jx/thermal.c
M src/southbridge/intel/i82801jx/usb_ehci.c
M src/southbridge/intel/i82870/ioapic.c
M src/southbridge/intel/i82870/pcibridge.c
M src/southbridge/intel/ibexpeak/azalia.c
M src/southbridge/intel/ibexpeak/lpc.c
M src/southbridge/intel/ibexpeak/me.c
M src/southbridge/intel/ibexpeak/sata.c
M src/southbridge/intel/ibexpeak/smbus.c
M src/southbridge/intel/ibexpeak/thermal.c
M src/southbridge/intel/ibexpeak/usb_ehci.c
M src/southbridge/intel/lynxpoint/azalia.c
M src/southbridge/intel/lynxpoint/lpc.c
M src/southbridge/intel/lynxpoint/me.c
M src/southbridge/intel/lynxpoint/pcie.c
M src/southbridge/intel/lynxpoint/sata.c
M src/southbridge/intel/lynxpoint/serialio.c
M src/southbridge/intel/lynxpoint/smbus.c
M src/southbridge/intel/lynxpoint/usb_ehci.c
M src/southbridge/intel/lynxpoint/usb_xhci.c
M src/southbridge/ricoh/rl5c476/rl5c476.c
M src/southbridge/ti/pci1x2x/pci1x2x.c
M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Pci22.h
M src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/IndustryStandard/Pci22.h
M src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/Pci22.h
263 files changed, 6,620 insertions(+), 6,622 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/39331/17

Change in coreboot[master]: src: Make PCI ID define names shorter

[Michael Niewöhner (Code Review)]

Attention is currently required from: Felix Singer, Raul Rangel, Patrick Rudolph, Mariusz Szafrański, Jonathan Zhang, Paul Menzel, Angel Pons, Jason Glenesk, Nico Huber, Anjaneya "Reddy" Chagam, Martin Roth, Marshall Dawson, Johnny Lin, Tim Wawrzynczak, Christian Walter, Suresh Bellampalli, Michal Motyl, Fred Reitberger, Felix Held, Tim Chu.
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39331 )

Change subject: src: Make PCI ID define names shorter
......................................................................

Patch Set 17: Code-Review+2

Change in coreboot[master]: src: Make PCI ID define names shorter

[Felix Singer (Code Review)]

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/39331 )

Change subject: src: Make PCI ID define names shorter
......................................................................

src: Make PCI ID define names shorter

Shorten define names containing PCI_{DEVICE,VENDOR}_ID_ with
PCI_{DID,VID}_ using the commands below, which also take care of some
spacing issues. An additional clean up of pci_ids.h is done in
CB:61531.

Used commands:
* find -type f -exec sed -i 's/PCI_([DV])(EVICE|ENDOR)_ID_([_0-9A-Za-z]{2}([_0-9A-Za-z]{8})*[_0-9A-Za-z]{0,5})\t/PCI_\1ID_\3\t\t/g'

* find -type f -exec sed -i 's/PCI_([DV])(EVICE|ENDOR)_ID_([_0-9A-Za-z]*)/PCI_\1ID_\3/g'

Change-Id: If9027700f53b6d0d3964c26a41a1f9b8f62be178
Signed-off-by: Felix Singer 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39331
Tested-by: build bot (Jenkins) 
Reviewed-by: Michael Niewöhner 
---
M src/device/pci_rom.c
M src/drivers/aspeed/ast2050/ast2050.c
M src/drivers/broadcom/bcm57xx_aspm_disable.c
M src/drivers/generic/bayhub/bh720.c
M src/drivers/generic/bayhub_lv2/lv2.c
M src/drivers/genesyslogic/gl9750/gl9750.c
M src/drivers/genesyslogic/gl9755/gl9755.c
M src/drivers/genesyslogic/gl9763e/gl9763e.c
M src/drivers/intel/gma/opregion.c
M src/drivers/intel/i210/i210.c
M src/drivers/intel/ish/ish.c
M src/drivers/net/r8168.c
M src/drivers/ricoh/rce822/rce822.c
M src/drivers/siemens/nc_fpga/nc_fpga.c
M src/drivers/siemens/nc_fpga/nc_fpga_early.c
M src/drivers/usb/pci_xhci/pci_xhci.c
M src/drivers/wifi/generic/acpi.c
M src/drivers/wifi/generic/generic.c
M src/drivers/wifi/generic/smbios.c
M src/include/device/pci_ids.h
M src/mainboard/google/brya/variants/brask/ramstage.c
M src/mainboard/google/brya/variants/brya0/ramstage.c
M src/mainboard/google/brya/variants/brya4es/ramstage.c
M src/mainboard/google/brya/variants/kano/ramstage.c
M src/mainboard/google/hatch/variants/baseboard/mainboard.c
M src/mainboard/google/poppy/variants/atlas/mainboard.c
M src/mainboard/google/poppy/variants/nocturne/mainboard.c
M src/mainboard/intel/adlrvp/ramstage.c
M src/mainboard/lenovo/x60/mainboard.c
M src/mainboard/prodrive/hermes/devicetree.cb
M src/mainboard/siemens/mc_apl1/mainboard.c
M src/mainboard/siemens/mc_apl1/variants/mc_apl1/mainboard.c
M src/mainboard/siemens/mc_apl1/variants/mc_apl2/mainboard.c
M src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c
M src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c
M src/mainboard/siemens/mc_apl1/variants/mc_apl6/mainboard.c
M src/mainboard/siemens/mc_ehl/mainboard.c
M src/northbridge/amd/agesa/family14/northbridge.c
M src/northbridge/amd/agesa/family15tn/iommu.c
M src/northbridge/amd/agesa/family15tn/northbridge.c
M src/northbridge/amd/agesa/family16kb/northbridge.c
M src/northbridge/amd/pi/00730F01/iommu.c
M src/northbridge/amd/pi/00730F01/northbridge.c
M src/northbridge/intel/gm45/gma.c
M src/northbridge/intel/haswell/gma.c
M src/northbridge/intel/haswell/minihd.c
M src/northbridge/intel/haswell/northbridge.c
M src/northbridge/intel/haswell/pcie.c
M src/northbridge/intel/i440bx/northbridge.c
M src/northbridge/intel/i945/gma.c
M src/northbridge/intel/i945/northbridge.c
M src/northbridge/intel/ironlake/gma.c
M src/northbridge/intel/ironlake/northbridge.c
M src/northbridge/intel/pineview/gma.c
M src/northbridge/intel/sandybridge/gma.c
M src/northbridge/intel/sandybridge/northbridge.c
M src/northbridge/intel/sandybridge/pcie.c
M src/northbridge/intel/x4x/gma.c
M src/soc/amd/cezanne/data_fabric.c
M src/soc/amd/cezanne/root_complex.c
M src/soc/amd/common/block/acp/acp.c
M src/soc/amd/common/block/graphics/graphics.c
M src/soc/amd/common/block/hda/hda.c
M src/soc/amd/common/block/iommu/iommu.c
M src/soc/amd/common/block/lpc/lpc.c
M src/soc/amd/common/block/pci/pcie_gpp.c
M src/soc/amd/common/block/sata/sata.c
M src/soc/amd/common/block/smbus/sm.c
M src/soc/amd/picasso/data_fabric.c
M src/soc/amd/picasso/root_complex.c
M src/soc/amd/sabrina/data_fabric.c
M src/soc/amd/sabrina/root_complex.c
M src/soc/amd/sabrina/xhci.c
M src/soc/amd/stoneyridge/include/soc/pci_devs.h
M src/soc/amd/stoneyridge/northbridge.c
M src/soc/amd/stoneyridge/usb.c
M src/soc/cavium/common/pci/uart.c
M src/soc/intel/alderlake/bootblock/report_platform.c
M src/soc/intel/alderlake/chip.h
M src/soc/intel/alderlake/cpu.c
M src/soc/intel/alderlake/fsp_params.c
M src/soc/intel/alderlake/vr_config.c
M src/soc/intel/apollolake/report_platform.c
M src/soc/intel/baytrail/ehci.c
M src/soc/intel/baytrail/emmc.c
M src/soc/intel/baytrail/gfx.c
M src/soc/intel/baytrail/hda.c
M src/soc/intel/baytrail/lpe.c
M src/soc/intel/baytrail/lpss.c
M src/soc/intel/baytrail/northcluster.c
M src/soc/intel/baytrail/pcie.c
M src/soc/intel/baytrail/sata.c
M src/soc/intel/baytrail/sd.c
M src/soc/intel/baytrail/southcluster.c
M src/soc/intel/baytrail/xhci.c
M src/soc/intel/braswell/emmc.c
M src/soc/intel/braswell/gfx.c
M src/soc/intel/braswell/lpe.c
M src/soc/intel/braswell/lpss.c
M src/soc/intel/braswell/northcluster.c
M src/soc/intel/braswell/pcie.c
M src/soc/intel/braswell/sata.c
M src/soc/intel/braswell/sd.c
M src/soc/intel/braswell/southcluster.c
M src/soc/intel/braswell/xhci.c
M src/soc/intel/broadwell/gma.c
M src/soc/intel/broadwell/minihd.c
M src/soc/intel/broadwell/northbridge.c
M src/soc/intel/broadwell/pch/adsp.c
M src/soc/intel/broadwell/pch/hda.c
M src/soc/intel/broadwell/pch/lpc.c
M src/soc/intel/broadwell/pch/me.c
M src/soc/intel/broadwell/pch/pcie.c
M src/soc/intel/broadwell/pch/sata.c
M src/soc/intel/broadwell/pch/serialio.c
M src/soc/intel/broadwell/pch/usb_ehci.c
M src/soc/intel/broadwell/pch/usb_xhci.c
M src/soc/intel/cannonlake/bootblock/report_platform.c
M src/soc/intel/cannonlake/vr_config.c
M src/soc/intel/common/block/cnvi/cnvi.c
M src/soc/intel/common/block/cse/cse.c
M src/soc/intel/common/block/dsp/dsp.c
M src/soc/intel/common/block/dtt/dtt.c
M src/soc/intel/common/block/graphics/graphics.c
M src/soc/intel/common/block/hda/hda.c
M src/soc/intel/common/block/i2c/i2c.c
M src/soc/intel/common/block/ipu/ipu.c
M src/soc/intel/common/block/lpc/lpc.c
M src/soc/intel/common/block/p2sb/p2sb.c
M src/soc/intel/common/block/p2sb/p2sblib.c
M src/soc/intel/common/block/pcie/pcie.c
M src/soc/intel/common/block/pmc/pmc.c
M src/soc/intel/common/block/sata/sata.c
M src/soc/intel/common/block/scs/mmc.c
M src/soc/intel/common/block/scs/sd.c
M src/soc/intel/common/block/smbus/smbus.c
M src/soc/intel/common/block/spi/spi.c
M src/soc/intel/common/block/sram/sram.c
M src/soc/intel/common/block/systemagent/systemagent.c
M src/soc/intel/common/block/uart/uart.c
M src/soc/intel/common/block/usb4/usb4.c
M src/soc/intel/common/block/usb4/xhci.c
M src/soc/intel/common/block/xdci/xdci.c
M src/soc/intel/common/block/xhci/xhci.c
M src/soc/intel/denverton_ns/csme_ie_kt.c
M src/soc/intel/denverton_ns/lpc.c
M src/soc/intel/denverton_ns/npk.c
M src/soc/intel/denverton_ns/sata.c
M src/soc/intel/denverton_ns/systemagent.c
M src/soc/intel/denverton_ns/uart.c
M src/soc/intel/denverton_ns/xhci.c
M src/soc/intel/elkhartlake/bootblock/report_platform.c
M src/soc/intel/icelake/bootblock/report_platform.c
M src/soc/intel/jasperlake/bootblock/report_platform.c
M src/soc/intel/quark/ehci.c
M src/soc/intel/quark/gpio_i2c.c
M src/soc/intel/quark/lpc.c
M src/soc/intel/quark/northcluster.c
M src/soc/intel/quark/sd.c
M src/soc/intel/quark/spi.c
M src/soc/intel/quark/uart.c
M src/soc/intel/skylake/bootblock/report_platform.c
M src/soc/intel/skylake/graphics.c
M src/soc/intel/skylake/vr_config.c
M src/soc/intel/tigerlake/bootblock/report_platform.c
M src/soc/intel/tigerlake/lpm.c
M src/soc/intel/tigerlake/systemagent.c
M src/soc/intel/xeon_sp/cpx/chip.c
M src/soc/intel/xeon_sp/uncore.c
M src/southbridge/amd/agesa/hudson/hda.c
M src/southbridge/amd/agesa/hudson/hudson.c
M src/southbridge/amd/agesa/hudson/ide.c
M src/southbridge/amd/agesa/hudson/lpc.c
M src/southbridge/amd/agesa/hudson/pci.c
M src/southbridge/amd/agesa/hudson/pcie.c
M src/southbridge/amd/agesa/hudson/sata.c
M src/southbridge/amd/agesa/hudson/sd.c
M src/southbridge/amd/agesa/hudson/sm.c
M src/southbridge/amd/agesa/hudson/usb.c
M src/southbridge/amd/cimx/sb800/late.c
M src/southbridge/amd/pi/hudson/hda.c
M src/southbridge/amd/pi/hudson/hudson.c
M src/southbridge/amd/pi/hudson/ide.c
M src/southbridge/amd/pi/hudson/lpc.c
M src/southbridge/amd/pi/hudson/pci.c
M src/southbridge/amd/pi/hudson/pcie.c
M src/southbridge/amd/pi/hudson/sata.c
M src/southbridge/amd/pi/hudson/sd.c
M src/southbridge/amd/pi/hudson/sm.c
M src/southbridge/amd/pi/hudson/usb.c
M src/southbridge/intel/bd82x6x/azalia.c
M src/southbridge/intel/bd82x6x/lpc.c
M src/southbridge/intel/bd82x6x/me.c
M src/southbridge/intel/bd82x6x/me_8.x.c
M src/southbridge/intel/bd82x6x/pci.c
M src/southbridge/intel/bd82x6x/pcie.c
M src/southbridge/intel/bd82x6x/sata.c
M src/southbridge/intel/bd82x6x/smbus.c
M src/southbridge/intel/bd82x6x/usb_ehci.c
M src/southbridge/intel/bd82x6x/usb_xhci.c
M src/southbridge/intel/common/early_smbus.c
M src/southbridge/intel/i82371eb/bootblock.c
M src/southbridge/intel/i82371eb/early_pm.c
M src/southbridge/intel/i82371eb/early_smbus.c
M src/southbridge/intel/i82371eb/ide.c
M src/southbridge/intel/i82371eb/isa.c
M src/southbridge/intel/i82371eb/smbus.c
M src/southbridge/intel/i82371eb/usb.c
M src/southbridge/intel/i82801dx/ac97.c
M src/southbridge/intel/i82801dx/ide.c
M src/southbridge/intel/i82801dx/lpc.c
M src/southbridge/intel/i82801dx/pci.c
M src/southbridge/intel/i82801dx/usb.c
M src/southbridge/intel/i82801dx/usb2.c
M src/southbridge/intel/i82801gx/ac97.c
M src/southbridge/intel/i82801gx/azalia.c
M src/southbridge/intel/i82801gx/ide.c
M src/southbridge/intel/i82801gx/lpc.c
M src/southbridge/intel/i82801gx/pci.c
M src/southbridge/intel/i82801gx/pcie.c
M src/southbridge/intel/i82801gx/sata.c
M src/southbridge/intel/i82801gx/smbus.c
M src/southbridge/intel/i82801gx/usb.c
M src/southbridge/intel/i82801gx/usb_ehci.c
M src/southbridge/intel/i82801ix/azalia.c
M src/southbridge/intel/i82801ix/lpc.c
M src/southbridge/intel/i82801ix/pci.c
M src/southbridge/intel/i82801ix/pcie.c
M src/southbridge/intel/i82801ix/sata.c
M src/southbridge/intel/i82801ix/smbus.c
M src/southbridge/intel/i82801ix/thermal.c
M src/southbridge/intel/i82801ix/usb_ehci.c
M src/southbridge/intel/i82801jx/azalia.c
M src/southbridge/intel/i82801jx/lpc.c
M src/southbridge/intel/i82801jx/pci.c
M src/southbridge/intel/i82801jx/pcie.c
M src/southbridge/intel/i82801jx/sata.c
M src/southbridge/intel/i82801jx/smbus.c
M src/southbridge/intel/i82801jx/thermal.c
M src/southbridge/intel/i82801jx/usb_ehci.c
M src/southbridge/intel/i82870/ioapic.c
M src/southbridge/intel/i82870/pcibridge.c
M src/southbridge/intel/ibexpeak/azalia.c
M src/southbridge/intel/ibexpeak/lpc.c
M src/southbridge/intel/ibexpeak/me.c
M src/southbridge/intel/ibexpeak/sata.c
M src/southbridge/intel/ibexpeak/smbus.c
M src/southbridge/intel/ibexpeak/thermal.c
M src/southbridge/intel/ibexpeak/usb_ehci.c
M src/southbridge/intel/lynxpoint/azalia.c
M src/southbridge/intel/lynxpoint/lpc.c
M src/southbridge/intel/lynxpoint/me.c
M src/southbridge/intel/lynxpoint/pcie.c
M src/southbridge/intel/lynxpoint/sata.c
M src/southbridge/intel/lynxpoint/serialio.c
M src/southbridge/intel/lynxpoint/smbus.c
M src/southbridge/intel/lynxpoint/usb_ehci.c
M src/southbridge/intel/lynxpoint/usb_xhci.c
M src/southbridge/ricoh/rl5c476/rl5c476.c
M src/southbridge/ti/pci1x2x/pci1x2x.c
M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Pci22.h
M src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/IndustryStandard/Pci22.h
M src/vendorcode/intel/edk2/edk2-stable202111/MdePkg/Include/IndustryStandard/Pci22.h
263 files changed, 6,620 insertions(+), 6,622 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Michael Niewöhner: Looks good to me, approved