Change in coreboot[master]: soc/mediatek/mt8192: add rtc MT6359P driver - coreboot-gerrit

14 Oct 2020

Yidi Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46395 )
Change subject: soc/mediatek/mt8192: add rtc MT6359P driver
......................................................................
soc/mediatek/mt8192: add rtc MT6359P driver
Add rtc MT6359P driver.
TEST=boot asurada
Signed-off-by: Yuchen Huang yuchen.huang@mediatek.corp-partner.google.com
Change-Id: I57d6738fdec148c7458b2024a0a8225415ca2f3e
---
M src/soc/mediatek/common/include/soc/rtc_common.h
M src/soc/mediatek/common/rtc.c
M src/soc/mediatek/mt8192/Makefile.inc
M src/soc/mediatek/mt8192/bootblock.c
A src/soc/mediatek/mt8192/include/soc/rtc.h
A src/soc/mediatek/mt8192/rtc.c
6 files changed, 694 insertions(+), 25 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/46395/1

diff --git a/src/soc/mediatek/common/include/soc/rtc_common.h b/src/soc/mediatek/common/include/soc/rtc_common.h
old mode 100644
new mode 100755
index 5159f37..19dc3cd
--- a/src/soc/mediatek/common/include/soc/rtc_common.h
+++ b/src/soc/mediatek/common/include/soc/rtc_common.h
@@ -102,26 +102,4 @@
 int rtc_reg_init(void);
 void rtc_boot_common(void);
-static inline s32 rtc_read(u16 addr, u16 *rdata)
-{
-	s32 ret;
-
-	ret = pwrap_read(addr, rdata);
-	if (ret < 0)
-		rtc_info("pwrap_read fail: ret=%d\n", ret);
-
-	return ret;
-}
-
-static inline s32 rtc_write(u16 addr, u16 wdata)
-{
-	s32 ret;
-
-	ret = pwrap_write(addr, wdata);
-	if (ret < 0)
-		rtc_info("pwrap_write fail: ret=%d\n", ret);
-
-	return ret;
-}
-
 #endif /* SOC_MEDIATEK_RTC_COMMON_H */
diff --git a/src/soc/mediatek/common/rtc.c b/src/soc/mediatek/common/rtc.c
old mode 100644
new mode 100755
index 0925f7f..d0b90f7
--- a/src/soc/mediatek/common/rtc.c
+++ b/src/soc/mediatek/common/rtc.c
@@ -2,7 +2,7 @@
#include <soc/rtc_common.h>
 #include <soc/rtc.h>
-#include <soc/pmic_wrap.h>
+#include <soc/pmif.h>
 #include <timer.h>
/* ensure rtc write success */
@@ -164,8 +164,8 @@
switch (rtc_check_state()) {
    case RTC_STATE_REBOOT:
-		pwrap_write_field(RTC_BBPU, RTC_BBPU_KEY | RTC_BBPU_RELOAD,
-				  0xFFFF, 0);
+		rtc_read(RTC_BBPU, &bbpu);
+		rtc_write(RTC_BBPU, bbpu | RTC_BBPU_KEY | RTC_BBPU_RELOAD);
    	rtc_write_trigger();
    	rtc_osc_init();
    	break;
@@ -176,6 +176,7 @@
    default:
    	if (rtc_init(0))
    		rtc_init(1);
+		rtc_info("RTC_STATE_INIT\n");
    	break;
    }
diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc
old mode 100644
new mode 100755
index 5fc90a8..9542aa4
--- a/src/soc/mediatek/mt8192/Makefile.inc
+++ b/src/soc/mediatek/mt8192/Makefile.inc
@@ -11,6 +11,7 @@
 bootblock-y += ../common/uart.c
 bootblock-y += ../common/wdt.c
 bootblock-y += pmif.c pmif_clk.c pmif_spi.c pmif_spmi.c
+bootblock-y += ../common/rtc.c rtc.c
 bootblock-y += mt6315.c
 bootblock-y += mt6359p.c
diff --git a/src/soc/mediatek/mt8192/bootblock.c b/src/soc/mediatek/mt8192/bootblock.c
old mode 100644
new mode 100755
index 7987b1c..5bb85ba
--- a/src/soc/mediatek/mt8192/bootblock.c
+++ b/src/soc/mediatek/mt8192/bootblock.c
@@ -7,6 +7,7 @@
 #include <soc/pll.h>
 #include <soc/pmif.h>
 #include <soc/wdt.h>
+#include <soc/rtc.h>
void bootblock_soc_init(void)
 {
@@ -16,4 +17,5 @@
    mtk_pmif_init();
    mt6359p_init();
    mt6315_init();
+	rtc_boot();
 }
diff --git a/src/soc/mediatek/mt8192/include/soc/rtc.h b/src/soc/mediatek/mt8192/include/soc/rtc.h
new file mode 100755
index 0000000..b1be85c
--- /dev/null
+++ b/src/soc/mediatek/mt8192/include/soc/rtc.h
@@ -0,0 +1,220 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 MediaTek Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#ifndef SOC_MEDIATEK_MT8192_RTC_H
+#define SOC_MEDIATEK_MT8192_RTC_H
+
+#include <soc/rtc_common.h>
+
+/* RTC registers */
+enum {
+	RTC_BBPU = 0x0588,
+	RTC_IRQ_STA = 0x058A,
+	RTC_IRQ_EN = 0x058C,
+	RTC_CII_EN = 0x058E
+};
+
+enum {
+	RTC_TC_SEC = 0x0592,
+	RTC_TC_MIN = 0x0594,
+	RTC_TC_HOU = 0x0596,
+	RTC_TC_DOM = 0x0598,
+	RTC_TC_DOW = 0x059A,
+	RTC_TC_MTH = 0x059C,
+	RTC_TC_YEA = 0x059E
+};
+
+enum {
+	RTC_AL_SEC = 0x05A0,
+	RTC_AL_MIN = 0x05A2,
+	RTC_AL_HOU = 0x05A4,
+	RTC_AL_DOM = 0x05A6,
+	RTC_AL_DOW = 0x05A8,
+	RTC_AL_MTH = 0x05AA,
+	RTC_AL_YEA = 0x05AC,
+	RTC_AL_MASK = 0x0590
+};
+
+enum {
+	RTC_OSC32CON = 0x05AE,
+	RTC_CON = 0x05C4,
+	RTC_WRTGR = 0x05C2
+};
+
+enum {
+	RTC_POWERKEY1 = 0x05B0,
+	RTC_POWERKEY2 = 0x05B2
+};
+
+enum {
+	RTC_PDN1 = 0x05B4,
+	RTC_PDN2 = 0x05B6,
+	RTC_SPAR0 = 0x05B8,
+	RTC_SPAR1 = 0x05BA,
+	RTC_PROT = 0x05BC,
+	RTC_DIFF = 0x05BE,
+	RTC_CALI = 0x05C0
+};
+
+enum {
+	RTC_BBPU_ENABLE_ALARM	= 1U << 0,
+	RTC_BBPU_SPAR_SW	= 1U << 1,
+	RTC_BBPU_RESET_SPAR	= 1U << 2,
+	RTC_BBPU_RESET_ALARM	= 1U << 3,
+	RTC_BBPU_CLRPKY	= 1U << 4,
+	RTC_BBPU_RELOAD	= 1U << 5,
+	RTC_BBPU_CBUSY	= 1U << 6,
+	RTC_CBUSY_TIMEOUT_US = 1000000
+};
+
+enum {
+	RTC_CON_VBAT_LPSTA_RAW	= 1U << 0,
+	RTC_CON_EOSC32_LPEN	= 1U << 1,
+	RTC_CON_XOSC32_LPEN	= 1U << 2,
+	RTC_CON_LPRST		= 1U << 3,
+	RTC_CON_CDBO		= 1U << 4,
+	RTC_CON_F32KOB		= 1U << 5,
+	RTC_CON_GPO		= 1U << 6,
+	RTC_CON_GOE		= 1U << 7,
+	RTC_CON_GSR		= 1U << 8,
+	RTC_CON_GSMT		= 1U << 9,
+	RTC_CON_GPEN		= 1U << 10,
+	RTC_CON_GPU		= 1U << 11,
+	RTC_CON_GE4		= 1U << 12,
+	RTC_CON_GE8		= 1U << 13,
+	RTC_CON_GPI		= 1U << 14,
+	RTC_CON_LPSTA_RAW	= 1U << 15
+};
+
+enum {
+	RTC_XOSCCALI_MASK	= 0x1F << 0,
+	RTC_XOSC32_ENB		= 1U << 5,
+	RTC_EMB_HW_MODE		= 0U << 6,
+	RTC_EMB_K_EOSC32_MODE	= 1U << 6,
+	RTC_EMB_SW_DCXO_MODE	= 2U << 6,
+	RTC_EMB_SW_EOSC32_MODE	= 3U << 6,
+	RTC_EMBCK_SEL_MODE_MASK	= 3U << 6,
+	RTC_EMBCK_SRC_SEL	= 1U << 8,
+	RTC_EMBCK_SEL_OPTION	= 1U << 9,
+	RTC_GPS_CKOUT_EN	= 1U << 10,
+	RTC_REG_XOSC32_ENB	= 1U << 15
+};
+
+enum {
+	RTC_LPD_OPT_XOSC_AND_EOSC_LPD	= 0U << 13,
+	RTC_LPD_OPT_EOSC_LPD		= 1U << 13,
+	RTC_LPD_OPT_XOSC_LPD		= 2U << 13,
+	RTC_LPD_OPT_F32K_CK_ALIVE	= 3U << 13,
+	RTC_LPD_OPT_MASK		= 3U << 13
+};
+
+/* PMIC TOP Register Definition */
+enum {
+	PMIC_RG_SCK_TOP_CON0 = 0x050C
+};
+
+/* PMIC TOP Register Definition */
+enum {
+	PMIC_RG_TOP_CKPDN_CON0 = 0x010C,
+	PMIC_RG_TOP_CKPDN_CON0_SET = 0x010E,
+	PMIC_RG_TOP_CKPDN_CON0_CLR = 0x0110,
+	PMIC_RG_TOP_CKPDN_CON1 = 0x0112,
+	PMIC_RG_TOP_CKPDN_CON1_SET = 0x0114,
+	PMIC_RG_TOP_CKPDN_CON1_CLR = 0x0116,
+	PMIC_RG_TOP_CKSEL_CON0 = 0x0118,
+	PMIC_RG_TOP_CKSEL_CON0_SET = 0x011A,
+	PMIC_RG_TOP_CKSEL_CON0_CLR = 0x011C
+};
+
+enum {
+	PMIC_RG_FQMTR_32K_CK_PDN_SHIFT = 10,
+	PMIC_RG_FQMTR_CK_PDN_SHIFT = 11
+};
+
+/* PMIC DCXO Register Definition */
+enum {
+	PMIC_RG_DCXO_CW00 = 0x0788,
+	PMIC_RG_DCXO_CW00_SET = 0x078A,
+	PMIC_RG_DCXO_CW00_CLR = 0x078C,
+	PMIC_RG_DCXO_CW02 = 0x0790,
+	PMIC_RG_DCXO_CW08 = 0x079C,
+	PMIC_RG_DCXO_CW09 = 0x079E,
+	PMIC_RG_DCXO_CW09_SET = 0x07A0,
+	PMIC_RG_DCXO_CW09_CLR = 0x07A2,
+	PMIC_RG_DCXO_CW12 = 0x07A8
+};
+
+/* PMIC Frequency Meter Definition */
+enum {
+	PMIC_RG_FQMTR_CKSEL	= 0x0118,
+	PMIC_RG_FQMTR_RST	= 0x013A,
+	PMIC_RG_FQMTR_CON0	= 0x0546,
+	PMIC_RG_FQMTR_WINSET	= 0x0548,
+	PMIC_RG_FQMTR_DATA	= 0x054A,
+	FQMTR_TIMEOUT_US	= 8000
+};
+
+enum {
+	PMIC_FQMTR_FIX_CLK_26M		= 0U << 0,
+	PMIC_FQMTR_FIX_CLK_XOSC_32K_DET	= 1U << 0,
+	PMIC_FQMTR_FIX_CLK_EOSC_32K	= 2U << 0,
+	PMIC_FQMTR_FIX_CLK_RTC_32K	= 3U << 0,
+	PMIC_FQMTR_FIX_CLK_DCXO1M_CK	= 4U << 0,
+	PMIC_FQMTR_FIX_CLK_TCK_SEC	= 5U << 0,
+	PMIC_FQMTR_FIX_CLK_PMU_32K	= 6U << 0,
+	PMIC_FQMTR_CKSEL_MASK		= 7U << 0
+};
+
+enum {
+	PMIC_FQMTR_RST_SHIFT = 8
+};
+
+enum {
+	PMIC_FQMTR_CON0_XOSC32_CK	= 0U << 0,
+	PMIC_FQMTR_CON0_DCXO_F32K_CK	= 1U << 0,
+	PMIC_FQMTR_CON0_EOSC32_CK	= 2U << 0,
+	PMIC_FQMTR_CON0_XOSC32_CK_DETECTON = 3U << 0,
+	PMIC_FQMTR_CON0_FQM26M_CK	= 4U << 0,
+	PMIC_FQMTR_CON0_FQM32k_CK	= 5U << 0,
+	PMIC_FQMTR_CON0_TEST_CK		= 6U << 0,
+	PMIC_FQMTR_CON0_TCKSEL_MASK	= 7U << 0,
+	PMIC_FQMTR_CON0_BUSY		= 1U << 3,
+	PMIC_FQMTR_CON0_DCXO26M_EN	= 1U << 4,
+	PMIC_FQMTR_CON0_FQMTR_EN	= 1U << 15
+};
+
+enum {
+	RTC_FQMTR_LOW_BASE = 794 - 2,
+	RTC_FQMTR_HIGH_BASE = 794 + 2
+};
+
+enum {
+	RTC_XOSCCALI_START = 0x00,
+	RTC_XOSCCALI_END = 0x1f
+};
+
+enum {
+	RTC_TC_MTH_MASK = 0xf
+};
+
+int rtc_read(u16 addr, u16 *rdata);
+int rtc_write(u16 addr, u16 wdata);
+void rtc_write_field(u16 reg, u16 val, u16 mask, u16 shift);
+void rtc_bbpu_power_on(void);
+void rtc_osc_init(void);
+int rtc_init(u8 recover);
+void rtc_boot(void);
+void mt6359_dcxo_disable_unused(void);
+#endif /* SOC_MEDIATEK_MT8192_RTC_H */
+
diff --git a/src/soc/mediatek/mt8192/rtc.c b/src/soc/mediatek/mt8192/rtc.c
new file mode 100755
index 0000000..a8e28b5
--- /dev/null
+++ b/src/soc/mediatek/mt8192/rtc.c
@@ -0,0 +1,467 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 MediaTek Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#include <delay.h>
+#include <halt.h>
+#include <soc/mt6359p.h>
+#include <soc/pmif.h>
+#include <soc/rtc_common.h>
+#include <soc/rtc.h>
+#include <timer.h>
+
+#define RTC_GPIO_USER_MASK	  ((1 << 13) - (1 << 8))
+
+static struct pmif *pmif_arb = NULL;
+
+int rtc_read(u16 addr, u16 *rdata)
+{
+	if (pmif_arb == NULL)
+		pmif_arb = get_pmif_controller(PMIF_SPI, 0);
+	return pmif_arb->read_cmd(pmif_arb, 0, (unsigned int)addr, (unsigned int *)rdata);
+}
+
+int rtc_write(u16 addr, u16 wdata)
+{
+	if (pmif_arb == NULL)
+		pmif_arb = get_pmif_controller(PMIF_SPI, 0);
+	return pmif_arb->write_cmd(pmif_arb, 0, (unsigned int)addr, (unsigned int)wdata);
+}
+
+void rtc_write_field(u16 reg, u16 val, u16 mask, u16 shift)
+{
+	u16 old, new;
+
+	rtc_read(reg, &old);
+	new = old & ~(mask << shift);
+	new |= (val << shift);
+	rtc_write(reg, new);
+}
+
+/* initialize rtc setting of using dcxo clock */
+static int rtc_enable_dcxo(void)
+{
+	if (!rtc_writeif_unlock()) { /* Unlock for reload */
+		rtc_info("rtc_writeif_unlock() failed\n");
+		return 0;
+	}
+
+	u16 bbpu, con, osc32con, sec;
+
+	rtc_read(RTC_BBPU, &bbpu);
+	rtc_write(RTC_BBPU, bbpu | RTC_BBPU_KEY | RTC_BBPU_RELOAD);
+	rtc_write_trigger();
+	rtc_read(RTC_OSC32CON, &osc32con);
+	osc32con &= ~(RTC_EMBCK_SRC_SEL | RTC_EMBCK_SEL_MODE_MASK
+		      | RTC_GPS_CKOUT_EN);
+	osc32con |= RTC_XOSC32_ENB | RTC_REG_XOSC32_ENB
+		    | RTC_EMB_K_EOSC32_MODE | RTC_EMBCK_SEL_OPTION;
+
+	if (!rtc_xosc_write(osc32con)) {
+		rtc_info("rtc_xosc_write() failed\n");
+		return 0;
+	}
+
+	rtc_read(RTC_CON, &con);
+	rtc_read(RTC_OSC32CON, &osc32con);
+	rtc_read(RTC_AL_SEC, &sec);
+	rtc_info("con=0x%x, osc32con=0x%x, sec=0x%x\n", con, osc32con, sec);
+	return 1;
+}
+
+/* initialize rtc related gpio */
+static int rtc_gpio_init(void)
+{
+	u16 con;
+
+	/* GPI mode and pull down */
+	rtc_read(RTC_CON, &con);
+	con &= (RTC_CON_LPSTA_RAW | RTC_CON_LPRST | RTC_CON_EOSC32_LPEN
+		| RTC_CON_XOSC32_LPEN);
+	con |= (RTC_CON_GPEN | RTC_CON_GOE);
+	con &= ~(RTC_CON_F32KOB);
+	con &= ~RTC_CON_GPU;
+	rtc_write(RTC_CON, con);
+
+	return rtc_write_trigger();
+}
+
+static u16 rtc_get_frequency_meter(u16 val, u16 measure_src, u16 window_size)
+{
+	u16 bbpu, osc32con;
+	u16 fqmtr_busy, fqmtr_data, fqmtr_rst, fqmtr_tcksel;
+	struct stopwatch sw;
+
+	if (val) {
+		rtc_read(RTC_BBPU, &bbpu);
+		rtc_write(RTC_BBPU, bbpu | RTC_BBPU_KEY | RTC_BBPU_RELOAD);
+		rtc_write_trigger();
+		rtc_read(RTC_OSC32CON, &osc32con);
+		rtc_xosc_write((osc32con & ~RTC_XOSCCALI_MASK) |
+				(val & RTC_XOSCCALI_MASK));
+	}
+
+	/* enable FQMTR clock */
+	rtc_write_field(PMIC_RG_TOP_CKPDN_CON0_CLR, 1, 1,
+			  PMIC_RG_FQMTR_32K_CK_PDN_SHIFT);
+	rtc_write_field(PMIC_RG_TOP_CKPDN_CON0_CLR, 1, 1,
+			  PMIC_RG_FQMTR_CK_PDN_SHIFT);
+	/* FQMTR reset */
+	rtc_write_field(PMIC_RG_FQMTR_RST, 1, 1, PMIC_FQMTR_RST_SHIFT);
+
+	do {
+		rtc_read(PMIC_RG_FQMTR_DATA, &fqmtr_data);
+		rtc_read(PMIC_RG_FQMTR_CON0, &fqmtr_busy);
+	} while (fqmtr_data && (fqmtr_busy & PMIC_FQMTR_CON0_BUSY));
+
+	rtc_read(PMIC_RG_FQMTR_RST, &fqmtr_rst);
+	/* FQMTR normal */
+	rtc_write_field(PMIC_RG_FQMTR_RST, 0, 1, PMIC_FQMTR_RST_SHIFT);
+	/* set frequency meter window value (0=1X32K(fixed clock)) */
+	rtc_write(PMIC_RG_FQMTR_WINSET, window_size);
+	/* enable 26M and set test clock source */
+	rtc_write(PMIC_RG_FQMTR_CON0, PMIC_FQMTR_CON0_DCXO26M_EN | measure_src);
+	/* enable 26M -> delay 100us -> enable FQMTR */
+	udelay(100);
+	rtc_read(PMIC_RG_FQMTR_CON0, &fqmtr_tcksel);
+	/* enable FQMTR */
+	rtc_write(PMIC_RG_FQMTR_CON0, fqmtr_tcksel | PMIC_FQMTR_CON0_FQMTR_EN);
+	udelay(100);
+	stopwatch_init_usecs_expire(&sw, FQMTR_TIMEOUT_US);
+	/* FQMTR read until ready */
+	do {
+		rtc_read(PMIC_RG_FQMTR_CON0, &fqmtr_busy);
+		if (stopwatch_expired(&sw)) {
+			rtc_info("get frequency time out !!\n");
+			return 0;
+		}
+	} while (fqmtr_busy & PMIC_FQMTR_CON0_BUSY);
+
+	/* read data should be closed to 26M/32k = 794 */
+	rtc_read(PMIC_RG_FQMTR_DATA, &fqmtr_data);
+	rtc_read(PMIC_RG_FQMTR_CON0, &fqmtr_tcksel);
+	/* disable FQMTR */
+	rtc_write(PMIC_RG_FQMTR_CON0, fqmtr_tcksel & ~PMIC_FQMTR_CON0_FQMTR_EN);
+	/* disable FQMTR -> delay 100us -> disable 26M */
+	udelay(100);
+	/* disable 26M */
+	rtc_read(PMIC_RG_FQMTR_CON0, &fqmtr_tcksel);
+	rtc_write(PMIC_RG_FQMTR_CON0,
+		  fqmtr_tcksel & ~PMIC_FQMTR_CON0_DCXO26M_EN);
+	rtc_info("input=0x%x, output=%d\n", val, fqmtr_data);
+	/* disable FQMTR clock */
+	rtc_write_field(PMIC_RG_TOP_CKPDN_CON0_SET, 1, 1,
+			  PMIC_RG_FQMTR_32K_CK_PDN_SHIFT);
+	rtc_write_field(PMIC_RG_TOP_CKPDN_CON0_SET, 1, 1,
+			  PMIC_RG_FQMTR_CK_PDN_SHIFT);
+	return fqmtr_data;
+}
+
+/* 32k clock calibration */
+static u16 rtc_eosc_cali(void)
+{
+	u16 middle, diff1, diff2, cksel;
+	u16 val = 0;
+	u16 left = RTC_XOSCCALI_START, right = RTC_XOSCCALI_END;
+
+	rtc_read(PMIC_RG_FQMTR_CKSEL, &cksel);
+	cksel &= ~PMIC_FQMTR_CKSEL_MASK;
+	/* select EOSC_32 as fixed clock */
+	rtc_write(PMIC_RG_FQMTR_CKSEL, cksel | PMIC_FQMTR_FIX_CLK_EOSC_32K);
+	rtc_read(PMIC_RG_FQMTR_CKSEL, &cksel);
+	rtc_info("PMIC_RG_FQMTR_CKSEL=0x%x\n", cksel);
+
+	while (left <= right) {
+		middle = (right + left) / 2;
+		if (middle == left)
+			break;
+		/* select 26M as target clock */
+		val = rtc_get_frequency_meter(middle, PMIC_FQMTR_CON0_FQM26M_CK, 0);
+		if (val >= RTC_FQMTR_LOW_BASE && val <= RTC_FQMTR_HIGH_BASE)
+			break;
+		if (val > RTC_FQMTR_HIGH_BASE)
+			right = middle;
+		else
+			left = middle;
+	}
+
+	if (val >= RTC_FQMTR_LOW_BASE && val <= RTC_FQMTR_HIGH_BASE)
+		return middle;
+
+	val = rtc_get_frequency_meter(left, PMIC_FQMTR_CON0_FQM26M_CK, 0);
+
+	if (val > RTC_FQMTR_LOW_BASE)
+		diff1 = val - RTC_FQMTR_LOW_BASE;
+	else
+		diff1 = RTC_FQMTR_LOW_BASE - val;
+
+	val = rtc_get_frequency_meter(right, PMIC_FQMTR_CON0_FQM26M_CK, 0);
+
+	if (val > RTC_FQMTR_LOW_BASE)
+		diff2 = val - RTC_FQMTR_LOW_BASE;
+	else
+		diff2 = RTC_FQMTR_LOW_BASE - val;
+
+	if (diff1 < diff2)
+		return left;
+	else
+		return right;
+}
+
+void rtc_osc_init(void)
+{
+	u16 osc32con;
+
+	/* enable 32K export */
+	rtc_gpio_init();
+	/* Calibrate eosc32 for powerdown clock */
+	rtc_read(RTC_OSC32CON, &osc32con);
+	rtc_info("osc32con val = 0x%x\n", osc32con);
+	osc32con &= ~RTC_XOSCCALI_MASK;
+	osc32con |= rtc_eosc_cali() & RTC_XOSCCALI_MASK;
+	rtc_xosc_write(osc32con);
+	rtc_info("EOSC32 cali val = 0x%x\n", osc32con);
+}
+
+/* enable lpd subroutine */
+static int rtc_lpen(u16 con)
+{
+	con &= ~RTC_CON_LPRST;
+	rtc_write(RTC_CON, con);
+
+	if (!rtc_write_trigger())
+		return 0;
+
+	con |= RTC_CON_LPRST;
+	rtc_write(RTC_CON, con);
+
+	if (!rtc_write_trigger())
+		return 0;
+
+	con &= ~RTC_CON_LPRST;
+	rtc_write(RTC_CON, con);
+
+	if (!rtc_write_trigger())
+		return 0;
+
+	return 1;
+}
+
+/* low power detect setting */
+static int rtc_lpd_init(void)
+{
+	u16 con, sec;
+
+	/* disable both XOSC & EOSC LPD */
+	rtc_read(RTC_AL_SEC, &sec);
+	sec |= RTC_LPD_OPT_F32K_CK_ALIVE;
+	rtc_write(RTC_AL_SEC, sec);
+
+	if (!rtc_write_trigger())
+		return 0;
+
+	/* init XOSC32 to detect 32k clock stop */
+	rtc_read(RTC_CON, &con);
+	con |= RTC_CON_XOSC32_LPEN;
+
+	if (!rtc_lpen(con))
+		return 0;
+
+	/* init EOSC32 to detect rtc low power */
+	rtc_read(RTC_CON, &con);
+	con |= RTC_CON_EOSC32_LPEN;
+
+	if (!rtc_lpen(con))
+		return 0;
+
+	rtc_read(RTC_CON, &con);
+	con &= ~RTC_CON_XOSC32_LPEN;
+	rtc_write(RTC_CON, con);
+	/*Enable RTC_LPD_OPT: EOSC LPD*/
+	rtc_read(RTC_AL_SEC, &sec);
+	sec &= ~RTC_LPD_OPT_MASK;
+	sec |= RTC_LPD_OPT_EOSC_LPD;
+	rtc_write(RTC_AL_SEC, sec);
+
+	if (!rtc_write_trigger())
+		return 0;
+
+	return 1;
+}
+
+static bool rtc_hw_init(void)
+{
+	u16 bbpu;
+
+	rtc_read(RTC_BBPU, &bbpu);
+	rtc_write(RTC_BBPU, (bbpu | RTC_BBPU_KEY | RTC_BBPU_RESET_ALARM | RTC_BBPU_RESET_SPAR) & (~RTC_BBPU_SPAR_SW));
+	rtc_write_trigger();
+	udelay(500);
+
+	rtc_read(RTC_BBPU, &bbpu);
+	rtc_write(RTC_BBPU, bbpu | RTC_BBPU_KEY | RTC_BBPU_RELOAD);
+	rtc_write_trigger();
+	rtc_read(RTC_BBPU, &bbpu);
+
+	if (bbpu & RTC_BBPU_RESET_ALARM || bbpu & RTC_BBPU_RESET_SPAR) {
+		rtc_info("timeout\n");
+		return false;
+	}
+	return true;
+}
+
+/* write powerkeys to enable rtc functions */
+static int rtc_powerkey_init(void)
+{
+	rtc_write(RTC_POWERKEY1, RTC_POWERKEY1_KEY);
+	rtc_write(RTC_POWERKEY2, RTC_POWERKEY2_KEY);
+	return rtc_write_trigger();
+}
+
+/* rtc init check */
+int rtc_init(u8 recover)
+{
+	int ret;
+
+	rtc_info("recovery: %d\n", recover);
+
+	/* write powerkeys to enable rtc functions */
+	if (!rtc_powerkey_init()) {
+		ret = -RTC_STATUS_POWERKEY_INIT_FAIL;
+		goto err;
+	}
+
+	/* write interface unlock need to be set after powerkey match */
+	if (!rtc_writeif_unlock()) {
+		ret = -RTC_STATUS_WRITEIF_UNLOCK_FAIL;
+		goto err;
+	}
+
+	//rtc_osc_init();
+
+	if (recover)
+		mdelay(20);
+
+	if (!rtc_gpio_init()) {
+		ret = -RTC_STATUS_GPIO_INIT_FAIL;
+		goto err;
+	}
+
+	if (!rtc_hw_init()) {
+		ret = -RTC_STATUS_HW_INIT_FAIL;
+		goto err;
+	}
+
+	if (!rtc_reg_init()) {
+		ret = -RTC_STATUS_REG_INIT_FAIL;
+		goto err;
+	}
+
+	if (!rtc_lpd_init()) {
+		ret = -RTC_STATUS_LPD_INIT_FAIL;
+		goto err;
+	}
+	/* After lpd init, powerkeys need to be written again to enable
+	 * low power detect function.
+	 */
+	if (!rtc_powerkey_init()) {
+		ret = -RTC_STATUS_POWERKEY_INIT_FAIL;
+		goto err;
+	}
+	return RTC_STATUS_OK;
+err:
+	rtc_info("init fail: ret=%d\n", ret);
+	return ret;
+}
+
+/* enable rtc bbpu */
+void rtc_bbpu_power_on(void)
+{
+	u16 bbpu;
+	int ret;
+
+	/* pull powerhold high, control by pmic */
+	rtc_write_field(PMIC_PWRHOLD, 1, 0x1, 0);
+	bbpu = RTC_BBPU_KEY | RTC_BBPU_ENABLE_ALARM;
+	rtc_write(RTC_BBPU, bbpu);
+	ret = rtc_write_trigger();
+	rtc_info("rtc_write_trigger=%d\n", ret);
+	rtc_read(RTC_BBPU, &bbpu);
+	rtc_info("done BBPU=%#x\n", bbpu);
+}
+
+void poweroff(void)
+{
+	u16 bbpu;
+
+	if (!rtc_writeif_unlock())
+		rtc_info("rtc_writeif_unlock() failed\n");
+	/* pull PWRBB low */
+	bbpu = RTC_BBPU_KEY | RTC_BBPU_ENABLE_ALARM;
+	rtc_write(RTC_BBPU, bbpu);
+	rtc_write_field(PMIC_PWRHOLD, 0, 0x1, 0);
+	halt();
+}
+
+static void dcxo_init(void)
+{
+	u16 tmp;
+
+	rtc_read(PMIC_RG_DCXO_CW00, &tmp);
+	rtc_info("CW00,0x%x:0x%x\n", PMIC_RG_DCXO_CW00, tmp);
+	rtc_read(PMIC_RG_DCXO_CW09, &tmp);
+	rtc_info("CW09,0x%x:0x%x\n", PMIC_RG_DCXO_CW09, tmp);
+	rtc_read(PMIC_RG_DCXO_CW08, &tmp);
+	rtc_info("CW08,0x%x:0x%x\n", PMIC_RG_DCXO_CW08, tmp);
+	/* 26M enable control */
+	/* Enable clock buffer XO_SOC */
+	rtc_write_field(PMIC_RG_DCXO_CW00, 0x4005, 0xFFFF, 0);
+	rtc_read(PMIC_RG_DCXO_CW00, &tmp);
+	rtc_info("CW0,0x%x:0x%x\n", PMIC_RG_DCXO_CW00, tmp);
+	rtc_write_field(PMIC_RG_DCXO_CW09_CLR, 0x3f, 0x3f, 9);
+	rtc_read(PMIC_RG_DCXO_CW09, &tmp);
+	rtc_info("PMIC_RG_DCXO_CW09,0x%x:0x%x\n", PMIC_RG_DCXO_CW09, tmp);
+	/* Mode and buffer controlled by srclken0 */
+	rtc_write_field(PMIC_RG_DCXO_CW08, 0x1, 0x1, 2);
+	rtc_read(PMIC_RG_DCXO_CW08, &tmp);
+	rtc_info("PMIC_RG_DCXO_CW08,0x%x:0x%x\n", PMIC_RG_DCXO_CW08, tmp);
+}
+
+void mt6359_dcxo_disable_unused(void)
+{
+	/* Disable HW BBLPM arbiter */
+	//rtc_write_field(PMIC_RG_DCXO_CW12, 0x0, 0x1, 0);
+	rtc_write_field(PMIC_RG_DCXO_CW12, 0x2, 0x3, 0);
+}
+
+/* the rtc boot flow entry */
+void rtc_boot(void)
+{
+	u16 tmp;
+
+	/* dcxo clock init settings */
+	dcxo_init();
+	/* dcxo 32k init settings */
+	rtc_write_field(PMIC_RG_DCXO_CW02, 0xF, 0xF, 0);
+	rtc_read(PMIC_RG_SCK_TOP_CON0, &tmp);
+	rtc_info("PMIC_RG_SCK_TOP_CON0,0x%x:0x%x\n", PMIC_RG_SCK_TOP_CON0, tmp);
+	rtc_write_field(PMIC_RG_SCK_TOP_CON0, 0x1, 0x1, 0);
+	rtc_read(PMIC_RG_SCK_TOP_CON0, &tmp);
+	rtc_info("PMIC_RG_SCK_TOP_CON0,0x%x:0x%x\n", PMIC_RG_SCK_TOP_CON0, tmp);
+	/* use dcxo 32K clock */
+	if (!rtc_enable_dcxo())
+		rtc_info("rtc_enable_dcxo() failed\n");
+	rtc_boot_common();
+	rtc_bbpu_power_on();
+}
+
-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I57d6738fdec148c7458b2024a0a8225415ca2f3e
Gerrit-Change-Number: 46395
Gerrit-PatchSet: 1
Gerrit-Owner: Yidi Lin yidi.lin@mediatek.com
Gerrit-Reviewer: Martin Roth martinroth@google.com
Gerrit-Reviewer: Patrick Georgi pgeorgi@google.com
Gerrit-MessageType: newchange



    