EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49007 )
Change subject: mb/google/brya: Initiate peripheral buses ......................................................................
mb/google/brya: Initiate peripheral buses
Initiate peripheral buses based on latest schematic.
BUG=b:174266035 TEST=Build Test
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: Ibf48aceca7ac8774b0353e31bd81e1880c4066ea --- M src/mainboard/google/brya/variants/baseboard/devicetree.cb 1 file changed, 107 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/49007/1
diff --git a/src/mainboard/google/brya/variants/baseboard/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/devicetree.cb index 479a7ee..96e0a9d 100644 --- a/src/mainboard/google/brya/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/devicetree.cb @@ -3,6 +3,113 @@ device lapic 0 on end end
+ register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" # USB2_C0 + register "usb2_ports[1]" = "USB2_PORT_MID(OC1)" # USB2_C1 + register "usb2_ports[2]" = "USB2_PORT_MID(OC2)" # USB2_C2 + register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WWAN + register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Camera + register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A0 + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Bluetooth + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC3)" # USB3/2 Type A port A0 + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 WWAN + + # Enable WLAN PCIE 5 using clk 2 + register "pch_pcie_rp[PCH_RP(5)]" = "{ + .clk_src = 2, + .clk_req = 2, + .flags = PCIE_RP_ENABLED, + }" + + # Enable WWAN PCIE 6 using clk 5 + register "pch_pcie_rp[PCH_RP(6)]" = "{ + .clk_src = 5, + .clk_req = 5, + .flags = PCIE_RP_ENABLED, + }" + + # Enable SD Card PCIE 8 using clk 3 + register "pch_pcie_rp[PCH_RP(8)]" = "{ + .clk_src = 3, + .clk_req = 3, + .flags = PCIE_RP_ENABLED | PCIE_RP_HOTPLUG_ENABLED | PCIE_RP_LTR_ENABLED, + }" + + # Enable NVMe PCIE 9 using clk 1 + register "pch_pcie_rp[PCH_RP(9)]" = "{ + .clk_src = 1, + .clk_req = 1, + .flags = PCIE_RP_ENABLED | PCIE_RP_LTR_ENABLED, + }" + + register "SerialIoI2cMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoPci, + [PchSerialIoIndexI2C5] = PchSerialIoPci, + }" + + register "SerialIoGSpiMode" = "{ + [PchSerialIoIndexGSPI0] = PchSerialIoDisabled, + [PchSerialIoIndexGSPI1] = PchSerialIoPci, + }" + + register "SerialIoGSpiCsMode" = "{ + [PchSerialIoIndexGSPI0] = 0, + [PchSerialIoIndexGSPI1] = 1, + }" + + register "SerialIoGSpiCsState" = "{ + [PchSerialIoIndexGSPI0] = 0, + [PchSerialIoIndexGSPI1] = 1, + }" + + register "SerialIoUartMode" = "{ + [PchSerialIoIndexUART0] = PchSerialIoPci, + [PchSerialIoIndexUART1] = PchSerialIoDisabled, + [PchSerialIoIndexUART2] = PchSerialIoDisabled, + }" + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | + #| GSPI1 | Fingerprint MCU | + #| I2C0 | Audio | + #| I2C1 | Touchscreen | + #| I2C2 | SAR0 | + #| I2C3 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| I2C4 | CAM | + #| I2C5 | Trackpad | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[3] = { + .early_init = 1, + .speed = I2C_SPEED_FAST, + }, + .i2c[4] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + }, + }" + device domain 0 on device ref igpu on end device ref dtt on end @@ -30,7 +137,6 @@ device ref pcie_rp8 on end #PCIE8 SD card device ref pcie_rp9 on end #PCIE9-12 SSD device ref uart0 on end - device ref gspi0 on end device ref gspi1 on end device ref pch_espi on chip ec/google/chromeec
EricR Lai has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/49007 )
Change subject: mb/google/brya: Initiate peripheral buses ......................................................................
mb/google/brya: Initiate peripheral buses
Initiate peripheral buses based on latest schematic.
BUG=b:174266035 TEST=Build Test
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: Ibf48aceca7ac8774b0353e31bd81e1880c4066ea --- M src/mainboard/google/brya/variants/baseboard/devicetree.cb 1 file changed, 105 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/49007/2
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/49007
to look at the new patch set (#3).
Change subject: mb/google/brya: Initiate peripheral buses ......................................................................
mb/google/brya: Initiate peripheral buses
Initiate peripheral buses based on latest schematic. Reland CB:48295
BUG=b:174266035 TEST=Build Test
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: Ibf48aceca7ac8774b0353e31bd81e1880c4066ea --- M src/mainboard/google/brya/variants/baseboard/devicetree.cb 1 file changed, 105 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/49007/3
Attention is currently required from: EricR Lai. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49007 )
Change subject: mb/google/brya: Initiate peripheral buses ......................................................................
Patch Set 3: Code-Review+2
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49007 )
Change subject: mb/google/brya: Initiate peripheral buses ......................................................................
Patch Set 3: Code-Review-1
(1 comment)
Patchset:
PS3: Set -1 to block the cherry-pick by accident..
Hello build bot (Jenkins), Tim Wawrzynczak,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#4).
Change subject: mb/google/brya: Initiate peripheral buses ......................................................................
mb/google/brya: Initiate peripheral buses
Initiate peripheral buses based on latest schematic. Reland CB:48295
BUG=b:174266035 TEST=Build Test
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: Ibf48aceca7ac8774b0353e31bd81e1880c4066ea --- M src/mainboard/google/brya/variants/baseboard/devicetree.cb 1 file changed, 105 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/49007/4
Attention is currently required from: EricR Lai. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49007 )
Change subject: mb/google/brya: Initiate peripheral buses ......................................................................
Patch Set 4: Code-Review+2
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I'd like you to reexamine a change. Please visit
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to look at the new patch set (#15).
Change subject: mb/google/brya: Initiate peripheral buses ......................................................................
mb/google/brya: Initiate peripheral buses
Initiate peripheral buses based on latest schematic. Reland CB:48295
BUG=b:174266035 TEST=Build Test
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: Ibf48aceca7ac8774b0353e31bd81e1880c4066ea --- M src/mainboard/google/brya/variants/baseboard/devicetree.cb 1 file changed, 109 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/49007/15
Attention is currently required from: Furquan Shaikh. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49007 )
Change subject: mb/google/brya: Initiate peripheral buses ......................................................................
Patch Set 15:
(1 comment)
Patchset:
PS15: @Furquan, Is this what we talk about? move the RP config under pci device node?
Attention is currently required from: Furquan Shaikh, EricR Lai. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49007 )
Change subject: mb/google/brya: Initiate peripheral buses ......................................................................
Patch Set 15: Code-Review+2
(1 comment)
Patchset:
PS15:
@Furquan, Is this what we talk about? move the RP config under pci device node?
yes, because there is no chip in between, the registers still go with the SoC chip
Attention is currently required from: EricR Lai. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49007 )
Change subject: mb/google/brya: Initiate peripheral buses ......................................................................
Patch Set 15:
(6 comments)
Patchset:
PS15:
yes, because there is no chip in between, the registers still go with the SoC chip
Yes!
File src/mainboard/google/brya/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/49007/comment/e44787ec_e7b2a81c PS15, Line 32: [PchSerialIoIndexGSPI0] = 0, Don't really need to set this as GSP0 is disabled. Same for CS state below.
https://review.coreboot.org/c/coreboot/+/49007/comment/84a6a313_3d697353 PS15, Line 33: [PchSerialIoIndexGSPI1] = 1, Do we need to initialize GSPI for FPMCU? Wouldn't this be done by the OS?
https://review.coreboot.org/c/coreboot/+/49007/comment/7090cc4a_6f3c2bae PS15, Line 105: #USB3-1 Type A This comment doesn't really look right. Why does a PCIE RP device say USB3? Same for RP4 below.
https://review.coreboot.org/c/coreboot/+/49007/comment/04a2aef0_776fb706 PS15, Line 110: one additional tab here and on next line.
https://review.coreboot.org/c/coreboot/+/49007/comment/3a735977_fa08561e PS15, Line 134: PCIE_RP_LTR Why is LTR not enabled for WLAN and WWAN ports? Also, what about AER?
Attention is currently required from: Furquan Shaikh. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49007 )
Change subject: mb/google/brya: Initiate peripheral buses ......................................................................
Patch Set 15:
(3 comments)
File src/mainboard/google/brya/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/49007/comment/05d0c9f4_918bf787 PS15, Line 33: [PchSerialIoIndexGSPI1] = 1,
Do we need to initialize GSPI for FPMCU? Wouldn't this be done by the OS?
Not sure here.
https://review.coreboot.org/c/coreboot/+/49007/comment/59f82fdd_d50a0027 PS15, Line 105: #USB3-1 Type A
This comment doesn't really look right. Why does a PCIE RP device say USB3? Same for RP4 below.
Do we need to enable RP port if this is combo PCIE and USB?
https://review.coreboot.org/c/coreboot/+/49007/comment/5b0c1c5d_b222bb1c PS15, Line 134: PCIE_RP_LTR
Why is LTR not enabled for WLAN and WWAN ports? Also, what about AER?
Previous project not enabled for it. LTR may cause device lose when suspend/resume. Do we need AER, I think it okay to have it?
Attention is currently required from: EricR Lai. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49007 )
Change subject: mb/google/brya: Initiate peripheral buses ......................................................................
Patch Set 15:
(2 comments)
File src/mainboard/google/brya/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/49007/comment/a65dd8f8_e7e704cc PS15, Line 105: #USB3-1 Type A
Do we need to enable RP port if this is combo PCIE and USB?
No, the lanes would be owned by the USB controller and hence the PCIe RP should be kept off.
https://review.coreboot.org/c/coreboot/+/49007/comment/90babb7e_475981b5 PS15, Line 134: PCIE_RP_LTR
Previous project not enabled for it. LTR may cause device lose when suspend/resume. […]
I don't think that's correct. LTR is important for ensuring the PCIe links can enter their low power state. I think we should keep it enabled for all ports.
I think we should enable AER. It is helpful in identifying link errors.
Attention is currently required from: Furquan Shaikh. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49007 )
Change subject: mb/google/brya: Initiate peripheral buses ......................................................................
Patch Set 15:
(7 comments)
File src/mainboard/google/brya/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/49007/comment/76402d33_5948e029 PS15, Line 32: [PchSerialIoIndexGSPI0] = 0,
Don't really need to set this as GSP0 is disabled. Same for CS state below.
Done
https://review.coreboot.org/c/coreboot/+/49007/comment/8f395ba6_b49ffa09 PS15, Line 33: [PchSerialIoIndexGSPI1] = 1,
Not sure here.
volteer enable this so keep this. We can remove this after?
https://review.coreboot.org/c/coreboot/+/49007/comment/22769976_52c7be8e PS15, Line 105: #USB3-1 Type A
No, the lanes would be owned by the USB controller and hence the PCIe RP should be kept off.
Done
https://review.coreboot.org/c/coreboot/+/49007/comment/fc73b5cf_ab28ee33 PS15, Line 105: #USB3-1 Type A
No, the lanes would be owned by the USB controller and hence the PCIe RP should be kept off.
Done
https://review.coreboot.org/c/coreboot/+/49007/comment/50e11e2e_6c8efa05 PS15, Line 110:
one additional tab here and on next line.
Done
https://review.coreboot.org/c/coreboot/+/49007/comment/460b240f_fa705f8d PS15, Line 134: PCIE_RP_LTR
I don't think that's correct. […]
Done
https://review.coreboot.org/c/coreboot/+/49007/comment/fd5b5be3_451ca99e PS15, Line 134: PCIE_RP_LTR
I don't think that's correct. […]
Done
Attention is currently required from: Furquan Shaikh. Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#16).
Change subject: mb/google/brya: Initiate peripheral buses ......................................................................
mb/google/brya: Initiate peripheral buses
Initiate peripheral buses based on latest schematic. Reland CB:48295
BUG=b:174266035 TEST=Build Test
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: Ibf48aceca7ac8774b0353e31bd81e1880c4066ea --- M src/mainboard/google/brya/variants/baseboard/devicetree.cb 1 file changed, 109 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/49007/16
Attention is currently required from: Furquan Shaikh, EricR Lai. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49007 )
Change subject: mb/google/brya: Initiate peripheral buses ......................................................................
Patch Set 17: Code-Review+1
(3 comments)
File src/mainboard/google/brya/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/49007/comment/261af03b_6e7918e8 PS17, Line 6: USB2_PORT_MID USB2_PORT_TYPE_C
https://review.coreboot.org/c/coreboot/+/49007/comment/46641e6e_a3709f34 PS17, Line 7: USB2_PORT_MID USB2_PORT_TYPE_C
https://review.coreboot.org/c/coreboot/+/49007/comment/c9dd7d79_56a7a3fd PS17, Line 8: USB2_PORT_MID USB2_PORT_TYPE_C
Attention is currently required from: EricR Lai. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49007 )
Change subject: mb/google/brya: Initiate peripheral buses ......................................................................
Patch Set 17:
(1 comment)
File src/mainboard/google/brya/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/49007/comment/f2335c87_006da3ae PS15, Line 33: [PchSerialIoIndexGSPI1] = 1,
volteer enable this so keep this. […]
Sure. Can you please raise a bug so that we don't forget?
Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49007 )
Change subject: mb/google/brya: Initiate peripheral buses ......................................................................
Patch Set 17:
(4 comments)
File src/mainboard/google/brya/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/49007/comment/921e724c_1a82168a PS15, Line 33: [PchSerialIoIndexGSPI1] = 1,
Sure. […]
b:177928256 for tracking this. But who is the owner?
File src/mainboard/google/brya/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/49007/comment/8ccfad95_df820b26 PS17, Line 6: USB2_PORT_MID
USB2_PORT_TYPE_C
Done
https://review.coreboot.org/c/coreboot/+/49007/comment/d53f31e6_b7f4cbba PS17, Line 7: USB2_PORT_MID
USB2_PORT_TYPE_C
Done
https://review.coreboot.org/c/coreboot/+/49007/comment/87993540_046113cd PS17, Line 8: USB2_PORT_MID
USB2_PORT_TYPE_C
Done
Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak. Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#18).
Change subject: mb/google/brya: Initiate peripheral buses ......................................................................
mb/google/brya: Initiate peripheral buses
Initiate peripheral buses based on latest schematic. Reland CB:48295
BUG=b:174266035 TEST=Build Test
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: Ibf48aceca7ac8774b0353e31bd81e1880c4066ea --- M 3rdparty/blobs M src/mainboard/google/brya/variants/baseboard/devicetree.cb 2 files changed, 110 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/49007/18
Attention is currently required from: Tim Wawrzynczak, EricR Lai. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49007 )
Change subject: mb/google/brya: Initiate peripheral buses ......................................................................
Patch Set 18:
(1 comment)
File src/mainboard/google/brya/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/49007/comment/3894bed2_4bd20b32 PS15, Line 33: [PchSerialIoIndexGSPI1] = 1,
b:177928256 for tracking this. […]
Either you or Tim ;).
Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49007 )
Change subject: mb/google/brya: Initiate peripheral buses ......................................................................
Patch Set 18:
(1 comment)
File src/mainboard/google/brya/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/49007/comment/345e2407_a87cc6ba PS15, Line 33: [PchSerialIoIndexGSPI1] = 1,
Either you or Tim ;).
Do we have feature use the FP to wake system and login quickly like Mac? Not sure google's plan on FP usage and scenario.
Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak. Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#19).
Change subject: mb/google/brya: Initiate peripheral buses ......................................................................
mb/google/brya: Initiate peripheral buses
Initiate peripheral buses based on latest schematic.
BUG=b:174266035 TEST=Build Test
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: Ibf48aceca7ac8774b0353e31bd81e1880c4066ea --- M 3rdparty/blobs M src/mainboard/google/brya/variants/baseboard/devicetree.cb 2 files changed, 110 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/49007/19
Attention is currently required from: Furquan Shaikh, EricR Lai. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49007 )
Change subject: mb/google/brya: Initiate peripheral buses ......................................................................
Patch Set 19:
(2 comments)
File 3rdparty/blobs:
PS19: you may need to run `git submodule update --force --checkout` first 😉
File src/mainboard/google/brya/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/49007/comment/cbba0e7c_20655579 PS15, Line 33: [PchSerialIoIndexGSPI1] = 1,
Do we have feature use the FP to wake system and login quickly like Mac? Not sure google's plan on F […]
I think on current devices it (fingerprint) can only be used to log you in after you are logged into a session where you already used your password ? I don't know of any upcoming policy changes
Attention is currently required from: Tim Wawrzynczak, EricR Lai. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49007 )
Change subject: mb/google/brya: Initiate peripheral buses ......................................................................
Patch Set 19:
(1 comment)
File src/mainboard/google/brya/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/49007/comment/e41ebb0b_74062375 PS15, Line 33: [PchSerialIoIndexGSPI1] = 1,
I think on current devices it (fingerprint) can only be used to log you in after you are logged into […]
FP is a wake source, but not from deep sleep states (S5/G3). coreboot is not involved on S0ix path, so this shouldn't be a problem.
Attention is currently required from: Tim Wawrzynczak, EricR Lai. Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/49007
to look at the new patch set (#20).
Change subject: mb/google/brya: Initiate peripheral buses ......................................................................
mb/google/brya: Initiate peripheral buses
Initiate peripheral buses based on latest schematic.
BUG=b:174266035 TEST=Build Test
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: Ibf48aceca7ac8774b0353e31bd81e1880c4066ea --- M src/mainboard/google/brya/variants/baseboard/devicetree.cb 1 file changed, 101 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/49007/20
Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49007 )
Change subject: mb/google/brya: Initiate peripheral buses ......................................................................
Patch Set 20:
(2 comments)
File 3rdparty/blobs:
PS19:
you may need to run `git submodule update --force --checkout` first 😉
Done
File src/mainboard/google/brya/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/49007/comment/6ebca98b_cddf2c10 PS15, Line 33: [PchSerialIoIndexGSPI1] = 1,
FP is a wake source, but not from deep sleep states (S5/G3). […]
Make sense. Removed this.
Attention is currently required from: Furquan Shaikh, EricR Lai. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49007 )
Change subject: mb/google/brya: Initiate peripheral buses ......................................................................
Patch Set 20: Code-Review+2
Attention is currently required from: Furquan Shaikh, EricR Lai. Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/49007
to look at the new patch set (#22).
Change subject: mb/google/brya: Initiate peripheral buses ......................................................................
mb/google/brya: Initiate peripheral buses
Initiate peripheral buses based on latest schematic.
BUG=b:174266035 TEST=Build Test
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: Ibf48aceca7ac8774b0353e31bd81e1880c4066ea --- M 3rdparty/blobs M 3rdparty/intel-microcode M src/mainboard/google/brya/variants/baseboard/devicetree.cb 3 files changed, 100 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/49007/22
Attention is currently required from: Furquan Shaikh, EricR Lai. Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/49007
to look at the new patch set (#23).
Change subject: mb/google/brya: Initiate peripheral buses ......................................................................
mb/google/brya: Initiate peripheral buses
Initiate peripheral buses based on latest schematic.
BUG=b:174266035 TEST=Build Test
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: Ibf48aceca7ac8774b0353e31bd81e1880c4066ea --- M src/mainboard/google/brya/variants/baseboard/devicetree.cb 1 file changed, 98 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/49007/23
Attention is currently required from: Furquan Shaikh. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49007 )
Change subject: mb/google/brya: Initiate peripheral buses ......................................................................
Patch Set 23:
(1 comment)
Patchset:
PS23: @Tim, I change back. Let's move and not block by the adlrvp. And I can refactor after Intel debug the another CL.
Attention is currently required from: Furquan Shaikh, EricR Lai. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49007 )
Change subject: mb/google/brya: Initiate peripheral buses ......................................................................
Patch Set 23: Code-Review+2
(1 comment)
Patchset:
PS23:
@Tim, I change back. Let's move and not block by the adlrvp. […]
Thanks Eric, sounds like a plan.
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/49007 )
Change subject: mb/google/brya: Initiate peripheral buses ......................................................................
mb/google/brya: Initiate peripheral buses
Initiate peripheral buses based on latest schematic.
BUG=b:174266035 TEST=Build Test
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: Ibf48aceca7ac8774b0353e31bd81e1880c4066ea Reviewed-on: https://review.coreboot.org/c/coreboot/+/49007 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Tim Wawrzynczak twawrzynczak@chromium.org --- M src/mainboard/google/brya/variants/baseboard/devicetree.cb 1 file changed, 98 insertions(+), 3 deletions(-)
Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved
diff --git a/src/mainboard/google/brya/variants/baseboard/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/devicetree.cb index 479a7ee..51a39c0 100644 --- a/src/mainboard/google/brya/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/devicetree.cb @@ -3,6 +3,104 @@ device lapic 0 on end end
+ register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" # USB2_C0 + register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC1)" # USB2_C1 + register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC2)" # USB2_C2 + register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WWAN + register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Camera + register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A0 + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Bluetooth + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC3)" # USB3/2 Type A port A0 + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 WWAN + + # Enable WLAN PCIE 5 using clk 2 + register "PchPcieRpEnable[5]" = "1" + register "PcieRpLtrEnable[5]" = "1" + register "PcieClkSrcUsage[2]" = "5" + register "PcieClkSrcClkReq[2]" = "2" + register "PcieRpAdvancedErrorReporting[5]" = "1" + + # Enable WWAN PCIE 6 using clk 5 + register "PchPcieRpEnable[6]" = "1" + register "PcieRpLtrEnable[6]" = "1" + register "PcieClkSrcUsage[5]" = "6" + register "PcieClkSrcClkReq[5]" = "5" + register "PcieRpAdvancedErrorReporting[6]" = "1" + + # Enable SD Card PCIE 8 using clk 3 + register "PchPcieRpEnable[7]" = "1" + register "PcieRpLtrEnable[7]" = "1" + register "PcieRpHotPlug[7]" = "1" + register "PcieClkSrcUsage[3]" = "7" + register "PcieClkSrcClkReq[3]" = "3" + register "PcieRpAdvancedErrorReporting[7]" = "1" + + # Enable NVMe PCIE 9 using clk 1 + register "PchPcieRpEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "1" + register "PcieClkSrcUsage[1]" = "8" + register "PcieClkSrcClkReq[1]" = "1" + register "PcieRpAdvancedErrorReporting[8]" = "1" + + register "SerialIoI2cMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoPci, + [PchSerialIoIndexI2C5] = PchSerialIoPci, + }" + + register "SerialIoGSpiMode" = "{ + [PchSerialIoIndexGSPI0] = PchSerialIoDisabled, + [PchSerialIoIndexGSPI1] = PchSerialIoPci, + }" + + register "SerialIoUartMode" = "{ + [PchSerialIoIndexUART0] = PchSerialIoPci, + [PchSerialIoIndexUART1] = PchSerialIoDisabled, + [PchSerialIoIndexUART2] = PchSerialIoDisabled, + }" + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | + #| GSPI1 | Fingerprint MCU | + #| I2C0 | Audio | + #| I2C1 | Touchscreen | + #| I2C2 | SAR0 | + #| I2C3 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| I2C4 | CAM | + #| I2C5 | Trackpad | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[3] = { + .early_init = 1, + .speed = I2C_SPEED_FAST, + }, + .i2c[4] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + }, + }" + device domain 0 on device ref igpu on end device ref dtt on end @@ -23,14 +121,11 @@ end device ref heci1 on end device ref sata on end - device ref pcie_rp1 on end #USB3-1 Type A - device ref pcie_rp4 on end #USB3-4 WWAN device ref pcie_rp5 on end #PCIE5 WLAN device ref pcie_rp6 on end #PCIE6 WWAN device ref pcie_rp8 on end #PCIE8 SD card device ref pcie_rp9 on end #PCIE9-12 SSD device ref uart0 on end - device ref gspi0 on end device ref gspi1 on end device ref pch_espi on chip ec/google/chromeec
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EricR Lai (Code Review) -
Furquan Shaikh (Code Review)
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Patrick Georgi (Code Review)
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Tim Wawrzynczak (Code Review)