Attention is currently required from: EricR Lai.
6 comments:
Patchset:
yes, because there is no chip in between, the registers still go with the SoC chip
Yes!
File src/mainboard/google/brya/variants/baseboard/devicetree.cb:
Patch Set #15, Line 32: [PchSerialIoIndexGSPI0] = 0,
Don't really need to set this as GSP0 is disabled. Same for CS state below.
Patch Set #15, Line 33: [PchSerialIoIndexGSPI1] = 1,
Do we need to initialize GSPI for FPMCU? Wouldn't this be done by the OS?
Patch Set #15, Line 105: #USB3-1 Type A
This comment doesn't really look right. Why does a PCIE RP device say USB3? Same for RP4 below.
one additional tab here and on next line.
Patch Set #15, Line 134: PCIE_RP_LTR
Why is LTR not enabled for WLAN and WWAN ports? Also, what about AER?
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