Attention is currently required from: Furquan Shaikh.
7 comments:
File src/mainboard/google/brya/variants/baseboard/devicetree.cb:
Patch Set #15, Line 32: [PchSerialIoIndexGSPI0] = 0,
Don't really need to set this as GSP0 is disabled. Same for CS state below.
Done
Patch Set #15, Line 33: [PchSerialIoIndexGSPI1] = 1,
Not sure here.
volteer enable this so keep this. We can remove this after?
Patch Set #15, Line 105: #USB3-1 Type A
No, the lanes would be owned by the USB controller and hence the PCIe RP should be kept off.
Done
Patch Set #15, Line 105: #USB3-1 Type A
No, the lanes would be owned by the USB controller and hence the PCIe RP should be kept off.
Done
one additional tab here and on next line.
Done
Patch Set #15, Line 134: PCIE_RP_LTR
I don't think that's correct. […]
Done
Patch Set #15, Line 134: PCIE_RP_LTR
I don't think that's correct. […]
Done
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