Tommie Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43442 )
Change subject: mb/google/volteer: Add new variant Lingcod ......................................................................
mb/google/volteer: Add new variant Lingcod
This commit creates new Lingcod variant for Volteer.
BUG=b:161103776 BRANCH=volteer TEST=emerge-volteer coreboot
Change-Id: I6f79431d3948788ce27ae14b469ffc229ebf8b6a Signed-off-by: tong.lin tong.lin@bitland.corp-partner.google.com --- M src/mainboard/google/volteer/Kconfig M src/mainboard/google/volteer/Kconfig.name A src/mainboard/google/volteer/variants/lingcod/Makefile.inc A src/mainboard/google/volteer/variants/lingcod/gpio.c A src/mainboard/google/volteer/variants/lingcod/include/variant/ec.h A src/mainboard/google/volteer/variants/lingcod/include/variant/gpio.h A src/mainboard/google/volteer/variants/lingcod/memory.c A src/mainboard/google/volteer/variants/lingcod/memory/Makefile.inc A src/mainboard/google/volteer/variants/lingcod/memory/dram_id.generated.txt A src/mainboard/google/volteer/variants/lingcod/memory/mem_list_variant.txt A src/mainboard/google/volteer/variants/lingcod/overridetree.cb 11 files changed, 312 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/43442/1
diff --git a/src/mainboard/google/volteer/Kconfig b/src/mainboard/google/volteer/Kconfig index 16834ae..ab85d22 100644 --- a/src/mainboard/google/volteer/Kconfig +++ b/src/mainboard/google/volteer/Kconfig @@ -68,6 +68,7 @@ config MAINBOARD_PART_NUMBER string default "Halvor" if BOARD_GOOGLE_HALVOR + default "Lingcod" if BOARD_GOOGLE_LINGCOD default "Malefor" if BOARD_GOOGLE_MALEFOR default "Terrador" if BOARD_GOOGLE_TERRADOR default "Trondo" if BOARD_GOOGLE_TRONDO @@ -101,6 +102,7 @@ config VARIANT_DIR string default "halvor" if BOARD_GOOGLE_HALVOR + default "lingcod" if BOARD_GOOGLE_LINGCOD default "malefor" if BOARD_GOOGLE_MALEFOR default "terrador" if BOARD_GOOGLE_TERRADOR default "trondo" if BOARD_GOOGLE_TRONDO diff --git a/src/mainboard/google/volteer/Kconfig.name b/src/mainboard/google/volteer/Kconfig.name index 8e6d884..88c6277 100644 --- a/src/mainboard/google/volteer/Kconfig.name +++ b/src/mainboard/google/volteer/Kconfig.name @@ -5,6 +5,11 @@ select BOARD_GOOGLE_BASEBOARD_VOLTEER select SOC_INTEL_CSE_LITE_SKU
+config BOARD_GOOGLE_LINGCOD + bool "-> Lingcod" + select BOARD_GOOGLE_BASEBOARD_VOLTEER + select SOC_INTEL_CSE_LITE_SKU + config BOARD_GOOGLE_MALEFOR bool "-> Malefor" select BOARD_GOOGLE_BASEBOARD_VOLTEER diff --git a/src/mainboard/google/volteer/variants/lingcod/Makefile.inc b/src/mainboard/google/volteer/variants/lingcod/Makefile.inc new file mode 100644 index 0000000..343c7db --- /dev/null +++ b/src/mainboard/google/volteer/variants/lingcod/Makefile.inc @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0-only + +romstage-y += memory.c + +bootblock-y += gpio.c + +ramstage-y += gpio.c diff --git a/src/mainboard/google/volteer/variants/lingcod/gpio.c b/src/mainboard/google/volteer/variants/lingcod/gpio.c new file mode 100644 index 0000000..cdffb60 --- /dev/null +++ b/src/mainboard/google/volteer/variants/lingcod/gpio.c @@ -0,0 +1,203 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <commonlib/helpers.h> + +/* Pad configuration in ramstage */ +/* Leave eSPI pins untouched from default settings */ +static const struct pad_config gpio_table[] = { + /* A0 thru A6 come configured out of reset, do not touch */ + /* A0 : ESPI_IO0 ==> ESPI_IO_0 */ + /* A1 : ESPI_IO1 ==> ESPI_IO_1 */ + /* A2 : ESPI_IO2 ==> ESPI_IO_2 */ + /* A3 : ESPI_IO3 ==> ESPI_IO_3 */ + /* A4 : ESPI_CS# ==> ESPI_CS_L */ + /* A5 : ESPI_CLK ==> ESPI_CLK */ + /* A6 : ESPI_RESET# ==> NC(TP764) */ + /* A7 : I2S2_SCLK ==> EN_PP3300_TRACKPAD */ + PAD_CFG_GPO(GPP_A7, 1, DEEP), + /* A8 : I2S2_SFRM ==> EN_PP3300_TOUCHSCREEN */ + PAD_CFG_GPO(GPP_A8, 0, DEEP), + /* A10 : I2S2_RXD ==> EN_SPKR_PA */ + PAD_CFG_GPO(GPP_A10, 1, DEEP), + /* A13 : PMC_I2C_SCL ==> BT_DISABLE_L */ + PAD_CFG_GPO(GPP_A13, 1, DEEP), + /* A16 : USB_OC3# ==> USB_C0_OC_ODL */ + PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), + /* A18 : DDSP_HPDB ==> HDMI_HPD */ + PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), + /* A19 : DDSP_HPD1 ==> USB_C0_DP_HPD */ + PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1), + /* A20 : DDSP_HPD2 ==> USB_C1_DP_HPD */ + PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1), + /* A21 : DDPC_CTRCLK ==> EN_FP_PWR */ + PAD_CFG_GPO(GPP_A21, 1, DEEP), + /* A22 : DDPC_CTRLDATA ==> EN_HDMI_PWR */ + PAD_CFG_GPO(GPP_A22, 1, DEEP), + /* A23 : I2S1_SCLK ==> I2S1_SPKR_SCLK */ + PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1), + + /* B2 : VRALERT# ==> NOT USED */ + PAD_NC(GPP_B2, NONE), + /* B3 : CPU_GP2 ==> PEN_DET_ODL */ + PAD_CFG_GPI(GPP_B3, NONE, DEEP), + /* B9 : I2C5_SDA ==> PCH_I2C5_TRACKPAD_SDA */ + PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), + /* B10 : I2C5_SCL ==> PCH_I2C5_TRACKPAD_SCL */ + PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), + /* B19 : GSPI1_CS0# ==> PCH_GSPI1_FPMCU_CS_L */ + PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1), + /* B20 : GSPI1_CLK ==> PCH_GSPI1_FPMCU_CLK */ + PAD_CFG_NF(GPP_B20, NONE, DEEP, NF1), + /* B21 : GSPI1_MISO ==> PCH_GSPI1_FPMCU_MISO */ + PAD_CFG_NF(GPP_B21, NONE, DEEP, NF1), + /* B22 : GSPI1_MOSI ==> PCH_GSPI1_GPMCU_MOSI */ + PAD_CFG_NF(GPP_B22, NONE, DEEP, NF1), + + /* C0 : SMBCLK ==> EN_PP3300_WLAN */ + PAD_CFG_GPO(GPP_C0, 1, DEEP), + /* C7 : SML1DATA ==> EN_USI_CHARGE */ + PAD_CFG_GPO(GPP_C7, 1, DEEP), + /* C10 : UART0_RTS# ==> USI_RST_L */ + PAD_CFG_GPO(GPP_C10, 0, DEEP), + /* C11 : UART0_CTS# ==> NOT USED */ + PAD_NC(GPP_C11, NONE), + /* C16 : I2C0_SDA ==> PCH_I2C0_1V8_AUDIO_SDA */ + PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), + /* C17 : I2C0_SCL ==> PCH_I2C0_1V8_AUDIO_SCL */ + PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), + /* C18 : I2C1_SDA ==> PCH_I2C1_TOUCH_USI_SDA */ + PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), + /* C19 : I2C1_SCL ==> PCH_I2C1_TOUCH_USI_SCL */ + PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), + /* C20 : UART2_RXD ==> FPMCU_INT_L */ + PAD_CFG_GPI_INT(GPP_C20, NONE, PLTRST, LEVEL), + /* C22 : UART2_RTS# ==> PCH_FPMCU_BOOT0 */ + PAD_CFG_GPO(GPP_C22, 0, DEEP), + /* C23 : UART2_CTS# ==> FPMCU_RST_ODL */ + PAD_CFG_GPO(GPP_C23, 1, DEEP), + + /* D5 : SRCCLKREQ0$ ==> SSD_CLKREQ_ODL */ + PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), + /* D6 : SRCCLKREQ1# ==> WLAN_CLKREQ_ODL */ + PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), + /* D8 : SRCCLKREQ3# ==> SD_CLKREQ_ODL */ + PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), + /* D16 : ISH_UART0_CTS# ==> EN_PP3300_SD */ + PAD_CFG_GPO(GPP_D16, 1, DEEP), + /* D17 : ISH_GP4 ==> EN_CVF_PWR */ + PAD_CFG_GPO(GPP_D17, 1, DEEP), + + /* E1 : SPI1_IO2 ==> PEN_DET_ODL */ + PAD_CFG_GPI_SCI_LOW(GPP_E1, NONE, DEEP, EDGE_SINGLE), + /* E2 : SPI1_IO3 ==> WLAN_PCIE_WAKE_ODL */ + PAD_CFG_GPI(GPP_E2, NONE, DEEP), + /* E3 : CPU_GP0 ==> USI_REPORT_EN */ + PAD_CFG_GPO(GPP_E3, 1, DEEP), + /* E4 : SATA_DEVSLP0 ==> M2_SSD_PE_WAKE_ODL */ + PAD_CFG_GPI(GPP_E4, NONE, DEEP), + /* E7 : CPU_GP1 ==> USI_INT */ + PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST, LEVEL, NONE), + /* E11 : SPI1_CLK ==> SD_PE_WAKE_ODL */ + PAD_CFG_GPI(GPP_E11, NONE, DEEP), + /* E12 : SPI1_MISO_IO1 ==> PEN_ALERT_ODL */ + PAD_CFG_GPI(GPP_E12, NONE, DEEP), + /* E15 : ISH_GP6 ==> TRACKPAD_INT_ODL */ + PAD_CFG_GPI_IRQ_WAKE(GPP_E15, NONE, DEEP, LEVEL, INVERT), + + /* F6 : CNV_PA_BLANKING ==> NC */ + PAD_NC(GPP_F6, NONE), + /* F8 : I2S_MCLK2_INOUT ==> HP_INT_L */ + PAD_CFG_GPI_INT(GPP_F8, NONE, PLTRST, EDGE_BOTH), + /* F13 : GSXDOUT ==> WiFi_DISABLE_L */ + PAD_CFG_GPO(GPP_F13, 1, DEEP), + /* F19 : SRCCLKREQ6# ==> WLAN_INT_L */ + PAD_CFG_GPI_SCI_LOW(GPP_F19, NONE, DEEP, EDGE_SINGLE), + + /* H3 : SX_EXIT_HOLDOFF# ==> SD_PERST_L */ + PAD_CFG_GPO(GPP_H3, 1, DEEP), + /* H8 : I2C4_SDA ==> NC */ + PAD_NC(GPP_H8, NONE), + /* H9 : I2C4_SCL ==> NC */ + PAD_NC(GPP_H9, NONE), + /* H11 : SRCCLKREQ5# ==> WLAN_PERST_L */ + PAD_CFG_GPO(GPP_H11, 1, DEEP), + /* H16 : DDPB_CTRLCLK ==> DDPB_HDMI_CTRLCLK */ + PAD_CFG_NF(GPP_H16, NONE, DEEP, NF1), + /* H17 : DDPB_CTRLDATA ==> DDPB_HDMI_CTRLDATA */ + PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), + /* H19 : TIME_SYNC0 ==> USER_PRES_FP_ODL */ + PAD_CFG_GPI(GPP_H19, NONE, DEEP), + + /* R0 : HDA_BCLK ==> I2S0_HP_SCLK */ + PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2), + /* R1 : HDA_SYNC ==> I2S0_HP_SFRM */ + PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2), + /* R2 : HDA_SDO ==> I2S0_PCH_TX_HP_RX_STRAP */ + PAD_CFG_NF(GPP_R2, DN_20K, DEEP, NF2), + /* R3 : HDA_SDIO ==> I2S0_PCH_RX_HP_TX */ + PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2), + /* R5 : HDA_SDI1 ==> I2S1_PCH_RX_SPKR_TX */ + PAD_CFG_NF(GPP_R5, NONE, DEEP, NF2), + /* R6 : I2S1_TXD ==> I2S1_PCH_RX_SPKR_RX */ + PAD_CFG_NF(GPP_R6, NONE, DEEP, NF2), + /* R7 : I2S1_SFRM ==> I2S1_SPKR_SFRM */ + PAD_CFG_NF(GPP_R7, NONE, DEEP, NF2), + + /* S6 : SNDW3_CLK ==> DMIC_CLK0 */ + PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2), + /* S7 : SNDW3_DATA ==> DMIC_DATA0 */ + PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2), +}; + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* A12 : SATAXPCIE1 ==> M2_SSD_PEDET */ + PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), + + /* A17 : DDSP_HPDC ==> MEM_CH_SEL */ + PAD_CFG_GPI(GPP_A17, NONE, DEEP), + + /* B11 : PMCALERT# ==> PCH_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_B11, NONE, DEEP), + + /* B15 : GSPI0_CS0# ==> PCH_GSPI0_H1_TPM_CS_L */ + PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), + + /* B16 : GSPI0_CLK ==> PCH_GSPI0_H1_TPM_CLK */ + PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), + + /* B17 : GSPI0_MISO ==> PCH_GSPIO_H1_TPM_MISO */ + PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), + + /* B18 : GSPI0_MOSI ==> PCH_GSPI0_H1_TPM_MOSI_STRAP */ + PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), + + /* C0 : SMBCLK ==> EN_PP3300_WLAN */ + PAD_CFG_GPO(GPP_C0, 1, DEEP), + + /* C21 : UART2_TXD ==> H1_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), + + /* C22 : UART2_RTS# ==> PCH_FPMCU_BOOT0 */ + PAD_CFG_GPO(GPP_C22, 0, DEEP), + + /* E12 : SPI1_MISO_IO1 ==> PEN_ALERT_ODL */ + PAD_CFG_GPO(GPP_E12, 1, DEEP), + + /* H11 : SRCCLKREQ5# ==> WLAN_PERST_L */ + PAD_CFG_GPO(GPP_H11, 1, DEEP), +}; + +const struct pad_config *variant_override_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} diff --git a/src/mainboard/google/volteer/variants/lingcod/include/variant/ec.h b/src/mainboard/google/volteer/variants/lingcod/include/variant/ec.h new file mode 100644 index 0000000..4a9a461 --- /dev/null +++ b/src/mainboard/google/volteer/variants/lingcod/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __VARIANT_EC_H__ +#define __VARIANT_EC_H__ + +#include <baseboard/ec.h> + +#endif diff --git a/src/mainboard/google/volteer/variants/lingcod/include/variant/gpio.h b/src/mainboard/google/volteer/variants/lingcod/include/variant/gpio.h new file mode 100644 index 0000000..0075826 --- /dev/null +++ b/src/mainboard/google/volteer/variants/lingcod/include/variant/gpio.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include <baseboard/gpio.h> + +/* Copied from baseboard and may need to change for the new variant. */ + +#endif diff --git a/src/mainboard/google/volteer/variants/lingcod/memory.c b/src/mainboard/google/volteer/variants/lingcod/memory.c new file mode 100644 index 0000000..5444c6f --- /dev/null +++ b/src/mainboard/google/volteer/variants/lingcod/memory.c @@ -0,0 +1,60 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <baseboard/variants.h> + +static const struct lpddr4x_cfg malefor_memcfg = { + /* DQ byte map */ + .dq_map = { + [0] = { + { 3, 1, 0, 2, 4, 6, 7, 5, }, /* DDR0_DQ0[7:0] */ + { 12, 13, 14, 15, 8, 9, 10, 11 }, /* DDR0_DQ1[7:0] */ + }, + [1] = { + { 0, 7, 1, 6, 2, 4, 3, 5, }, /* DDR1_DQ0[7:0] */ + { 8, 15, 14, 9, 13, 10, 12, 11 }, /* DDR1_DQ1[7:0] */ + }, + [2] = { + { 3, 2, 0, 1, 4, 5, 6, 7, }, /* DDR2_DQ0[7:0] */ + { 12, 13, 15, 14, 8, 9, 10, 11 }, /* DDR2_DQ1[7:0] */ + }, + [3] = { + { 6, 0, 1, 7, 5, 4, 2, 3, }, /* DDR3_DQ0[7:0] */ + { 15, 14, 8, 9, 10, 12, 11, 13 }, /* DDR3_DQ1[7:0] */ + }, + [4] = { + { 5, 0, 1, 3, 4, 2, 7, 6, }, /* DDR4_DQ0[7:0] */ + { 11, 14, 13, 12, 8, 9, 15, 10 }, /* DDR4_DQ1[7:0] */ + }, + [5] = { + { 3, 4, 2, 5, 0, 6, 1, 7, }, /* DDR5_DQ0[7:0] */ + { 13, 12, 11, 10, 14, 15, 9, 8 }, /* DDR5_DQ1[7:0] */ + }, + [6] = { + { 3, 2, 1, 0, 5, 4, 7, 6, }, /* DDR6_DQ0[7:0] */ + { 12, 13, 15, 14, 8, 11, 9, 10 }, /* DDR6_DQ1[7:0] */ + }, + [7] = { + { 3, 4, 2, 5, 1, 0, 7, 6, }, /* DDR7_DQ0[7:0] */ + { 15, 14, 9, 8, 12, 10, 11, 13 }, /* DDR7_DQ1[7:0] */ + }, + }, + + /* DQS CPU<>DRAM map */ + .dqs_map = { + [0] = { 0, 1 }, /* DDR0_DQS[1:0] */ + [1] = { 0, 1 }, /* DDR1_DQS[1:0] */ + [2] = { 0, 1 }, /* DDR2_DQS[1:0] */ + [3] = { 0, 1 }, /* DDR3_DQS[1:0] */ + [4] = { 0, 1 }, /* DDR4_DQS[1:0] */ + [5] = { 0, 1 }, /* DDR5_DQS[1:0] */ + [6] = { 0, 1 }, /* DDR6_DQS[1:0] */ + [7] = { 0, 1 }, /* DDR7_DQS[1:0] */ + }, + + .ect = 1, /* Enable Early Command Training */ +}; + +const struct lpddr4x_cfg *variant_memory_params(void) +{ + return &malefor_memcfg; +} diff --git a/src/mainboard/google/volteer/variants/lingcod/memory/Makefile.inc b/src/mainboard/google/volteer/variants/lingcod/memory/Makefile.inc new file mode 100644 index 0000000..b0c7319 --- /dev/null +++ b/src/mainboard/google/volteer/variants/lingcod/memory/Makefile.inc @@ -0,0 +1,5 @@ +## SPDX-License-Identifier: GPL-2.0-or-later +## This is an auto-generated file. Do not edit!! + +SPD_SOURCES = +SPD_SOURCES += spd-1.hex # ID = 0(0b0000) Parts = K4U6E3S4AA-MGCR, MT53E512M32D2NP-046 WT:E, H9HCNNNBKMMLXR-NEE diff --git a/src/mainboard/google/volteer/variants/lingcod/memory/dram_id.generated.txt b/src/mainboard/google/volteer/variants/lingcod/memory/dram_id.generated.txt new file mode 100644 index 0000000..0b033c8 --- /dev/null +++ b/src/mainboard/google/volteer/variants/lingcod/memory/dram_id.generated.txt @@ -0,0 +1,4 @@ +DRAM Part Name ID to assign +K4U6E3S4AA-MGCR 0 (0000) +MT53E512M32D2NP-046 WT:E 0 (0000) +H9HCNNNBKMMLXR-NEE 0 (0000) diff --git a/src/mainboard/google/volteer/variants/lingcod/memory/mem_list_variant.txt b/src/mainboard/google/volteer/variants/lingcod/memory/mem_list_variant.txt new file mode 100644 index 0000000..dfce32c --- /dev/null +++ b/src/mainboard/google/volteer/variants/lingcod/memory/mem_list_variant.txt @@ -0,0 +1,3 @@ +K4U6E3S4AA-MGCR +MT53E512M32D2NP-046 WT:E +H9HCNNNBKMMLXR-NEE diff --git a/src/mainboard/google/volteer/variants/lingcod/overridetree.cb b/src/mainboard/google/volteer/variants/lingcod/overridetree.cb new file mode 100644 index 0000000..b12e47a --- /dev/null +++ b/src/mainboard/google/volteer/variants/lingcod/overridetree.cb @@ -0,0 +1,5 @@ +chip soc/intel/tigerlake + + device domain 0 on + end +end
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43442 )
Change subject: mb/google/volteer: Add new variant Lingcod ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/43442/1/src/mainboard/google/voltee... File src/mainboard/google/volteer/variants/lingcod/gpio.c:
https://review.coreboot.org/c/coreboot/+/43442/1/src/mainboard/google/voltee... PS1, Line 130: /* H19 : TIME_SYNC0 ==> USER_PRES_FP_ODL */ 'PRES' may be misspelled - perhaps 'PRESS'?
Hello build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43442
to look at the new patch set (#2).
Change subject: mb/google/volteer: Add new variant Lingcod ......................................................................
mb/google/volteer: Add new variant Lingcod
This commit creates new Lingcod variant for Volteer.
BUG=b:161103776 BRANCH=volteer TEST=emerge-volteer coreboot
Change-Id: I6f79431d3948788ce27ae14b469ffc229ebf8b6a Signed-off-by: tong.lin tong.lin@bitland.corp-partner.google.com --- M src/mainboard/google/volteer/Kconfig M src/mainboard/google/volteer/Kconfig.name A src/mainboard/google/volteer/variants/lingcod/Makefile.inc A src/mainboard/google/volteer/variants/lingcod/gpio.c A src/mainboard/google/volteer/variants/lingcod/include/variant/ec.h A src/mainboard/google/volteer/variants/lingcod/include/variant/gpio.h A src/mainboard/google/volteer/variants/lingcod/memory.c A src/mainboard/google/volteer/variants/lingcod/memory/Makefile.inc A src/mainboard/google/volteer/variants/lingcod/memory/dram_id.generated.txt A src/mainboard/google/volteer/variants/lingcod/memory/mem_list_variant.txt A src/mainboard/google/volteer/variants/lingcod/overridetree.cb 11 files changed, 312 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/43442/2
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43442 )
Change subject: mb/google/volteer: Add new variant Lingcod ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/43442/2/src/mainboard/google/voltee... File src/mainboard/google/volteer/variants/lingcod/gpio.c:
https://review.coreboot.org/c/coreboot/+/43442/2/src/mainboard/google/voltee... PS2, Line 130: /* H19 : TIME_SYNC0 ==> USER_PRES_FP_ODL */ 'PRES' may be misspelled - perhaps 'PRESS'?
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43442 )
Change subject: mb/google/volteer: Add new variant Lingcod ......................................................................
Patch Set 2: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/43442/2/src/mainboard/google/voltee... File src/mainboard/google/volteer/variants/lingcod/include/variant/gpio.h:
https://review.coreboot.org/c/coreboot/+/43442/2/src/mainboard/google/voltee... PS2, Line 8: /* Copied from baseboard and may need to change for the new variant. */ Any changes needed?
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43442 )
Change subject: mb/google/volteer: Add new variant Lingcod ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/43442/3/src/mainboard/google/voltee... File src/mainboard/google/volteer/variants/lingcod/gpio.c:
https://review.coreboot.org/c/coreboot/+/43442/3/src/mainboard/google/voltee... PS3, Line 130: /* H19 : TIME_SYNC0 ==> USER_PRES_FP_ODL */ 'PRES' may be misspelled - perhaps 'PRESS'?
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Angel Pons, Peichao Li,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43442
to look at the new patch set (#4).
Change subject: mb/google/volteer: Add new variant Lingcod ......................................................................
mb/google/volteer: Add new variant Lingcod
This commit creates new Lingcod variant for Volteer. Fine tune GPIO and memory based on Lingcod schematics.
BUG=b:161103776 BRANCH=volteer TEST=emerge-volteer coreboot
Change-Id: I6f79431d3948788ce27ae14b469ffc229ebf8b6a Signed-off-by: tong.lin tong.lin@bitland.corp-partner.google.com --- M src/mainboard/google/volteer/Kconfig M src/mainboard/google/volteer/Kconfig.name A src/mainboard/google/volteer/variants/lingcod/Makefile.inc A src/mainboard/google/volteer/variants/lingcod/gpio.c A src/mainboard/google/volteer/variants/lingcod/include/variant/ec.h A src/mainboard/google/volteer/variants/lingcod/include/variant/gpio.h A src/mainboard/google/volteer/variants/lingcod/memory.c A src/mainboard/google/volteer/variants/lingcod/memory/Makefile.inc A src/mainboard/google/volteer/variants/lingcod/memory/dram_id.generated.txt A src/mainboard/google/volteer/variants/lingcod/memory/mem_list_variant.txt A src/mainboard/google/volteer/variants/lingcod/overridetree.cb 11 files changed, 321 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/43442/4
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43442 )
Change subject: mb/google/volteer: Add new variant Lingcod ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/43442/4/src/mainboard/google/voltee... File src/mainboard/google/volteer/variants/lingcod/gpio.c:
https://review.coreboot.org/c/coreboot/+/43442/4/src/mainboard/google/voltee... PS4, Line 136: /* H19 : TIME_SYNC0 ==> USER_PRES_FP_ODL */ 'PRES' may be misspelled - perhaps 'PRESS'?
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43442 )
Change subject: mb/google/volteer: Add new variant Lingcod ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/43442/4//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/43442/4//COMMIT_MSG@17 PS4, Line 17: tong.lin Please use “Tommie Lin”? (Or whatever is “correct”.)
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Angel Pons, Peichao Li,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43442
to look at the new patch set (#5).
Change subject: mb/google/volteer: Create a new variant for Lingcod ......................................................................
mb/google/volteer: Create a new variant for Lingcod
This commit creates new Lingcod variant for Volteer. Fine tune GPIO and memory based on Lingcod schematics.
BUG=b:161103776 BRANCH=volteer TEST=emerge-volteer coreboot
Change-Id: I6f79431d3948788ce27ae14b469ffc229ebf8b6a Signed-off-by: Tommie Lin tong.lin@bitland.corp-partner.google.com --- M src/mainboard/google/volteer/Kconfig M src/mainboard/google/volteer/Kconfig.name A src/mainboard/google/volteer/variants/lingcod/Makefile.inc A src/mainboard/google/volteer/variants/lingcod/gpio.c A src/mainboard/google/volteer/variants/lingcod/include/variant/ec.h A src/mainboard/google/volteer/variants/lingcod/include/variant/gpio.h A src/mainboard/google/volteer/variants/lingcod/memory.c A src/mainboard/google/volteer/variants/lingcod/memory/Makefile.inc A src/mainboard/google/volteer/variants/lingcod/memory/dram_id.generated.txt A src/mainboard/google/volteer/variants/lingcod/memory/mem_list_variant.txt A src/mainboard/google/volteer/variants/lingcod/overridetree.cb 11 files changed, 321 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/43442/5
Tommie Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43442 )
Change subject: mb/google/volteer: Create a new variant for Lingcod ......................................................................
Patch Set 5:
(2 comments)
https://review.coreboot.org/c/coreboot/+/43442/4//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/43442/4//COMMIT_MSG@17 PS4, Line 17: tong.lin
Please use “Tommie Lin”? (Or whatever is “correct”. […]
Done
https://review.coreboot.org/c/coreboot/+/43442/2/src/mainboard/google/voltee... File src/mainboard/google/volteer/variants/lingcod/include/variant/gpio.h:
https://review.coreboot.org/c/coreboot/+/43442/2/src/mainboard/google/voltee... PS2, Line 8: /* Copied from baseboard and may need to change for the new variant. */
Any changes needed?
I have tuned GPIO based on Lingcod schematics.
Tommie Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43442 )
Change subject: mb/google/volteer: Create a new variant for Lingcod ......................................................................
Patch Set 5: Code-Review+1
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43442 )
Change subject: mb/google/volteer: Create a new variant for Lingcod ......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/c/coreboot/+/43442/6/src/mainboard/google/voltee... File src/mainboard/google/volteer/variants/lingcod/gpio.c:
https://review.coreboot.org/c/coreboot/+/43442/6/src/mainboard/google/voltee... PS6, Line 136: /* H19 : TIME_SYNC0 ==> USER_PRES_FP_ODL */ 'PRES' may be misspelled - perhaps 'PRESS'?
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43442 )
Change subject: mb/google/volteer: Create a new variant for Lingcod ......................................................................
Patch Set 6: Code-Review+1
(7 comments)
https://review.coreboot.org/c/coreboot/+/43442/6//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/43442/6//COMMIT_MSG@14 PS6, Line 14: TEST=emerge-volteer coreboot The most important question is: does it boot? 😄
https://review.coreboot.org/c/coreboot/+/43442/6/src/mainboard/google/voltee... File src/mainboard/google/volteer/variants/lingcod/gpio.c:
https://review.coreboot.org/c/coreboot/+/43442/6/src/mainboard/google/voltee... PS6, Line 49: /* B19 : GSPI1_CS0# ==> PCH_GSPI1_FPMCU_CS_L */ : PAD_NC(GPP_B19, NONE), : /* B20 : GSPI1_CLK ==> PCH_GSPI1_FPMCU_CLK */ : PAD_NC(GPP_B20, NONE), : /* B21 : GSPI1_MISO ==> PCH_GSPI1_FPMCU_MISO */ : PAD_NC(GPP_B21, NONE), : /* B22 : GSPI1_MOSI ==> PCH_GSPI1_GPMCU_MOSI */ : PAD_NC(GPP_B22, NONE), These comments would need to be updated to reflect that GSPI1 is not used
https://review.coreboot.org/c/coreboot/+/43442/6/src/mainboard/google/voltee... PS6, Line 136: USER_PRES_FP_ODL Is this comment accurate?
https://review.coreboot.org/c/coreboot/+/43442/6/src/mainboard/google/voltee... PS6, Line 156: /* S6 : SNDW3_CLK ==> DMIC_CLK0 */ : PAD_CFG_NF(GPP_S6, NONE, DEEP, NF1), : /* S7 : SNDW3_DATA ==> DMIC_DATA0 */ : PAD_CFG_NF(GPP_S7, NONE, DEEP, NF1), I see this has been changed from NF2 to NF1. Is NF1 DMIC_CLK0, though?
https://review.coreboot.org/c/coreboot/+/43442/2/src/mainboard/google/voltee... File src/mainboard/google/volteer/variants/lingcod/include/variant/gpio.h:
https://review.coreboot.org/c/coreboot/+/43442/2/src/mainboard/google/voltee... PS2, Line 8: /* Copied from baseboard and may need to change for the new variant. */
I have tuned GPIO based on Lingcod schematics.
Ack
https://review.coreboot.org/c/coreboot/+/43442/6/src/mainboard/google/voltee... File src/mainboard/google/volteer/variants/lingcod/memory.c:
https://review.coreboot.org/c/coreboot/+/43442/6/src/mainboard/google/voltee... PS6, Line 5: malefor Oops, this isn't Malefor 😄
https://review.coreboot.org/c/coreboot/+/43442/6/src/mainboard/google/voltee... File src/mainboard/google/volteer/variants/lingcod/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/43442/6/src/mainboard/google/voltee... PS6, Line 3: device domain 0 on I'd say GSPI1 should be disabled, as the GPIOs for it are not used.
Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth, Angel Pons, Peichao Li, Zhuohao Lee,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43442
to look at the new patch set (#7).
Change subject: mb/google/volteer: Add new variant Lingcod ......................................................................
mb/google/volteer: Add new variant Lingcod
This commit creates new Lingcod variant for Volteer. Fine tune GPIO and memory based on Lingcod schematics.
BUG=b:161103776 BRANCH=volteer TEST=emerge-volteer coreboot, and boot into chromeos on proto board
Change-Id: I6f79431d3948788ce27ae14b469ffc229ebf8b6a Signed-off-by: tong.lin tong.lin@bitland.corp-partner.google.com --- M src/mainboard/google/volteer/Kconfig M src/mainboard/google/volteer/Kconfig.name A src/mainboard/google/volteer/variants/lingcod/Makefile.inc A src/mainboard/google/volteer/variants/lingcod/gpio.c A src/mainboard/google/volteer/variants/lingcod/include/variant/ec.h A src/mainboard/google/volteer/variants/lingcod/include/variant/gpio.h A src/mainboard/google/volteer/variants/lingcod/memory.c A src/mainboard/google/volteer/variants/lingcod/memory/Makefile.inc A src/mainboard/google/volteer/variants/lingcod/memory/dram_id.generated.txt A src/mainboard/google/volteer/variants/lingcod/memory/mem_list_variant.txt A src/mainboard/google/volteer/variants/lingcod/overridetree.cb 11 files changed, 384 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/43442/7
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43442 )
Change subject: mb/google/volteer: Add new variant Lingcod ......................................................................
Patch Set 7:
(1 comment)
https://review.coreboot.org/c/coreboot/+/43442/7/src/mainboard/google/voltee... File src/mainboard/google/volteer/variants/lingcod/gpio.c:
https://review.coreboot.org/c/coreboot/+/43442/7/src/mainboard/google/voltee... PS7, Line 130: /* H19 : TIME_SYNC0 ==> USER_PRES_FP_ODL */ 'PRES' may be misspelled - perhaps 'PRESS'?
Tommie Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43442 )
Change subject: mb/google/volteer: Add new variant Lingcod ......................................................................
Patch Set 7:
(5 comments)
https://review.coreboot.org/c/coreboot/+/43442/6/src/mainboard/google/voltee... File src/mainboard/google/volteer/variants/lingcod/gpio.c:
https://review.coreboot.org/c/coreboot/+/43442/6/src/mainboard/google/voltee... PS6, Line 49: /* B19 : GSPI1_CS0# ==> PCH_GSPI1_FPMCU_CS_L */ : PAD_NC(GPP_B19, NONE), : /* B20 : GSPI1_CLK ==> PCH_GSPI1_FPMCU_CLK */ : PAD_NC(GPP_B20, NONE), : /* B21 : GSPI1_MISO ==> PCH_GSPI1_FPMCU_MISO */ : PAD_NC(GPP_B21, NONE), : /* B22 : GSPI1_MOSI ==> PCH_GSPI1_GPMCU_MOSI */ : PAD_NC(GPP_B22, NONE),
These comments would need to be updated to reflect that GSPI1 is not used
Done
https://review.coreboot.org/c/coreboot/+/43442/6/src/mainboard/google/voltee... PS6, Line 136: USER_PRES_FP_ODL
Is this comment accurate?
No, the correct is USER_PRES_FP_ODL
https://review.coreboot.org/c/coreboot/+/43442/6/src/mainboard/google/voltee... PS6, Line 156: /* S6 : SNDW3_CLK ==> DMIC_CLK0 */ : PAD_CFG_NF(GPP_S6, NONE, DEEP, NF1), : /* S7 : SNDW3_DATA ==> DMIC_DATA0 */ : PAD_CFG_NF(GPP_S7, NONE, DEEP, NF1),
I see this has been changed from NF2 to NF1. […]
Sorry, it is NF2, not NF1.
https://review.coreboot.org/c/coreboot/+/43442/6/src/mainboard/google/voltee... File src/mainboard/google/volteer/variants/lingcod/memory.c:
https://review.coreboot.org/c/coreboot/+/43442/6/src/mainboard/google/voltee... PS6, Line 5: malefor
Oops, this isn't Malefor 😄
Done
https://review.coreboot.org/c/coreboot/+/43442/6/src/mainboard/google/voltee... File src/mainboard/google/volteer/variants/lingcod/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/43442/6/src/mainboard/google/voltee... PS6, Line 3: device domain 0 on
I'd say GSPI1 should be disabled, as the GPIOs for it are not used.
GSPI1 has been disabled, like gpio.c +49~56
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43442 )
Change subject: mb/google/volteer: Add new variant Lingcod ......................................................................
Patch Set 8:
(1 comment)
https://review.coreboot.org/c/coreboot/+/43442/8/src/mainboard/google/voltee... File src/mainboard/google/volteer/variants/lingcod/gpio.c:
https://review.coreboot.org/c/coreboot/+/43442/8/src/mainboard/google/voltee... PS8, Line 130: /* H19 : TIME_SYNC0 ==> USER_PRES_FP_ODL */ 'PRES' may be misspelled - perhaps 'PRESS'?
Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth, Angel Pons, Peichao Li, Zhuohao Lee,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43442
to look at the new patch set (#9).
Change subject: mb/google/volteer: Add new variant Lingcod ......................................................................
mb/google/volteer: Add new variant Lingcod
This commit creates new Lingcod variant for Volteer. Fine tune GPIO and memory based on Lingcod schematics.
BUG=b:161103776 BRANCH=volteer TEST=emerge-volteer coreboot, and boot into chromeos on proto board
Change-Id: I6f79431d3948788ce27ae14b469ffc229ebf8b6a Signed-off-by: tong.lin tong.lin@bitland.corp-partner.google.com --- M src/mainboard/google/volteer/Kconfig M src/mainboard/google/volteer/Kconfig.name A src/mainboard/google/volteer/variants/lingcod/Makefile.inc A src/mainboard/google/volteer/variants/lingcod/gpio.c A src/mainboard/google/volteer/variants/lingcod/include/variant/ec.h A src/mainboard/google/volteer/variants/lingcod/include/variant/gpio.h A src/mainboard/google/volteer/variants/lingcod/memory.c A src/mainboard/google/volteer/variants/lingcod/memory/Makefile.inc A src/mainboard/google/volteer/variants/lingcod/memory/dram_id.generated.txt A src/mainboard/google/volteer/variants/lingcod/memory/mem_list_variant.txt A src/mainboard/google/volteer/variants/lingcod/overridetree.cb 11 files changed, 406 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/43442/9
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43442 )
Change subject: mb/google/volteer: Add new variant Lingcod ......................................................................
Patch Set 9:
(1 comment)
https://review.coreboot.org/c/coreboot/+/43442/9/src/mainboard/google/voltee... File src/mainboard/google/volteer/variants/lingcod/gpio.c:
https://review.coreboot.org/c/coreboot/+/43442/9/src/mainboard/google/voltee... PS9, Line 130: /* H19 : TIME_SYNC0 ==> USER_PRES_FP_ODL */ 'PRES' may be misspelled - perhaps 'PRESS'?
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43442 )
Change subject: mb/google/volteer: Add new variant Lingcod ......................................................................
Patch Set 9: Code-Review+1
(5 comments)
https://review.coreboot.org/c/coreboot/+/43442/6//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/43442/6//COMMIT_MSG@14 PS6, Line 14: TEST=emerge-volteer coreboot
The most important question is: does it boot? 😄
Done
https://review.coreboot.org/c/coreboot/+/43442/6/src/mainboard/google/voltee... File src/mainboard/google/volteer/variants/lingcod/gpio.c:
https://review.coreboot.org/c/coreboot/+/43442/6/src/mainboard/google/voltee... PS6, Line 136: USER_PRES_FP_ODL
No, the correct is USER_PRES_FP_ODL
Ack
https://review.coreboot.org/c/coreboot/+/43442/6/src/mainboard/google/voltee... PS6, Line 156: /* S6 : SNDW3_CLK ==> DMIC_CLK0 */ : PAD_CFG_NF(GPP_S6, NONE, DEEP, NF1), : /* S7 : SNDW3_DATA ==> DMIC_DATA0 */ : PAD_CFG_NF(GPP_S7, NONE, DEEP, NF1),
Sorry, it is NF2, not NF1.
Done
https://review.coreboot.org/c/coreboot/+/43442/6/src/mainboard/google/voltee... File src/mainboard/google/volteer/variants/lingcod/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/43442/6/src/mainboard/google/voltee... PS6, Line 3: device domain 0 on
GSPI1 has been disabled, like gpio. […]
Ack
https://review.coreboot.org/c/coreboot/+/43442/9/src/mainboard/google/voltee... File src/mainboard/google/volteer/variants/lingcod/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/43442/9/src/mainboard/google/voltee... PS9, Line 23: register "SerialIoI2cMode" = "{ Nit: I think this has to define all SerialIO devices. It's an array, so uninitialized elements will be zero
Zhuohao Lee has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43442 )
Change subject: mb/google/volteer: Add new variant Lingcod ......................................................................
Patch Set 9:
(14 comments)
Do you have the lingcod gpio vs volteer gpio table? I would like to double check your GPIO setting.
https://review.coreboot.org/c/coreboot/+/43442/9/src/mainboard/google/voltee... File src/mainboard/google/volteer/variants/lingcod/gpio.c:
https://review.coreboot.org/c/coreboot/+/43442/9/src/mainboard/google/voltee... PS9, Line 8: /* Leave eSPI pins untouched from default settings */ remove this.
https://review.coreboot.org/c/coreboot/+/43442/9/src/mainboard/google/voltee... PS9, Line 9: gpio_table rename to override_gpio_table to align with the other variant.
https://review.coreboot.org/c/coreboot/+/43442/9/src/mainboard/google/voltee... PS9, Line 10: /* A0 thru A6 come configured out of reset, do not touch */ : /* A0 : ESPI_IO0 ==> ESPI_IO_0 */ : /* A1 : ESPI_IO1 ==> ESPI_IO_1 */ : /* A2 : ESPI_IO2 ==> ESPI_IO_2 */ : /* A3 : ESPI_IO3 ==> ESPI_IO_3 */ : /* A4 : ESPI_CS# ==> ESPI_CS_L */ : /* A5 : ESPI_CLK ==> ESPI_CLK */ : /* A6 : ESPI_RESET# ==> NC(TP764) */ remove this. This is same as baseboard.
https://review.coreboot.org/c/coreboot/+/43442/9/src/mainboard/google/voltee... PS9, Line 28: /* A18 : DDSP_HPDB ==> NOT USED */ : PAD_NC(GPP_A18, NONE), remove this. This is same as baseboard.
https://review.coreboot.org/c/coreboot/+/43442/9/src/mainboard/google/voltee... PS9, Line 34: /* A21 : DDPC_CTRCLK ==> NOT USED */ : PAD_NC(GPP_A21, NONE), remove this. This is same as baseboard.
https://review.coreboot.org/c/coreboot/+/43442/9/src/mainboard/google/voltee... PS9, Line 49: /* B19 : GSPI1_CS0# ==> NOT USED */ : PAD_NC(GPP_B19, NONE), : /* B20 : GSPI1_CLK ==> NOT USED */ : PAD_NC(GPP_B20, NONE), : /* B21 : GSPI1_MISO ==> NOT USED */ : PAD_NC(GPP_B21, NONE), remove this. This is same as baseboard.
https://review.coreboot.org/c/coreboot/+/43442/9/src/mainboard/google/voltee... PS9, Line 60: /* C7 : SML1DATA ==> NOT USED */ : PAD_NC(GPP_C7, NONE), remove this. This is same as baseboard.
https://review.coreboot.org/c/coreboot/+/43442/9/src/mainboard/google/voltee... PS9, Line 64: /* C11 : UART0_CTS# ==> NOT USED */ : PAD_NC(GPP_C11, NONE), remove this. This is same as baseboard.
https://review.coreboot.org/c/coreboot/+/43442/9/src/mainboard/google/voltee... PS9, Line 74: /* C20 : UART2_RXD ==> NOT USED */ : PAD_NC(GPP_C20, NONE), remove this. This is same as baseboard.
https://review.coreboot.org/c/coreboot/+/43442/9/src/mainboard/google/voltee... PS9, Line 81: /* D5 : SRCCLKREQ0$ ==> SSD_CLKREQ_ODL */ : PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), remove this. This is same as baseboard.
https://review.coreboot.org/c/coreboot/+/43442/9/src/mainboard/google/voltee... PS9, Line 109: /* F6 : CNV_PA_BLANKING ==> NC */ : PAD_NC(GPP_F6, NONE), remove this. This is same as baseboard.
https://review.coreboot.org/c/coreboot/+/43442/9/src/mainboard/google/voltee... PS9, Line 120: /* H8 : I2C4_SDA ==> NOT USED */ : PAD_NC(GPP_H8, NONE), : /* H9 : I2C4_SCL ==> NOT USED */ : PAD_NC(GPP_H9, NONE), remove this. This is same as baseboard.
https://review.coreboot.org/c/coreboot/+/43442/9/src/mainboard/google/voltee... PS9, Line 198: gpio_table rename to override_gpio_table to align with the other variant.
https://review.coreboot.org/c/coreboot/+/43442/9/src/mainboard/google/voltee... PS9, Line 199: gpio_table rename to override_gpio_table to align with the other variant.
Tommie Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43442 )
Change subject: mb/google/volteer: Add new variant Lingcod ......................................................................
Patch Set 9:
(1 comment)
Patch Set 9:
(14 comments)
Do you have the lingcod gpio vs volteer gpio table? I would like to double check your GPIO setting.
Yes, I share S560&C560_PCH_GPIO_Table-20200629_Reviewed.xlsx with you on Google Drive.
https://review.coreboot.org/c/coreboot/+/43442/6//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/43442/6//COMMIT_MSG@14 PS6, Line 14: TEST=emerge-volteer coreboot
The most important question is: does it boot? 😄
Done
Hello build bot (Jenkins), Furquan Shaikh, Martin Roth, Angel Pons, Peichao Li, Zhuohao Lee,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43442
to look at the new patch set (#10).
Change subject: mb/google/volteer: Add new variant Lingcod ......................................................................
mb/google/volteer: Add new variant Lingcod
This commit creates new Lingcod variant for Volteer. Fine tune GPIO and memory based on Lingcod schematics.
BUG=b:161103776 BRANCH=volteer TEST=emerge-volteer coreboot, and boot into chromeos on proto board
Change-Id: I6f79431d3948788ce27ae14b469ffc229ebf8b6a Signed-off-by: tong.lin tong.lin@bitland.corp-partner.google.com --- M src/mainboard/google/volteer/Kconfig M src/mainboard/google/volteer/Kconfig.name A src/mainboard/google/volteer/variants/lingcod/Makefile.inc A src/mainboard/google/volteer/variants/lingcod/gpio.c A src/mainboard/google/volteer/variants/lingcod/include/variant/ec.h A src/mainboard/google/volteer/variants/lingcod/include/variant/gpio.h A src/mainboard/google/volteer/variants/lingcod/memory.c A src/mainboard/google/volteer/variants/lingcod/memory/Makefile.inc A src/mainboard/google/volteer/variants/lingcod/memory/dram_id.generated.txt A src/mainboard/google/volteer/variants/lingcod/memory/mem_list_variant.txt A src/mainboard/google/volteer/variants/lingcod/overridetree.cb 11 files changed, 373 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/43442/10
Tommie Lin has removed Patrick Georgi from this change. ( https://review.coreboot.org/c/coreboot/+/43442 )
Change subject: mb/google/volteer: Add new variant Lingcod ......................................................................
Removed reviewer Patrick Georgi.
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43442 )
Change subject: mb/google/volteer: Add new variant Lingcod ......................................................................
Patch Set 10:
(1 comment)
https://review.coreboot.org/c/coreboot/+/43442/10/src/mainboard/google/volte... File src/mainboard/google/volteer/variants/lingcod/gpio.c:
https://review.coreboot.org/c/coreboot/+/43442/10/src/mainboard/google/volte... PS10, Line 97: /* H19 : TIME_SYNC0 ==> USER_PRES_FP_ODL */ 'PRES' may be misspelled - perhaps 'PRESS'?
Zhuohao Lee has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43442 )
Change subject: mb/google/volteer: Add new variant Lingcod ......................................................................
Patch Set 10:
(7 comments)
https://review.coreboot.org/c/coreboot/+/43442/10/src/mainboard/google/volte... File src/mainboard/google/volteer/variants/lingcod/gpio.c:
https://review.coreboot.org/c/coreboot/+/43442/10/src/mainboard/google/volte... PS10, Line 51: /* C22 : UART2_RTS# ==> PCH_FPMCU_BOOT0 */ : PAD_CFG_GPO(GPP_C22, 0, DEEP), : /* C23 : UART2_CTS# ==> FPMCU_RST_ODL */ : PAD_CFG_GPO(GPP_C23, 1, DEEP), Could you please double check if you need to support the fingerprint? I don' find the fingerprint from the schematics.
https://review.coreboot.org/c/coreboot/+/43442/10/src/mainboard/google/volte... PS10, Line 62: /* D17 : ISH_GP4 ==> EN_CVF_PWR */ : PAD_CFG_GPO(GPP_D17, 1, DEEP), Do you need this? From the schematics, the PP3300_FCAM doesn't connect to anything. Please double check it.
https://review.coreboot.org/c/coreboot/+/43442/10/src/mainboard/google/volte... PS10, Line 65: /* E1 : SPI1_IO2 ==> PEN_DET_ODL */ : PAD_CFG_GPI_SCI_LOW(GPP_E1, NONE, DEEP, EDGE_SINGLE), Will the project support the pen ejection? I don't see the implementation from the schematics.
https://review.coreboot.org/c/coreboot/+/43442/10/src/mainboard/google/volte... PS10, Line 77: /* E12 : SPI1_MISO_IO1 ==> PEN_ALERT_ODL */ : PAD_CFG_GPI(GPP_E12, NONE, DEEP), Please check if this is needed. I don't see the pen charger.
https://review.coreboot.org/c/coreboot/+/43442/10/src/mainboard/google/volte... PS10, Line 97: /* H19 : TIME_SYNC0 ==> USER_PRES_FP_ODL */ : PAD_CFG_GPI(GPP_H19, NONE, DEEP), Could you please double check if you need to support the fingerprint?
https://review.coreboot.org/c/coreboot/+/43442/10/src/mainboard/google/volte... PS10, Line 153: /* C22 : UART2_RTS# ==> PCH_FPMCU_BOOT0 */ : PAD_CFG_GPO(GPP_C22, 0, DEEP), : Could you please double check if you need to support the fingerprint?
https://review.coreboot.org/c/coreboot/+/43442/10/src/mainboard/google/volte... PS10, Line 156: /* E12 : SPI1_MISO_IO1 ==> PEN_ALERT_ODL */ : PAD_CFG_GPO(GPP_E12, 1, DEEP), Please check if this is needed. I don't see the pen charger.
Hello build bot (Jenkins), Furquan Shaikh, Martin Roth, Angel Pons, Peichao Li, Zhuohao Lee,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43442
to look at the new patch set (#11).
Change subject: mb/google/volteer: Add new variant Lingcod ......................................................................
mb/google/volteer: Add new variant Lingcod
This commit creates new Lingcod variant for Volteer. Fine tune GPIO and memory based on Lingcod schematics.
BUG=b:161103776 BRANCH=volteer TEST=emerge-volteer coreboot, and boot into chromeos on proto board
Change-Id: I6f79431d3948788ce27ae14b469ffc229ebf8b6a Signed-off-by: tong.lin tong.lin@bitland.corp-partner.google.com --- M src/mainboard/google/volteer/Kconfig M src/mainboard/google/volteer/Kconfig.name A src/mainboard/google/volteer/variants/lingcod/Makefile.inc A src/mainboard/google/volteer/variants/lingcod/gpio.c A src/mainboard/google/volteer/variants/lingcod/include/variant/ec.h A src/mainboard/google/volteer/variants/lingcod/include/variant/gpio.h A src/mainboard/google/volteer/variants/lingcod/memory.c A src/mainboard/google/volteer/variants/lingcod/memory/Makefile.inc A src/mainboard/google/volteer/variants/lingcod/memory/dram_id.generated.txt A src/mainboard/google/volteer/variants/lingcod/memory/mem_list_variant.txt A src/mainboard/google/volteer/variants/lingcod/overridetree.cb 11 files changed, 355 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/43442/11
Tommie Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43442 )
Change subject: mb/google/volteer: Add new variant Lingcod ......................................................................
Patch Set 11:
(22 comments)
https://review.coreboot.org/c/coreboot/+/43442/9/src/mainboard/google/voltee... File src/mainboard/google/volteer/variants/lingcod/gpio.c:
https://review.coreboot.org/c/coreboot/+/43442/9/src/mainboard/google/voltee... PS9, Line 8: /* Leave eSPI pins untouched from default settings */
remove this.
Done
https://review.coreboot.org/c/coreboot/+/43442/9/src/mainboard/google/voltee... PS9, Line 9: gpio_table
rename to override_gpio_table to align with the other variant.
Done
https://review.coreboot.org/c/coreboot/+/43442/9/src/mainboard/google/voltee... PS9, Line 10: /* A0 thru A6 come configured out of reset, do not touch */ : /* A0 : ESPI_IO0 ==> ESPI_IO_0 */ : /* A1 : ESPI_IO1 ==> ESPI_IO_1 */ : /* A2 : ESPI_IO2 ==> ESPI_IO_2 */ : /* A3 : ESPI_IO3 ==> ESPI_IO_3 */ : /* A4 : ESPI_CS# ==> ESPI_CS_L */ : /* A5 : ESPI_CLK ==> ESPI_CLK */ : /* A6 : ESPI_RESET# ==> NC(TP764) */
remove this. This is same as baseboard.
Done
https://review.coreboot.org/c/coreboot/+/43442/9/src/mainboard/google/voltee... PS9, Line 28: /* A18 : DDSP_HPDB ==> NOT USED */ : PAD_NC(GPP_A18, NONE),
remove this. This is same as baseboard.
Done
https://review.coreboot.org/c/coreboot/+/43442/9/src/mainboard/google/voltee... PS9, Line 34: /* A21 : DDPC_CTRCLK ==> NOT USED */ : PAD_NC(GPP_A21, NONE),
remove this. This is same as baseboard.
Done
https://review.coreboot.org/c/coreboot/+/43442/9/src/mainboard/google/voltee... PS9, Line 49: /* B19 : GSPI1_CS0# ==> NOT USED */ : PAD_NC(GPP_B19, NONE), : /* B20 : GSPI1_CLK ==> NOT USED */ : PAD_NC(GPP_B20, NONE), : /* B21 : GSPI1_MISO ==> NOT USED */ : PAD_NC(GPP_B21, NONE),
remove this. This is same as baseboard.
Done
https://review.coreboot.org/c/coreboot/+/43442/9/src/mainboard/google/voltee... PS9, Line 60: /* C7 : SML1DATA ==> NOT USED */ : PAD_NC(GPP_C7, NONE),
remove this. This is same as baseboard.
Done
https://review.coreboot.org/c/coreboot/+/43442/9/src/mainboard/google/voltee... PS9, Line 64: /* C11 : UART0_CTS# ==> NOT USED */ : PAD_NC(GPP_C11, NONE),
remove this. This is same as baseboard.
Done
https://review.coreboot.org/c/coreboot/+/43442/9/src/mainboard/google/voltee... PS9, Line 74: /* C20 : UART2_RXD ==> NOT USED */ : PAD_NC(GPP_C20, NONE),
remove this. This is same as baseboard.
Done
https://review.coreboot.org/c/coreboot/+/43442/9/src/mainboard/google/voltee... PS9, Line 81: /* D5 : SRCCLKREQ0$ ==> SSD_CLKREQ_ODL */ : PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),
remove this. This is same as baseboard.
Done
https://review.coreboot.org/c/coreboot/+/43442/9/src/mainboard/google/voltee... PS9, Line 109: /* F6 : CNV_PA_BLANKING ==> NC */ : PAD_NC(GPP_F6, NONE),
remove this. This is same as baseboard.
Done
https://review.coreboot.org/c/coreboot/+/43442/9/src/mainboard/google/voltee... PS9, Line 120: /* H8 : I2C4_SDA ==> NOT USED */ : PAD_NC(GPP_H8, NONE), : /* H9 : I2C4_SCL ==> NOT USED */ : PAD_NC(GPP_H9, NONE),
remove this. This is same as baseboard.
Done
https://review.coreboot.org/c/coreboot/+/43442/9/src/mainboard/google/voltee... PS9, Line 198: gpio_table
rename to override_gpio_table to align with the other variant.
Done
https://review.coreboot.org/c/coreboot/+/43442/9/src/mainboard/google/voltee... PS9, Line 199: gpio_table
rename to override_gpio_table to align with the other variant.
Done
https://review.coreboot.org/c/coreboot/+/43442/10/src/mainboard/google/volte... File src/mainboard/google/volteer/variants/lingcod/gpio.c:
https://review.coreboot.org/c/coreboot/+/43442/10/src/mainboard/google/volte... PS10, Line 51: /* C22 : UART2_RTS# ==> PCH_FPMCU_BOOT0 */ : PAD_CFG_GPO(GPP_C22, 0, DEEP), : /* C23 : UART2_CTS# ==> FPMCU_RST_ODL */ : PAD_CFG_GPO(GPP_C23, 1, DEEP),
Could you please double check if you need to support the fingerprint? I don' find the fingerprint fr […]
We do not support fingerprint and PEN.
https://review.coreboot.org/c/coreboot/+/43442/10/src/mainboard/google/volte... PS10, Line 62: /* D17 : ISH_GP4 ==> EN_CVF_PWR */ : PAD_CFG_GPO(GPP_D17, 1, DEEP),
Do you need this? From the schematics, the PP3300_FCAM doesn't connect to anything. […]
Configure EN_FCAM_PWR to output HINGE_COMBO_P22 through U85.
https://review.coreboot.org/c/coreboot/+/43442/10/src/mainboard/google/volte... PS10, Line 65: /* E1 : SPI1_IO2 ==> PEN_DET_ODL */ : PAD_CFG_GPI_SCI_LOW(GPP_E1, NONE, DEEP, EDGE_SINGLE),
Will the project support the pen ejection? I don't see the implementation from the schematics.
Done
https://review.coreboot.org/c/coreboot/+/43442/10/src/mainboard/google/volte... PS10, Line 77: /* E12 : SPI1_MISO_IO1 ==> PEN_ALERT_ODL */ : PAD_CFG_GPI(GPP_E12, NONE, DEEP),
Please check if this is needed. I don't see the pen charger.
Done
https://review.coreboot.org/c/coreboot/+/43442/10/src/mainboard/google/volte... PS10, Line 97: /* H19 : TIME_SYNC0 ==> USER_PRES_FP_ODL */ : PAD_CFG_GPI(GPP_H19, NONE, DEEP),
Could you please double check if you need to support the fingerprint?
Done
https://review.coreboot.org/c/coreboot/+/43442/10/src/mainboard/google/volte... PS10, Line 153: /* C22 : UART2_RTS# ==> PCH_FPMCU_BOOT0 */ : PAD_CFG_GPO(GPP_C22, 0, DEEP), :
Could you please double check if you need to support the fingerprint?
Done
https://review.coreboot.org/c/coreboot/+/43442/10/src/mainboard/google/volte... PS10, Line 156: /* E12 : SPI1_MISO_IO1 ==> PEN_ALERT_ODL */ : PAD_CFG_GPO(GPP_E12, 1, DEEP),
Please check if this is needed. I don't see the pen charger.
Done
https://review.coreboot.org/c/coreboot/+/43442/9/src/mainboard/google/voltee... File src/mainboard/google/volteer/variants/lingcod/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/43442/9/src/mainboard/google/voltee... PS9, Line 23: register "SerialIoI2cMode" = "{
Nit: I think this has to define all SerialIO devices. […]
All 6 elements of the SerialIoI2cMode array are defined.
Hello build bot (Jenkins), Patrick Georgi, Furquan Shaikh, Martin Roth, Angel Pons, Peichao Li, Zhuohao Lee,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43442
to look at the new patch set (#12).
Change subject: mb/google/volteer: Add new variant Lingcod ......................................................................
mb/google/volteer: Add new variant Lingcod
This commit creates new Lingcod variant for Volteer. Fine tune GPIO and memory based on Lingcod schematics.
BUG=b:161103776 BRANCH=volteer TEST=emerge-volteer coreboot, and boot into chromeos on proto board
Change-Id: I6f79431d3948788ce27ae14b469ffc229ebf8b6a Signed-off-by: tong.lin tong.lin@bitland.corp-partner.google.com --- M src/mainboard/google/volteer/Kconfig M src/mainboard/google/volteer/Kconfig.name A src/mainboard/google/volteer/variants/lingcod/Makefile.inc A src/mainboard/google/volteer/variants/lingcod/gpio.c A src/mainboard/google/volteer/variants/lingcod/include/variant/ec.h A src/mainboard/google/volteer/variants/lingcod/include/variant/gpio.h A src/mainboard/google/volteer/variants/lingcod/memory.c A src/mainboard/google/volteer/variants/lingcod/memory/Makefile.inc A src/mainboard/google/volteer/variants/lingcod/memory/dram_id.generated.txt A src/mainboard/google/volteer/variants/lingcod/memory/mem_list_variant.txt A src/mainboard/google/volteer/variants/lingcod/overridetree.cb 11 files changed, 355 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/43442/12
Zhuohao Lee has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43442 )
Change subject: mb/google/volteer: Add new variant Lingcod ......................................................................
Patch Set 12:
(1 comment)
https://review.coreboot.org/c/coreboot/+/43442/10/src/mainboard/google/volte... File src/mainboard/google/volteer/variants/lingcod/gpio.c:
https://review.coreboot.org/c/coreboot/+/43442/10/src/mainboard/google/volte... PS10, Line 62: /* D17 : ISH_GP4 ==> EN_CVF_PWR */ : PAD_CFG_GPO(GPP_D17, 1, DEEP),
Configure EN_FCAM_PWR to output HINGE_COMBO_P22 through U85.
May i know what is the use case?
Tommie Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43442 )
Change subject: mb/google/volteer: Add new variant Lingcod ......................................................................
Patch Set 12:
(2 comments)
https://review.coreboot.org/c/coreboot/+/43442/10/src/mainboard/google/volte... File src/mainboard/google/volteer/variants/lingcod/gpio.c:
https://review.coreboot.org/c/coreboot/+/43442/10/src/mainboard/google/volte... PS10, Line 51: /* C22 : UART2_RTS# ==> PCH_FPMCU_BOOT0 */ : PAD_CFG_GPO(GPP_C22, 0, DEEP), : /* C23 : UART2_CTS# ==> FPMCU_RST_ODL */ : PAD_CFG_GPO(GPP_C23, 1, DEEP),
We do not support fingerprint and PEN.
Done
https://review.coreboot.org/c/coreboot/+/43442/10/src/mainboard/google/volte... PS10, Line 62: /* D17 : ISH_GP4 ==> EN_CVF_PWR */ : PAD_CFG_GPO(GPP_D17, 1, DEEP),
May i know what is the use case?
The output HINGE_COMBO_P22 is to power the camera.
Zhuohao Lee has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43442 )
Change subject: mb/google/volteer: Add new variant Lingcod ......................................................................
Patch Set 12:
(1 comment)
https://review.coreboot.org/c/coreboot/+/43442/10/src/mainboard/google/volte... File src/mainboard/google/volteer/variants/lingcod/gpio.c:
https://review.coreboot.org/c/coreboot/+/43442/10/src/mainboard/google/volte... PS10, Line 62: /* D17 : ISH_GP4 ==> EN_CVF_PWR */ : PAD_CFG_GPO(GPP_D17, 1, DEEP),
The output HINGE_COMBO_P22 is to power the camera.
Got it. Thanks
Attention is currently required from: Tommie Lin. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43442 )
Change subject: mb/google/volteer: Add new variant Lingcod ......................................................................
Patch Set 13:
(1 comment)
Patchset:
PS13: What is the status of this variant?
Martin L Roth has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/43442?usp=email )
Change subject: mb/google/volteer: Add new variant Lingcod ......................................................................
Abandoned
This patch has not been touched in over 12 months. Anyone who wants to take over work on this patch, please feel free to restore it and do any work needed to get it merged. If you create a new patch based on this work, please credit the original author.
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Angel Pons (Code Review) -
build bot (Jenkins) (Code Review)
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Martin L Roth (Code Review)
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Paul Menzel (Code Review)
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Tommie Lin (Code Review)
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Zhuohao Lee (Code Review)