Patch set 6:Code-Review +1
7 comments:
Patch Set #6, Line 14: TEST=emerge-volteer coreboot
The most important question is: does it boot? 😄
File src/mainboard/google/volteer/variants/lingcod/gpio.c:
/* B19 : GSPI1_CS0# ==> PCH_GSPI1_FPMCU_CS_L */
PAD_NC(GPP_B19, NONE),
/* B20 : GSPI1_CLK ==> PCH_GSPI1_FPMCU_CLK */
PAD_NC(GPP_B20, NONE),
/* B21 : GSPI1_MISO ==> PCH_GSPI1_FPMCU_MISO */
PAD_NC(GPP_B21, NONE),
/* B22 : GSPI1_MOSI ==> PCH_GSPI1_GPMCU_MOSI */
PAD_NC(GPP_B22, NONE),
These comments would need to be updated to reflect that GSPI1 is not used
Patch Set #6, Line 136: USER_PRES_FP_ODL
Is this comment accurate?
/* S6 : SNDW3_CLK ==> DMIC_CLK0 */
PAD_CFG_NF(GPP_S6, NONE, DEEP, NF1),
/* S7 : SNDW3_DATA ==> DMIC_DATA0 */
PAD_CFG_NF(GPP_S7, NONE, DEEP, NF1),
I see this has been changed from NF2 to NF1. Is NF1 DMIC_CLK0, though?
File src/mainboard/google/volteer/variants/lingcod/include/variant/gpio.h:
Patch Set #2, Line 8: /* Copied from baseboard and may need to change for the new variant. */
I have tuned GPIO based on Lingcod schematics.
Ack
File src/mainboard/google/volteer/variants/lingcod/memory.c:
Patch Set #6, Line 5: malefor
Oops, this isn't Malefor 😄
File src/mainboard/google/volteer/variants/lingcod/overridetree.cb:
Patch Set #6, Line 3: device domain 0 on
I'd say GSPI1 should be disabled, as the GPIOs for it are not used.
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