coreboot-gerrit April 2025

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[XS] Change in coreboot[main]: mb/novacustom/mtl-h/ramstage.c: Set Pinmux FSP UPDs
by Matt DeVillier (Code Review) 05 Apr '25

05 Apr '25

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86788?usp=email ) Change subject: mb/novacustom/mtl-h/ramstage.c: Set Pinmux FSP UPDs ...................................................................... mb/novacustom/mtl-h/ramstage.c: Set Pinmux FSP UPDs Set Pin Mux FSP UPDs as per mainboard schematic. Change-Id: Id075e236cee64527aab644616186a3e223c1bfc3 Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86788 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> --- M src/mainboard/novacustom/mtl-h/ramstage.c 1 file changed, 9 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Michał Żygowski: Looks good to me, approved diff --git a/src/mainboard/novacustom/mtl-h/ramstage.c b/src/mainboard/novacustom/mtl-h/ramstage.c index 19d14a6..637257a 100644 --- a/src/mainboard/novacustom/mtl-h/ramstage.c +++ b/src/mainboard/novacustom/mtl-h/ramstage.c @@ -35,6 +35,15 @@ params->PchEspiHostC10ReportEnable = 1; // Pinmux configuration + params->PchSerialIoI2cSdaPinMux[3] = 0x1A45CA06; // GPP_H6 + params->PchSerialIoI2cSclPinMux[3] = 0x1A45AA07; // GPP_H7 + + params->PchSerialIoI2cSdaPinMux[4] = 0x8A44CC0C; // GPP_E12 + params->PchSerialIoI2cSclPinMux[4] = 0x8A44AC0D; // GPP_E13 + + params->PchSerialIoI2cSdaPinMux[5] = 0x8A46CE0D; // GPP_F13 + params->PchSerialIoI2cSclPinMux[5] = 0x8A46AE0C; // GPP_F12 + params->CnviRfResetPinMux = 0x194CE404; // GPP_F04 params->CnviClkreqPinMux = 0x394CE605; // GPP_F05 -- To view, visit https://review.coreboot.org/c/coreboot/+/86788?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id075e236cee64527aab644616186a3e223c1bfc3 Gerrit-Change-Number: 86788 Gerrit-PatchSet: 7 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: mb/novacustom/mtl-h/romstage.c: Set Loadline FSP UPDs
by Matt DeVillier (Code Review) 05 Apr '25

05 Apr '25

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86787?usp=email ) Change subject: mb/novacustom/mtl-h/romstage.c: Set Loadline FSP UPDs ...................................................................... mb/novacustom/mtl-h/romstage.c: Set Loadline FSP UPDs Set AC / DC Load Line params. The values were dumped from original Clevo Insyde UEFI firmware, version 1.07.02 Change-Id: I4cf729fc55ed6f2722606f393b6aa45afe396a6e Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86787 Reviewed-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/novacustom/mtl-h/romstage.c 1 file changed, 7 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Michał Żygowski: Looks good to me, approved diff --git a/src/mainboard/novacustom/mtl-h/romstage.c b/src/mainboard/novacustom/mtl-h/romstage.c index 8fdd9ec..3eb1dca 100644 --- a/src/mainboard/novacustom/mtl-h/romstage.c +++ b/src/mainboard/novacustom/mtl-h/romstage.c @@ -27,5 +27,12 @@ }, }; + mupd->FspmConfig.AcLoadline[0] = 190; + mupd->FspmConfig.AcLoadline[1] = 310; + mupd->FspmConfig.AcLoadline[2] = 490; + mupd->FspmConfig.DcLoadline[0] = 190; + mupd->FspmConfig.DcLoadline[1] = 310; + mupd->FspmConfig.DcLoadline[2] = 490; + memcfg_init(mupd, &mem_config, &dimm_module_spd_info, half_populated); } -- To view, visit https://review.coreboot.org/c/coreboot/+/86787?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4cf729fc55ed6f2722606f393b6aa45afe396a6e Gerrit-Change-Number: 86787 Gerrit-PatchSet: 6 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: mb/google/fatcat/var/francka: Update HDA verb tables
by Matt DeVillier (Code Review) 05 Apr '25

05 Apr '25

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/87034?usp=email ) Change subject: mb/google/fatcat/var/francka: Update HDA verb tables ...................................................................... mb/google/fatcat/var/francka: Update HDA verb tables Enable internal DMIC for francka. Camera's DMIC is connected to the ALC256's DMIC pin. BUG=b:396558772 TEST=Camera's DMIC works on francka. Change-Id: Ie2b9fbd3d95cac145a4c64d9f07001d81880a0e5 Signed-off-by: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87034 Reviewed-by: Terry Cheong <htcheong(a)chromium.org> Reviewed-by: Jayvik Desai <jayvik(a)google.com> Reviewed-by: Pranava Y N <pranavayn(a)google.com> Reviewed-by: Subrata Banik <subratabanik(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/fatcat/variants/francka/hda_verb.c 1 file changed, 4 insertions(+), 5 deletions(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved Terry Cheong: Looks good to me, but someone else must approve Pranava Y N: Looks good to me, approved Jayvik Desai: Looks good to me, approved diff --git a/src/mainboard/google/fatcat/variants/francka/hda_verb.c b/src/mainboard/google/fatcat/variants/francka/hda_verb.c index 2f703b7..2f49bf2 100644 --- a/src/mainboard/google/fatcat/variants/francka/hda_verb.c +++ b/src/mainboard/google/fatcat/variants/francka/hda_verb.c @@ -6,7 +6,7 @@ /* coreboot specific header */ 0x10ec0256, /* Codec Vendor / Device ID: Realtek ALC256 */ 0x10ec12ac, /* Subsystem ID */ - 0x00000013, /* Number of jacks (NID entries) */ + 0x00000015, /* Number of jacks (NID entries) */ AZALIA_RESET(0x1), /* NID 0x01, HDA Codec Subsystem ID Verb Table */ @@ -15,11 +15,10 @@ /* Pin Widget Verb Table */ /* * DMIC - * Requirement is to use PCH DMIC. Hence, - * commented out codec's Internal DMIC. - * AZALIA_PIN_CFG(0, 0x12, 0x90A60130), - * AZALIA_PIN_CFG(0, 0x13, 0x40000000), + * Internal DMIC. */ + AZALIA_PIN_CFG(0, 0x12, 0x90A60130), + AZALIA_PIN_CFG(0, 0x13, 0x90A60140), /* Pin widget 0x14 - Front (Port-D) */ AZALIA_PIN_CFG(0, 0x14, 0x90170110), /* Pin widget 0x18 - NPC */ -- To view, visit https://review.coreboot.org/c/coreboot/+/87034?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie2b9fbd3d95cac145a4c64d9f07001d81880a0e5 Gerrit-Change-Number: 87034 Gerrit-PatchSet: 2 Gerrit-Owner: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Terry Cheong <htcheong(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

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[S] Change in coreboot[main]: cpu/x86: Replace LAPIC_DM_* with LAPIC_MT_*
by Matt DeVillier (Code Review) 05 Apr '25

05 Apr '25

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86683?usp=email ) ( 4 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: cpu/x86: Replace LAPIC_DM_* with LAPIC_MT_* ...................................................................... cpu/x86: Replace LAPIC_DM_* with LAPIC_MT_* AMD64 spec refers to the field as MT (Message Type), but the IA64 spec refers to it as DM (Delivery Mode). The problem is that there is another field abbreviated as DM (Destination Mode) right next to it. So for better readability, just stick to the AMD64 terminology. Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com> Change-Id: I25cf69d555fe22526f128ff7ed41f82b71f2acf2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/86683 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Andy Ebrahiem <ahmet.ebrahiem(a)9elements.com> Reviewed-by: Jérémy Compostella <jeremy.compostella(a)intel.com> Reviewed-by: Shuo Liu <shuo.liu(a)intel.com> --- M src/cpu/intel/car/p4-netburst/cache_as_ram.S M src/cpu/x86/lapic/lapic_cpu_stop.c M src/cpu/x86/mp_init.c M src/include/cpu/x86/lapic_def.h 4 files changed, 16 insertions(+), 15 deletions(-) Approvals: Andy Ebrahiem: Looks good to me, but someone else must approve Jérémy Compostella: Looks good to me, approved Shuo Liu: Looks good to me, but someone else must approve build bot (Jenkins): Verified diff --git a/src/cpu/intel/car/p4-netburst/cache_as_ram.S b/src/cpu/intel/car/p4-netburst/cache_as_ram.S index 1843954..1ce28a4 100644 --- a/src/cpu/intel/car/p4-netburst/cache_as_ram.S +++ b/src/cpu/intel/car/p4-netburst/cache_as_ram.S @@ -111,7 +111,7 @@ /* Send INIT IPI to all excluding ourself. */ movl LAPIC(ICR), %edi - movl $(LAPIC_DEST_ALLBUT | LAPIC_INT_ASSERT | LAPIC_DM_INIT), %eax + movl $(LAPIC_DEST_ALLBUT | LAPIC_INT_ASSERT | LAPIC_MT_INIT), %eax 1: movl %eax, (%edi) movl $0x30, %ecx 2: pause @@ -160,7 +160,7 @@ /* Send Start IPI to all excluding ourself. */ movl LAPIC(ICR), %edi - movl $(LAPIC_DEST_ALLBUT | LAPIC_DM_STARTUP), %eax + movl $(LAPIC_DEST_ALLBUT | LAPIC_MT_STARTUP), %eax orl $ap_sipi_vector_in_rom, %eax 1: movl %eax, (%edi) movl $0x30, %ecx diff --git a/src/cpu/x86/lapic/lapic_cpu_stop.c b/src/cpu/x86/lapic/lapic_cpu_stop.c index 6eacba6..1709b95 100644 --- a/src/cpu/x86/lapic/lapic_cpu_stop.c +++ b/src/cpu/x86/lapic/lapic_cpu_stop.c @@ -56,7 +56,7 @@ printk(BIOS_DEBUG, "CPU %ld going down...\n", id); /* send an LAPIC INIT to myself */ - lapic_send_ipi_self(LAPIC_INT_LEVELTRIG | LAPIC_INT_ASSERT | LAPIC_DM_INIT); + lapic_send_ipi_self(LAPIC_INT_LEVELTRIG | LAPIC_INT_ASSERT | LAPIC_MT_INIT); wait_for_ipi_completion_without_printk(timeout_100ms); mdelay(10); @@ -64,7 +64,7 @@ dprintk(BIOS_SPEW, "Deasserting INIT.\n"); /* Deassert the LAPIC INIT */ - lapic_send_ipi_self(LAPIC_INT_LEVELTRIG | LAPIC_DM_INIT); + lapic_send_ipi_self(LAPIC_INT_LEVELTRIG | LAPIC_MT_INIT); wait_for_ipi_completion_without_printk(timeout_100ms); halt(); diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index 47b3a9e..574f28e 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -434,7 +434,7 @@ printk(BIOS_DEBUG, "done.\n"); } - lapic_send_ipi_others(LAPIC_INT_ASSERT | LAPIC_DM_STARTUP | sipi_vector); + lapic_send_ipi_others(LAPIC_INT_ASSERT | LAPIC_MT_STARTUP | sipi_vector); printk(BIOS_DEBUG, "Waiting for SIPI to complete...\n"); if (apic_wait_timeout(10000 /* 10 ms */, 50 /* us */) != CB_SUCCESS) { printk(BIOS_ERR, "timed out.\n"); @@ -474,7 +474,7 @@ } /* Send INIT IPI to all but self. */ - lapic_send_ipi_others(LAPIC_INT_ASSERT | LAPIC_DM_INIT); + lapic_send_ipi_others(LAPIC_INT_ASSERT | LAPIC_MT_INIT); if (!CONFIG(X86_INIT_NEED_1_SIPI)) { printk(BIOS_DEBUG, "Waiting for 10ms after sending INIT.\n"); @@ -658,7 +658,7 @@ printk(BIOS_DEBUG, "done.\n"); } - lapic_send_ipi_self(LAPIC_INT_ASSERT | LAPIC_DM_SMI); + lapic_send_ipi_self(LAPIC_INT_ASSERT | LAPIC_MT_SMI); if (lapic_busy()) { if (apic_wait_timeout(1000 /* 1 ms */, 100 /* us */) != CB_SUCCESS) { diff --git a/src/include/cpu/x86/lapic_def.h b/src/include/cpu/x86/lapic_def.h index e118b6b..cb5482c 100644 --- a/src/include/cpu/x86/lapic_def.h +++ b/src/include/cpu/x86/lapic_def.h @@ -42,14 +42,15 @@ #define LAPIC_INT_ASSERT 0x04000 #define LAPIC_ICR_BUSY 0x01000 #define LAPIC_DEST_LOGICAL 0x00800 -#define LAPIC_DM_FIXED 0x00000 -#define LAPIC_DM_LOWEST 0x00100 -#define LAPIC_DM_SMI 0x00200 -#define LAPIC_DM_REMRD 0x00300 -#define LAPIC_DM_NMI 0x00400 -#define LAPIC_DM_INIT 0x00500 -#define LAPIC_DM_STARTUP 0x00600 -#define LAPIC_DM_EXTINT 0x00700 +// AMD64 refers to it as MT (Message Type), but IA-64 refers to it as DM (Delivery Mode) +#define LAPIC_MT_FIXED 0x00000 +#define LAPIC_MT_LOWEST 0x00100 +#define LAPIC_MT_SMI 0x00200 +#define LAPIC_MT_REMRD 0x00300 +#define LAPIC_MT_NMI 0x00400 +#define LAPIC_MT_INIT 0x00500 +#define LAPIC_MT_STARTUP 0x00600 +#define LAPIC_MT_EXTINT 0x00700 #define LAPIC_VECTOR_MASK 0x000FF #define LAPIC_ICR2 0x310 #define GET_LAPIC_DEST_FIELD(x) (((x)>>24)&0xFF) -- To view, visit https://review.coreboot.org/c/coreboot/+/86683?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I25cf69d555fe22526f128ff7ed41f82b71f2acf2 Gerrit-Change-Number: 86683 Gerrit-PatchSet: 6 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Andy Ebrahiem <ahmet.ebrahiem(a)9elements.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

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[L] Change in coreboot[main]: mb/asus/p8x7x-series: Add p8b75-v variant
by Angel Pons (Code Review) 05 Apr '25

05 Apr '25

Attention is currently required from: Felix Held, Keith Hui. Angel Pons has posted comments on this change by Keith Hui. ( https://review.coreboot.org/c/coreboot/+/85792?usp=email ) Change subject: mb/asus/p8x7x-series: Add p8b75-v variant ...................................................................... Patch Set 3: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/85792/comment/efa990e5_ef284d34?us… : PS3, Line 21: to use both to build a 16MiB flash space but that's to be confirmed. Firmware update size should tell if it's 8 or 16 MiB: it's a capsule with a 8 MiB body. You could also dump the IFD settings to see the configured chip sizes, but looks like the firmware update capsule does not include IFD/ME regions 😐 My guess is that this is some sort of Dual BIOS feature. File src/mainboard/asus/p8x7x-series/variants/p8b75-v/cmos.layout: https://review.coreboot.org/c/coreboot/+/85792/comment/3925e9ce_8a8c50e3?us… : PS3, Line 30: 425 1 e 9 audio_panel_type Missing default? File src/mainboard/asus/p8x7x-series/variants/p8b75-v/gma-mainboard.ads: https://review.coreboot.org/c/coreboot/+/85792/comment/863e430b_a22c7b7d?us… : PS3, Line 12: DP1, : HDMI1, : HDMI2, : HDMI3, I only see DVI-D and VGA -- To view, visit https://review.coreboot.org/c/coreboot/+/85792?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibb14c9efd1fb5b8826a646aae5f3fab9d9c08187 Gerrit-Change-Number: 85792 Gerrit-PatchSet: 3 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Keith Hui <buurin(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Sat, 05 Apr 2025 13:07:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[M] Change in coreboot[main]: mb/cwwk: Add CWWK CW-ADLNTB-1C2L-V3.0 board as an adl variants
by Angel Pons (Code Review) 05 Apr '25

05 Apr '25

Attention is currently required from: Brandon Weeks, Felix Held, Julian Intronati, Paul Menzel. Angel Pons has posted comments on this change by Julian Intronati. ( https://review.coreboot.org/c/coreboot/+/87027?usp=email ) Change subject: mb/cwwk: Add CWWK CW-ADLNTB-1C2L-V3.0 board as an adl variants ...................................................................... Patch Set 4: Code-Review+2 (3 comments) File src/mainboard/cwwk/adl/variants/cw-adlntb-1c2l-v3.0/board_info.txt: https://review.coreboot.org/c/coreboot/+/87027/comment/f532aef5_f6734a98?us… : PS3, Line 1: CW-X86-P5-V3 > The internal product name of the board is "CW_ADLNTB_1C2L" into the original bios. […] Generally, I would use whatever name is written on the mainboard, as that should identify the hardware. Laptops and prebuilt desktops may be easier to identify by the commercial name (HP 280 G2 Microtower) as opposed to the mainboard codename (Foxconn H-ICEAGE) as the latter is significantly more obscure, but specifying both might be necessary in some cases to fully identify the hardware. I usually ignore the names in firmware, especially given that some firmwares say that the board name is "To be filled by O.E.M." (i.e. the OEM forgot to put the name in there) 😄 In any case, I marked this comment as resolved because I don't think it's a big deal. The current names seem fine to me. File src/mainboard/cwwk/adl/variants/cw-adlntb-1c2l-v3.0/gpio.c: https://review.coreboot.org/c/coreboot/+/87027/comment/9edae1a4_66537b22?us… : PS3, Line 167: /* ------- GPIO Group vGPIO ------- */ : //PAD_CFG_GPO(GPP_VGPIO_0, 0, DEEP), /* GPIO */ : //PAD_CFG_GPI_TRIG_OWN(GPP_VGPIO_4, NONE, DEEP, OFF, ACPI), /* GPIO */ : //PAD_CFG_GPIO_BIDIRECT(GPP_VGPIO_5, 1, NONE, DEEP, LEVEL, ACPI), /* GPIO */ : //PAD_CFG_NF(GPP_VGPIO_6, NONE, DEEP, NF1), /* GPP_VGPIO_6 */ : //PAD_CFG_NF(GPP_VGPIO_7, NONE, DEEP, NF1), /* GPP_VGPIO_7 */ : //PAD_CFG_NF(GPP_VGPIO_8, NONE, DEEP, NF1), /* GPP_VGPIO_8 */ : //PAD_CFG_NF(GPP_VGPIO_9, NONE, DEEP, NF1), /* GPP_VGPIO_9 */ : //PAD_CFG_NF(GPP_VGPIO_10, NONE, DEEP, NF1), /* GPP_VGPIO_10 */ : //PAD_CFG_NF(GPP_VGPIO_11, NONE, DEEP, NF1), /* GPP_VGPIO_11 */ : //PAD_CFG_NF(GPP_VGPIO_12, NONE, DEEP, NF1), /* GPP_VGPIO_12 */ : //PAD_CFG_NF(GPP_VGPIO_13, NONE, DEEP, NF1), /* GPP_VGPIO_13 */ : //PAD_CFG_NF(GPP_VGPIO_18, NONE, DEEP, NF1), /* GPP_VGPIO_18 */ : //PAD_CFG_NF(GPP_VGPIO_19, NONE, DEEP, NF1), /* GPP_VGPIO_19 */ : //PAD_CFG_NF(GPP_VGPIO_20, NONE, DEEP, NF1), /* GPP_VGPIO_20 */ : //PAD_CFG_NF(GPP_VGPIO_21, NONE, DEEP, NF1), /* GPP_VGPIO_21 */ : //PAD_CFG_NF(GPP_VGPIO_22, NONE, DEEP, NF1), /* GPP_VGPIO_22 */ : //PAD_CFG_NF(GPP_VGPIO_23, NONE, DEEP, NF1), /* GPP_VGPIO_23 */ : //PAD_CFG_NF(GPP_VGPIO_24, NONE, DEEP, NF1), /* GPP_VGPIO_24 */ : //PAD_CFG_NF(GPP_VGPIO_25, NONE, DEEP, NF1), /* GPP_VGPIO_25 */ : //PAD_CFG_NF(GPP_VGPIO_30, NONE, DEEP, NF1), /* GPP_VGPIO_30 */ : //PAD_CFG_NF(GPP_VGPIO_31, NONE, DEEP, NF1), /* GPP_VGPIO_31 */ : //PAD_CFG_NF(GPP_VGPIO_32, NONE, DEEP, NF1), /* GPP_VGPIO_32 */ : //PAD_CFG_NF(GPP_VGPIO_33, NONE, DEEP, NF1), /* GPP_VGPIO_33 */ : //PAD_CFG_NF(GPP_VGPIO_34, NONE, DEEP, NF1), /* GPP_VGPIO_34 */ : //PAD_CFG_NF(GPP_VGPIO_35, NONE, DEEP, NF1), /* GPP_VGPIO_35 */ : //PAD_CFG_NF(GPP_VGPIO_36, NONE, DEEP, NF1), /* GPP_VGPIO_36 */ : //PAD_CFG_NF(GPP_VGPIO_37, NONE, DEEP, NF1), /* GPP_VGPIO_37 */ > When i generated the file those gpio has been generated. […] I've never understood what these VGPIOs do, I'm not sure where they're documented (if they're even documented). If someone finds a reason to configure them in the future, then they can just make another change that adds them. So yes, I agree with removing the commented-out lines. File src/mainboard/cwwk/adl/variants/cw-adlntb-1c2l-v3.0/romstage.c: https://review.coreboot.org/c/coreboot/+/87027/comment/e5176fd0_5afaa830?us… : PS3, Line 22: 0x52 > Yeah this is a weird one, that one took me a bunch of debuging to understand, I was stuck on memory […] Oof, I can imagine. I know that, at least on older platforms, you can try reading the SPD with userspace tools (e.g. `decode-dimms` from `i2c-tools` on Linux). This saves you from having to guess, but I'm not sure if DDR5 works the same way. -- To view, visit https://review.coreboot.org/c/coreboot/+/87027?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia0553141b41717b560042de1136d53b9c3cf7a69 Gerrit-Change-Number: 87027 Gerrit-PatchSet: 4 Gerrit-Owner: Julian Intronati <julian.intronati(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Brandon Weeks <bweeks(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Julian Intronati <julian.intronati(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Brandon Weeks <bweeks(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Julian Intronati <julian.intronati(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Sat, 05 Apr 2025 12:57:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Julian Intronati <julian.intronati(a)gmail.com>

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[XS] Change in coreboot[main]: WIP: mainboard/fatcat: Temporarily disable barrel charger power limit...
by Subrata Banik (Code Review) 05 Apr '25

05 Apr '25

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/87183?usp=email ) Change subject: WIP: mainboard/fatcat: Temporarily disable barrel charger power limit optimization ...................................................................... WIP: mainboard/fatcat: Temporarily disable barrel charger power limit optimization This commit temporarily disables the logic that prevents CPU power limit optimization when a barrel charger is attached. This is being done to reduce the boot time for fatcat SKU. We don't wish to keep barrel charger detection logic which is time consuming. TEST=Able to reduce boot time by 62ms. Change-Id: I613417be5a59790b8a5e6055957a2f518f4c42df Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/mainboard/google/fatcat/variants/baseboard/fatcat/ramstage.c 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/87183/1 diff --git a/src/mainboard/google/fatcat/variants/baseboard/fatcat/ramstage.c b/src/mainboard/google/fatcat/variants/baseboard/fatcat/ramstage.c index 21f8ccd..3e6405e4 100644 --- a/src/mainboard/google/fatcat/variants/baseboard/fatcat/ramstage.c +++ b/src/mainboard/google/fatcat/variants/baseboard/fatcat/ramstage.c @@ -52,10 +52,11 @@ void baseboard_devtree_update(void) { +#if 0 /* Don't optimize the power limit if booting with barrel attached */ if (CONFIG(BOARD_GOOGLE_MODEL_FATCAT) && google_chromeec_is_barrel_charger_present()) return; - +#endif if (!google_chromeec_is_battery_present()) variant_update_cpu_power_limits(power_optimized_limits, ARRAY_SIZE(power_optimized_limits)); -- To view, visit https://review.coreboot.org/c/coreboot/+/87183?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I613417be5a59790b8a5e6055957a2f518f4c42df Gerrit-Change-Number: 87183 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com>

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[S] Change in coreboot[main]: cpu/x86: Conditionally invalidate caches based on self-snooping support
by Subrata Banik (Code Review) 05 Apr '25

05 Apr '25

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/87182?usp=email ) Change subject: cpu/x86: Conditionally invalidate caches based on self-snooping support ...................................................................... cpu/x86: Conditionally invalidate caches based on self-snooping support The code currently unconditionally flushes or invalidates the entire cache (using `clflush_region` or `wbinvd`) after loading the SIPI vector for APs and after loading SMM handlers. This commit modifies this behavior to only perform these cache operations if the CPU does *not* support self-snooping. Rationale: - Self-snooping CPUs can maintain cache coherency within the core/complex more efficiently. CPU with self-snoop enabled does not necessarily need to perform wbinvd to ensure data written to the cache is reflected in main memory. Self-snooping CPUs employ a write-back caching policy, combined with a cache coherence protocol, to manage data writes and ensure consistency between cache and main memory. When the BSP writes the SIPI vector or SMM handlers to memory, other units within the same CPU that might be caching these regions should be aware of the updates through the self-snooping mechanism. A full cache flush or invalidate to ensure cache contains reaches to main memory might be unnecessary and could negatively impact performance. By conditionally performing these cache operations based on `self_snooping_supported()`, we can optimize the boot process for CPUs that have advanced cache coherency features while maintaining correct behavior on older or simpler CPUs. TEST=Boot google/rex, brox and fatcat with this patch. Able to reduce boot time by ~19-25ms. Change-Id: If32439752d0ceaa03b1d81873ea0bc562092e9d5 Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/cpu/x86/mp_init.c 1 file changed, 12 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/87182/1 diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index 47b3a9e..06ab037 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -365,12 +365,14 @@ ap_count = &sp->ap_count; atomic_set(ap_count, 0); - /* Make sure SIPI data hits RAM so the APs that come up will see the - startup code even if the caches are disabled. */ - if (clflush_supported()) - clflush_region((uintptr_t)mod_loc, module_size); - else - wbinvd(); + if (!self_snooping_supported()) { + /* Make sure SIPI data hits RAM so the APs that come up will see the + startup code even if the caches are disabled. */ + if (clflush_supported()) + clflush_region((uintptr_t)mod_loc, module_size); + else + wbinvd(); + } return ap_count; } @@ -826,8 +828,10 @@ smm_disable(); } - /* Ensure the SMM handlers hit DRAM before performing first SMI. */ - wbinvd(); + if (!self_snooping_supported()) { + /* Ensure the SMM handlers hit DRAM before performing first SMI. */ + wbinvd(); + } /* * Indicate that the SMM handlers have been loaded and MP -- To view, visit https://review.coreboot.org/c/coreboot/+/87182?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If32439752d0ceaa03b1d81873ea0bc562092e9d5 Gerrit-Change-Number: 87182 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com>

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[XS] Change in coreboot[main]: src/arch/x86/c_start: Delete duplicated code masking stack pointer
by NyeonWoo Kim (Code Review) 05 Apr '25

05 Apr '25

NyeonWoo Kim has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/87181?usp=email ) Change subject: src/arch/x86/c_start: Delete duplicated code masking stack pointer ...................................................................... src/arch/x86/c_start: Delete duplicated code masking stack pointer I found duplicated code masking stack pointer. So, i'd like to remove the duplicate for refactoring :-). This is my build output of c_start.o, before vs after modifying. before modifying ... 44: f3 ab rep stos %eax,%es:(%edi) 46: bc 00 00 00 00 mov $0x0,%esp 4b: 83 e4 f0 and $0xfffffff0,%esp 4e: b0 6e mov $0x6e,%al 50: e6 80 out %al,$0x80 52: 83 e4 f0 and $0xfffffff0,%esp // deleted. 55: e8 fc ff ff ff call 56 <_start+0x56> ... after modifying ... 44: f3 ab rep stos %eax,%es:(%edi) 46: bc 00 00 00 00 mov $0x0,%esp 4b: 83 e4 f0 and $0xfffffff0,%esp 4e: b0 6e mov $0x6e,%al 50: e6 80 out %al,$0x80 52: e8 fc ff ff ff call 53 <_start+0x53> ... Change-Id: I417ce90279fea4b00432e6a209f77a6dd0c0fee6 Signed-off-by: NyeonWoo Kim <knw0507(a)naver.com> --- M src/arch/x86/c_start.S 1 file changed, 0 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/87181/1 diff --git a/src/arch/x86/c_start.S b/src/arch/x86/c_start.S index 94b9bd9..fd61cab4 100644 --- a/src/arch/x86/c_start.S +++ b/src/arch/x86/c_start.S @@ -101,13 +101,6 @@ */ post_code(POSTCODE_PRE_HARDWAREMAIN) /* post 6e */ -#if ENV_X86_64 - movq $0xFFFFFFFFFFFFFFF0, %rax - and %rax, %rsp -#else - andl $0xFFFFFFF0, %esp -#endif - #if CONFIG(ASAN_IN_RAMSTAGE) call asan_init #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/87181?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I417ce90279fea4b00432e6a209f77a6dd0c0fee6 Gerrit-Change-Number: 87181 Gerrit-PatchSet: 1 Gerrit-Owner: NyeonWoo Kim

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[L] Change in coreboot[main]: mb/asus/p8x7x-series: Add p8b75-v variant
by Keith Hui (Code Review) 05 Apr '25

05 Apr '25

Attention is currently required from: Felix Held, Keith Hui. Hello Felix Held, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85792?usp=email to look at the new patch set (#3). The following approvals got outdated and were removed: Code-Review+2 by Felix Held, Verified+1 by build bot (Jenkins) The change is no longer submittable: Code-Review and Verified are unsatisfied now. Change subject: mb/asus/p8x7x-series: Add p8b75-v variant ...................................................................... mb/asus/p8x7x-series: Add p8b75-v variant Not hardware tested; copied from p8h77-v and p8z77-m then adjusted USB port config and overridetree based on info seen from vendor firmware update and boardview. VBT extracted manually from vendor firmware update. Currently known facts about this board that aren't already coded into this patch: - 3 PCI slots wired to B75 PCI bridge - DRAM_LED on GP07 of SIO and power LED on GPIO27 of PCH, just like p8z77-m - Has TWO 8MiB SPI flash chips on board, both wired to PCH. It appears to use both to build a 16MiB flash space but that's to be confirmed. Change-Id: Ibb14c9efd1fb5b8826a646aae5f3fab9d9c08187 Signed-off-by: Keith Hui <buurin(a)gmail.com> --- A Documentation/mainboard/asus/p8b75-v.md M Documentation/mainboard/index.md M src/mainboard/asus/p8x7x-series/Kconfig M src/mainboard/asus/p8x7x-series/Kconfig.name A src/mainboard/asus/p8x7x-series/variants/p8b75-v/board_info.txt A src/mainboard/asus/p8x7x-series/variants/p8b75-v/cmos.default A src/mainboard/asus/p8x7x-series/variants/p8b75-v/cmos.layout A src/mainboard/asus/p8x7x-series/variants/p8b75-v/data.vbt A src/mainboard/asus/p8x7x-series/variants/p8b75-v/early_init.c A src/mainboard/asus/p8x7x-series/variants/p8b75-v/gma-mainboard.ads A src/mainboard/asus/p8x7x-series/variants/p8b75-v/gpio.c A src/mainboard/asus/p8x7x-series/variants/p8b75-v/hda_verb.c A src/mainboard/asus/p8x7x-series/variants/p8b75-v/overridetree.cb 13 files changed, 656 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/85792/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/85792?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibb14c9efd1fb5b8826a646aae5f3fab9d9c08187 Gerrit-Change-Number: 85792 Gerrit-PatchSet: 3 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Keith Hui <buurin(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>

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