coreboot-gerrit April 2025

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[main]: mb/starlabs/starbook/tgl: Reconfigure PCH Strap GPIOs
by Sean Rhodes (Code Review) 04 Apr '25

04 Apr '25

Attention is currently required from: Matt DeVillier. Sean Rhodes has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/87172?usp=email ) Change subject: mb/starlabs/starbook/tgl: Reconfigure PCH Strap GPIOs ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/87172?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I557bfc1339bad169753640c9404813305a16024e Gerrit-Change-Number: 87172 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Comment-Date: Fri, 04 Apr 2025 20:24:29 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: mb/starlabs/starbook/tgl: Tidy GPIO comments for SATA
by Sean Rhodes (Code Review) 04 Apr '25

04 Apr '25

Sean Rhodes has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/87173?usp=email ) Change subject: mb/starlabs/starbook/tgl: Tidy GPIO comments for SATA ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/87173?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iee7121aef28618c0877c97cf454dc1a279758c21 Gerrit-Change-Number: 87173 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 04 Apr 2025 20:24:27 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: mb/starlabs/starbook/mtl: Uncomment eSPI GPIOs
by Sean Rhodes (Code Review) 04 Apr '25

04 Apr '25

Sean Rhodes has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/87178?usp=email ) Change subject: mb/starlabs/starbook/mtl: Uncomment eSPI GPIOs ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/87178?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie013ce1769e61fae1622a9cc1a048229fd9d6944 Gerrit-Change-Number: 87178 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Comment-Date: Fri, 04 Apr 2025 20:24:23 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: mb/intel/ptlrvp: Update flashmap to allocate 14MB to BIOS
by Jamie Ryu (Code Review) 04 Apr '25

04 Apr '25

Attention is currently required from: Bora Guvendik, Jayvik Desai, Subrata Banik, Wonkyu Kim. Hello Bora Guvendik, Jayvik Desai, Subrata Banik, Wonkyu Kim, Wonkyu Kim, build bot (Jenkins), srinivas.kulkarni(a)intel.com, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/87035?usp=email to look at the new patch set (#2). Change subject: mb/intel/ptlrvp: Update flashmap to allocate 14MB to BIOS ...................................................................... mb/intel/ptlrvp: Update flashmap to allocate 14MB to BIOS This updates flashmap descriptor to allocate 18MB to SI_ME and 14MB for BIOS. PTL RVP coreboot is used with several types of RVP boards and this layout with 14MB BIOS is very convenient for debugging and creating coreboot for certain use cases and tests purpose. TEST=Build the ptlrvp variant(ES) and check flashmap of the coreboot is updated correctly. Change-Id: Ie85b79ae8f7d4e30cf48eb6301224b0cf01b8dff Signed-off-by: Jamie Ryu <jamie.m.ryu(a)intel.com> --- M src/mainboard/intel/ptlrvp/chromeos.fmd 1 file changed, 5 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/87035/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/87035?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie85b79ae8f7d4e30cf48eb6301224b0cf01b8dff Gerrit-Change-Number: 87035 Gerrit-PatchSet: 2 Gerrit-Owner: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Wonkyu Kim Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: srinivas.kulkarni(a)intel.com Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Wonkyu Kim Gerrit-Attention: Subrata Banik <subratabanik(a)google.com>

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[S] Change in coreboot[main]: mb/intel/ptlrvp: Update flashmap to allocate 14MB to BIOS
by Jamie Ryu (Code Review) 04 Apr '25

04 Apr '25

Attention is currently required from: Bora Guvendik, Jayvik Desai, Subrata Banik, Wonkyu Kim. Jamie Ryu has posted comments on this change by Jamie Ryu. ( https://review.coreboot.org/c/coreboot/+/87035?usp=email ) Change subject: mb/intel/ptlrvp: Update flashmap to allocate 14MB to BIOS ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > any reason why PTLRVP can't use same layout as fatcat ? We are trying to utilize ptlrvp target build with several types of internal boards and found this layout with 14MB BIOS is very convenient for debugging and creating coreboot for certain tests. Hope this makes sense and please let me know if you have any comments. Thank you. -- To view, visit https://review.coreboot.org/c/coreboot/+/87035?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie85b79ae8f7d4e30cf48eb6301224b0cf01b8dff Gerrit-Change-Number: 87035 Gerrit-PatchSet: 1 Gerrit-Owner: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Wonkyu Kim Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: srinivas.kulkarni(a)intel.com Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Wonkyu Kim Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Comment-Date: Fri, 04 Apr 2025 17:30:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[S] Change in coreboot[main]: mb/intel/ptlrvp: Update flashmap to allocate 14MB to BIOS
by Name of user not set (Code Review) 04 Apr '25

04 Apr '25

Attention is currently required from: Bora Guvendik, Jamie Ryu, Jayvik Desai, Wonkyu Kim. srinivas.kulkarni(a)intel.com has posted comments on this change by Jamie Ryu. ( https://review.coreboot.org/c/coreboot/+/87035?usp=email ) Change subject: mb/intel/ptlrvp: Update flashmap to allocate 14MB to BIOS ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/87035?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie85b79ae8f7d4e30cf48eb6301224b0cf01b8dff Gerrit-Change-Number: 87035 Gerrit-PatchSet: 1 Gerrit-Owner: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Wonkyu Kim Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: srinivas.kulkarni(a)intel.com Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Wonkyu Kim Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Comment-Date: Fri, 04 Apr 2025 17:20:10 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: mb/google/fatcat: Increase sagv_freq_mhz for work point #1 to #3
by Subrata Banik (Code Review) 04 Apr '25

04 Apr '25

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/87087?usp=email ) Change subject: mb/google/fatcat: Increase sagv_freq_mhz for work point #1 to #3 ...................................................................... mb/google/fatcat: Increase sagv_freq_mhz for work point #1 to #3 Update the SaGV frequency registers - (`sagv_freq_mhz[1]`) in the devicetree from "3200" to "4800". - (`sagv_freq_mhz[2]`) in the devicetree from "6000" to "6400". - (`sagv_freq_mhz[3]`) in the devicetree from "6400" to "6800". This change likely to improve the device performance. BUG=b:328770565, b:407862619 TEST=Able to reduce the boot time by 18ms. Change-Id: Id0b25adeed4b3f3e1c37d17901006a2db2d21223 Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87087 Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Bora Guvendik <bora.guvendik(a)intel.corp-partner.google.com> Reviewed-by: Pranava Y N <pranavayn(a)google.com> --- M src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb 1 file changed, 3 insertions(+), 3 deletions(-) Approvals: Bora Guvendik: Looks good to me, approved Pranava Y N: Looks good to me, approved build bot (Jenkins): Verified Kapil Porwal: Looks good to me, approved diff --git a/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb b/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb index aa297b1..6f04713 100644 --- a/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb +++ b/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb @@ -36,13 +36,13 @@ register "sagv_freq_mhz[0]" = "2400" register "sagv_gear[0]" = "GEAR_4" - register "sagv_freq_mhz[1]" = "3200" + register "sagv_freq_mhz[1]" = "4800" register "sagv_gear[1]" = "GEAR_4" - register "sagv_freq_mhz[2]" = "6000" + register "sagv_freq_mhz[2]" = "6400" register "sagv_gear[2]" = "GEAR_4" - register "sagv_freq_mhz[3]" = "6400" + register "sagv_freq_mhz[3]" = "6800" register "sagv_gear[3]" = "GEAR_4" # Enable s0ix -- To view, visit https://review.coreboot.org/c/coreboot/+/87087?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id0b25adeed4b3f3e1c37d17901006a2db2d21223 Gerrit-Change-Number: 87087 Gerrit-PatchSet: 7 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.corp-partner.google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: mb/google/fatcat: Increase sagv_freq_mhz for work point #1 to #3
by Bora Guvendik (Code Review) 04 Apr '25

04 Apr '25

Attention is currently required from: Jayvik Desai, Jérémy Compostella, Paul Menzel, Subrata Banik. Bora Guvendik has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/87087?usp=email ) Change subject: mb/google/fatcat: Increase sagv_freq_mhz for work point #1 to #3 ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/87087?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id0b25adeed4b3f3e1c37d17901006a2db2d21223 Gerrit-Change-Number: 87087 Gerrit-PatchSet: 6 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.corp-partner.google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Fri, 04 Apr 2025 16:04:33 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: soc/intel/cmn/blk: Refactor CSE status flag and optimize forced sync
by Dinesh Gehlot (Code Review) 04 Apr '25

04 Apr '25

Attention is currently required from: Intel coreboot Reviewers, Kapil Porwal, Subrata Banik. Dinesh Gehlot has posted comments on this change by Dinesh Gehlot. ( https://review.coreboot.org/c/coreboot/+/86153?usp=email ) Change subject: soc/intel/cmn/blk: Refactor CSE status flag and optimize forced sync ...................................................................... Patch Set 15: (5 comments) Patchset: PS13: > can you please combine CB:86152 CL into CB:86153 Acknowledged Commit Message: https://review.coreboot.org/c/coreboot/+/86153/comment/f6561275_bf107a4f?us… : PS14, Line 7: Remove boot partition check for forced cse sync > this code does more things than this commit title Acknowledged File src/soc/intel/common/block/cse/cse_lite.c: https://review.coreboot.org/c/coreboot/+/86153/comment/a2aa6541_1cd92245?us… : PS12, Line 751: if ((vb2api_gbb_get_flags(ctx) & VB2_GBB_FLAG_FORCE_CSE_SYNC) && : cse_get_current_bp() == RO) { > > The current flag-based implementation has backward compatibility and will always function regardle […] We use `is_cse_sync_enforced()` to determine if a forced CSE sync is pending, regardless of the boot partition. In the case of a RW boot, it is the sole indicator to switch to the RO boot partition. Please note, ESOL has a separate check and will only appear if booting from RO, even if is_cse_sync_enforced() returns true. https://review.coreboot.org/c/coreboot/+/86153/comment/14e44807_9e430131?us… : PS12, Line 765: is_cse_sync_enforced > > The ESOL screen function at romstage also calls `is_cse_sync_enforced()`. […] The status update has been decoupled from is_cse_sync_enforced() as `cmos_update_cse_sync_status()`. It is being called from all the https://review.coreboot.org/c/coreboot/+/86153/comment/23e5c7e0_8c1088fd?us… : PS12, Line 792: n cse_info_in_cmos.cse_sync_status & CSE_ENFORCED_SYNC_REQ; > > Yes, the sync status update exhibits a distinct behavior and warrants relocation to a dedicated fu […] The `is_cse_sync_enforced` and `cmos_update_cse_sync_status` has been decoupled. -- To view, visit https://review.coreboot.org/c/coreboot/+/86153?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If1e4180cb5fec3990fdee2b0e412173b1c8c6ded Gerrit-Change-Number: 86153 Gerrit-PatchSet: 15 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Fri, 04 Apr 2025 15:19:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Dinesh Gehlot <digehlot(a)google.com>

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[M] Change in coreboot[main]: soc/intel/cmn/blk: Refactor CSE status flag and optimize forced sync
by Dinesh Gehlot (Code Review) 04 Apr '25

04 Apr '25

Attention is currently required from: Dinesh Gehlot, Intel coreboot Reviewers, Kapil Porwal. Hello Intel coreboot Reviewers, Kapil Porwal, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86153?usp=email to look at the new patch set (#15). Change subject: soc/intel/cmn/blk: Refactor CSE status flag and optimize forced sync ...................................................................... soc/intel/cmn/blk: Refactor CSE status flag and optimize forced sync This patch enhances the forced CSE sync mechanism by eliminating the boot partition check for RO. It uses the persistent CMOS flags to preserve the forced CSE update status across boots. This patch also replaces the CSE status boolean variable with a bit field to optimize CMOS memory utilization. Consequently, the remaining bits can potentially be utilized for additional CSE states in future. BUG=b:380220737 TEST=Verified forced CSE sync on google/rex0. Change-Id: If1e4180cb5fec3990fdee2b0e412173b1c8c6ded Signed-off-by: Dinesh Gehlot <digehlot(a)google.com> --- M src/soc/intel/common/block/cse/cse_lite.c M src/soc/intel/common/block/include/intelblocks/cse.h 2 files changed, 71 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/86153/15 -- To view, visit https://review.coreboot.org/c/coreboot/+/86153?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If1e4180cb5fec3990fdee2b0e412173b1c8c6ded Gerrit-Change-Number: 86153 Gerrit-PatchSet: 15 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com>

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coreboot-gerrit April 2025