coreboot-gerrit April 2025

coreboot-gerrit@coreboot.org

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[M] Change in coreboot[main]: soc/mediatek/mt8189: Add USB host support
by Yidi Lin (Code Review) 04 Apr '25

04 Apr '25

Yidi Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/87021?usp=email ) Change subject: soc/mediatek/mt8189: Add USB host support ...................................................................... soc/mediatek/mt8189: Add USB host support Correct XHCI and PHY register addresses and enable USB port 3 VBUS to support USB host functionality. BUG=b:379008996 BRANCH=none TEST=build pass Signed-off-by: Liu Liu <ot_liu.liu(a)mediatek.corp-partner.google.com> Change-Id: I5f1b4b3eb178cb9a110b97a2763c8cff5cdf0ddd Reviewed-on: https://review.coreboot.org/c/coreboot/+/87021 Reviewed-by: Yidi Lin <yidilin(a)google.com> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/mediatek/mt8189/Makefile.mk M src/soc/mediatek/mt8189/include/soc/addressmap.h A src/soc/mediatek/mt8189/include/soc/usb.h A src/soc/mediatek/mt8189/usb.c 4 files changed, 49 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Yidi Lin: Looks good to me, approved Yu-Ping Wu: Looks good to me, approved diff --git a/src/soc/mediatek/mt8189/Makefile.mk b/src/soc/mediatek/mt8189/Makefile.mk index 00489c0..6774f52 100644 --- a/src/soc/mediatek/mt8189/Makefile.mk +++ b/src/soc/mediatek/mt8189/Makefile.mk @@ -17,6 +17,7 @@ ramstage-y += emi.c ramstage-y += soc.c +ramstage-y += ../common/usb.c usb.c CPPFLAGS_common += -Isrc/soc/mediatek/mt8189/include CPPFLAGS_common += -Isrc/soc/mediatek/common/include diff --git a/src/soc/mediatek/mt8189/include/soc/addressmap.h b/src/soc/mediatek/mt8189/include/soc/addressmap.h index c0c78b1..5d99728 100644 --- a/src/soc/mediatek/mt8189/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8189/include/soc/addressmap.h @@ -30,8 +30,9 @@ SFLASH_REG_BASE = IO_PHYS + 0x01018000, PERICFG_AO_BASE = IO_PHYS + 0x01036000, DEVAPC_PERI_PAR_AO_BASE = IO_PHYS + 0x0103C000, - SSUSB_IPPC_BASE = IO_PHYS + 0x01203E00, + SSUSB_IPPC_BASE = IO_PHYS + 0x01263E00, UFSHCI_BASE = IO_PHYS + 0x012B0000, + SSUSB_SIF_BASE = IO_PHYS + 0x01B00300, MIPITX0_BASE = IO_PHYS + 0x01B40000, IOCFG_LM_BASE = IO_PHYS + 0x01B50000, EDP_BASE = IO_PHYS + 0x01B70000, @@ -42,7 +43,6 @@ IOCFG_BM2_BASE = IO_PHYS + 0x01D40000, IOCFG_LT0_BASE = IO_PHYS + 0x01E20000, IOCFG_LT1_BASE = IO_PHYS + 0x01E30000, - SSUSB_SIF_BASE = IO_PHYS + 0x01E80300, IOCFG_RT_BASE = IO_PHYS + 0x01F20000, DSI0_BASE = IO_PHYS + 0x04016000, DISP_DVO0 = IO_PHYS + 0x04019000, diff --git a/src/soc/mediatek/mt8189/include/soc/usb.h b/src/soc/mediatek/mt8189/include/soc/usb.h new file mode 100644 index 0000000..eba4d62 --- /dev/null +++ b/src/soc/mediatek/mt8189/include/soc/usb.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file is created based on MT8189 Functional Specification + * Chapter number: 9.5 + */ + +#ifndef SOC_MEDIATEK_MT8189_INCLUDE_SOC_USB_H +#define SOC_MEDIATEK_MT8189_INCLUDE_SOC_USB_H + +#include <soc/usb_common.h> + +struct ssusb_sif_port { + struct sif_u2_phy_com u2phy; + u32 reserved0[64 * 5]; + struct sif_u3phyd u3phyd; + u32 reserved1[64]; + struct sif_u3phya u3phya; + struct sif_u3phya_da u3phya_da; + u32 reserved2[64 * 3]; +}; +check_member(ssusb_sif_port, u3phyd, 0x600); +check_member(ssusb_sif_port, u3phya, 0x800); +check_member(ssusb_sif_port, u3phya_da, 0x900); +check_member(ssusb_sif_port, reserved2, 0xa00); + +#define USB_PORT_NUMBER 1 + +#endif diff --git a/src/soc/mediatek/mt8189/usb.c b/src/soc/mediatek/mt8189/usb.c new file mode 100644 index 0000000..4dde3de --- /dev/null +++ b/src/soc/mediatek/mt8189/usb.c @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file is created based on MT8189 Functional Specification + * Chapter number: 9.5 + */ + +#include <device/mmio.h> +#include <gpio.h> +#include <soc/pll_common.h> +#include <soc/usb.h> + +void mtk_usb_prepare(void) +{ + /* enable P3 VBUS */ + gpio_output(GPIO(USB3_DRV_VBUS), 1); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/87021?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5f1b4b3eb178cb9a110b97a2763c8cff5cdf0ddd Gerrit-Change-Number: 87021 Gerrit-PatchSet: 3 Gerrit-Owner: Vince Liu <vince-wl.liu(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Liu Liu <ot_liu.liu(a)mediatek.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

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[XS] Change in coreboot[main]: mb/google/skywalker: Initialize flash controller in bootblock
by Yidi Lin (Code Review) 04 Apr '25

04 Apr '25

Yidi Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86998?usp=email ) Change subject: mb/google/skywalker: Initialize flash controller in bootblock ...................................................................... mb/google/skywalker: Initialize flash controller in bootblock Initialize SPI NOR Flash Controller (SNFC) in the bootblock to enable CBFS and execute other stages such as verstage, romstage, ramstage, etc. BUG=b:379008996 BRANCH=none TEST=Read NOR flash data successfully. Signed-off-by: Noah Shen <noah.shen(a)mediatek.corp-partner.google.com> Change-Id: Icf4af32dd9d8c704fd7246adda94dfa3350bb672 Reviewed-on: https://review.coreboot.org/c/coreboot/+/86998 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yidi Lin <yidilin(a)google.com> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- M src/mainboard/google/skywalker/Kconfig M src/mainboard/google/skywalker/bootblock.c 2 files changed, 6 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Yidi Lin: Looks good to me, approved Yu-Ping Wu: Looks good to me, approved diff --git a/src/mainboard/google/skywalker/Kconfig b/src/mainboard/google/skywalker/Kconfig index a3bed90..b3da548 100644 --- a/src/mainboard/google/skywalker/Kconfig +++ b/src/mainboard/google/skywalker/Kconfig @@ -27,4 +27,8 @@ config MAINBOARD_PART_NUMBER string default "Skywalker" if BOARD_GOOGLE_SKYWALKER + +config BOOT_DEVICE_SPI_FLASH_BUS + int + default 7 endif diff --git a/src/mainboard/google/skywalker/bootblock.c b/src/mainboard/google/skywalker/bootblock.c index af9934e..1062d9b 100644 --- a/src/mainboard/google/skywalker/bootblock.c +++ b/src/mainboard/google/skywalker/bootblock.c @@ -1,8 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only OR MIT */ #include <bootblock_common.h> +#include <soc/spi.h> void bootblock_mainboard_init(void) { - /* TODO: add mainboard init for bootblock */ + mtk_snfc_init(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/86998?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icf4af32dd9d8c704fd7246adda94dfa3350bb672 Gerrit-Change-Number: 86998 Gerrit-PatchSet: 4 Gerrit-Owner: Vince Liu <vince-wl.liu(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

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[S] Change in coreboot[main]: soc/mediatek/mt8189: Add NOR-Flash support
by Yidi Lin (Code Review) 04 Apr '25

04 Apr '25

Yidi Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86997?usp=email ) Change subject: soc/mediatek/mt8189: Add NOR-Flash support ...................................................................... soc/mediatek/mt8189: Add NOR-Flash support Add NOR-Flash drivers for flash read/write. BUG=b:379008996 BRANCH=none TEST=Read NOR flash data successfully. Signed-off-by: Noah Shen <noah.shen(a)mediatek.corp-partner.google.com> Change-Id: I3a5b7682e4093f9eddf825bc57267b0180cf8b3c Reviewed-on: https://review.coreboot.org/c/coreboot/+/86997 Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Reviewed-by: Yidi Lin <yidilin(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/mediatek/mt8189/Kconfig M src/soc/mediatek/mt8189/Makefile.mk M src/soc/mediatek/mt8189/include/soc/spi.h M src/soc/mediatek/mt8189/spi.c 4 files changed, 24 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved Yidi Lin: Looks good to me, approved diff --git a/src/soc/mediatek/mt8189/Kconfig b/src/soc/mediatek/mt8189/Kconfig index d0395c2..512ae54 100644 --- a/src/soc/mediatek/mt8189/Kconfig +++ b/src/soc/mediatek/mt8189/Kconfig @@ -9,6 +9,7 @@ select ARCH_RAMSTAGE_ARMV8_64 select HAVE_UART_SPECIAL select SOC_MEDIATEK_COMMON + select FLASH_DUAL_IO_READ select ARM64_USE_ARCH_TIMER if SOC_MEDIATEK_MT8189 diff --git a/src/soc/mediatek/mt8189/Makefile.mk b/src/soc/mediatek/mt8189/Makefile.mk index a121413..00489c0 100644 --- a/src/soc/mediatek/mt8189/Makefile.mk +++ b/src/soc/mediatek/mt8189/Makefile.mk @@ -2,6 +2,7 @@ ifeq ($(CONFIG_SOC_MEDIATEK_MT8189),y) +all-y += ../common/flash_controller.c all-y += ../common/gpio.c ../common/gpio_op.c gpio.c all-$(CONFIG_SPI_FLASH) += spi.c all-y += ../common/timer_prepare.c timer.c diff --git a/src/soc/mediatek/mt8189/include/soc/spi.h b/src/soc/mediatek/mt8189/include/soc/spi.h index 8c66e4a..01e866b 100644 --- a/src/soc/mediatek/mt8189/include/soc/spi.h +++ b/src/soc/mediatek/mt8189/include/soc/spi.h @@ -8,6 +8,7 @@ #ifndef __SOC_MEDIATEK_MT8189_INCLUDE_SOC_SPI_H__ #define __SOC_MEDIATEK_MT8189_INCLUDE_SOC_SPI_H__ -#include <spi-generic.h> +/* Initialize SPI NOR Flash Controller */ +void mtk_snfc_init(void); -#endif /* __SOC_MEDIATEK_MT8189_INCLUDE_SOC_SPI_H__ */ +#endif diff --git a/src/soc/mediatek/mt8189/spi.c b/src/soc/mediatek/mt8189/spi.c index da40fc5..410b53e 100644 --- a/src/soc/mediatek/mt8189/spi.c +++ b/src/soc/mediatek/mt8189/spi.c @@ -5,17 +5,34 @@ * Chapter number: 9.17 */ -#include <device/mmio.h> -#include <soc/addressmap.h> +#include <gpio.h> +#include <soc/flash_controller_common.h> #include <soc/spi.h> +#include <spi_flash.h> + +static const struct pad_func nor_pinmux[4] = { + PAD_FUNC(SPINOR_CK, SPINOR_CK, GPIO_PULL_DOWN), + PAD_FUNC(SPINOR_CS, SPINOR_CS, GPIO_PULL_UP), + PAD_FUNC(SPINOR_IO0, SPINOR_IO0, GPIO_PULL_DOWN), + PAD_FUNC(SPINOR_IO1, SPINOR_IO1, GPIO_PULL_DOWN), +}; + +void mtk_snfc_init(void) +{ + for (size_t i = 0; i < ARRAY_SIZE(nor_pinmux); i++) + mtk_snfc_init_pad_func(&nor_pinmux[i], GPIO_DRV_8_MA); +} static const struct spi_ctrlr spi_flash_ctrlr = { .max_xfer_size = 65535, + .flash_probe = mtk_spi_flash_probe, }; const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { { .ctrlr = &spi_flash_ctrlr, + .bus_start = CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, + .bus_end = CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, }, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/86997?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3a5b7682e4093f9eddf825bc57267b0180cf8b3c Gerrit-Change-Number: 86997 Gerrit-PatchSet: 3 Gerrit-Owner: Vince Liu <vince-wl.liu(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in coreboot[main]: mb/starlabs/starbook/mtl: Reconfigure PCH Strap GPIOs
by Matt DeVillier (Code Review) 04 Apr '25

04 Apr '25

Attention is currently required from: Sean Rhodes. Matt DeVillier has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/87125?usp=email ) Change subject: mb/starlabs/starbook/mtl: Reconfigure PCH Strap GPIOs ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/87125?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I53415716364222de713b3bf967419e5a45322e69 Gerrit-Change-Number: 87125 Gerrit-PatchSet: 4 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Comment-Date: Fri, 04 Apr 2025 14:41:15 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: mb/starlabs/starbook/mtl: Reconfigure PCH Strap GPIOs
by Sean Rhodes (Code Review) 04 Apr '25

04 Apr '25

Attention is currently required from: Matt DeVillier. Hello Matt DeVillier, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/87125?usp=email to look at the new patch set (#4). Change subject: mb/starlabs/starbook/mtl: Reconfigure PCH Strap GPIOs ...................................................................... mb/starlabs/starbook/mtl: Reconfigure PCH Strap GPIOs Configure all strap GPIOs as outputs, rather than some being not connected. This doesn't change anything, but is more explicit. Set these all to sample on RSMRST. Change-Id: I53415716364222de713b3bf967419e5a45322e69 Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> --- M src/mainboard/starlabs/starbook/variants/mtl/gpio.c 1 file changed, 11 insertions(+), 43 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/87125/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/87125?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I53415716364222de713b3bf967419e5a45322e69 Gerrit-Change-Number: 87125 Gerrit-PatchSet: 4 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com>

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[M] Change in coreboot[main]: mb/starlabs/starbook/mtl: Reconfigure PCH Strap GPIOs
by Sean Rhodes (Code Review) 04 Apr '25

04 Apr '25

Attention is currently required from: Matt DeVillier. Hello Matt DeVillier, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/87125?usp=email to look at the new patch set (#3). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: mb/starlabs/starbook/mtl: Reconfigure PCH Strap GPIOs ...................................................................... mb/starlabs/starbook/mtl: Reconfigure PCH Strap GPIOs Configure all strap GPIOs as outputs, rather than some being not connected. This doesn't change anything, but is more explicit. Set these all to sample on RSMRST. Change-Id: I53415716364222de713b3bf967419e5a45322e69 Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> --- M src/mainboard/starlabs/starbook/variants/mtl/gpio.c 1 file changed, 11 insertions(+), 43 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/87125/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/87125?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I53415716364222de713b3bf967419e5a45322e69 Gerrit-Change-Number: 87125 Gerrit-PatchSet: 3 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com>

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[S] Change in coreboot[main]: ec/google/chromeec: Add Kconfig for ChromeEC SMBIOS APIs
by Kapil Porwal (Code Review) 04 Apr '25

04 Apr '25

Attention is currently required from: Aamir Bohra, Boris Mittelberg, Caveh Jalali, Dinesh Gehlot, Eran Mitrani, Eric Lai, Jakub "Kuba" Czapiga, Jason Nien, Jayvik Desai, Julius Werner, Martin Roth, Nick Vaccaro, Pranava Y N, Tarun, Yu-Ping Wu. Kapil Porwal has posted comments on this change by Aamir Bohra. ( https://review.coreboot.org/c/coreboot/+/86993?usp=email ) Change subject: ec/google/chromeec: Add Kconfig for ChromeEC SMBIOS APIs ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86993?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I665a3276aa6dc01571657359d17f292efc601d63 Gerrit-Change-Number: 86993 Gerrit-PatchSet: 4 Gerrit-Owner: Aamir Bohra <aamirbohra(a)google.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jakub "Kuba" Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Jakub "Kuba" Czapiga <czapiga(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Aamir Bohra <aamirbohra(a)google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Attention: Boris Mittelberg <bmbm(a)google.com> Gerrit-Comment-Date: Fri, 04 Apr 2025 13:40:37 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: mb/starlabs/starfighter: Remove comments for disconnected GPIOs
by Matt DeVillier (Code Review) 04 Apr '25

04 Apr '25

Attention is currently required from: Sean Rhodes. Matt DeVillier has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/87165?usp=email ) Change subject: mb/starlabs/starfighter: Remove comments for disconnected GPIOs ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/87165?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia609053b61937a2da01e99b13adb4b964f3ae2ad Gerrit-Change-Number: 87165 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Comment-Date: Fri, 04 Apr 2025 13:36:37 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: mb/starlabs/starfighter: Disconnect unused GPIOs
by Matt DeVillier (Code Review) 04 Apr '25

04 Apr '25

Attention is currently required from: Sean Rhodes. Matt DeVillier has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/87164?usp=email ) Change subject: mb/starlabs/starfighter: Disconnect unused GPIOs ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/87164?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4e58a0e7545167db2c4034499bb99d3bfffc2277 Gerrit-Change-Number: 87164 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Comment-Date: Fri, 04 Apr 2025 13:36:33 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: mb/starlabs/{starbook/adl_n,starlite_adl}: Add missing config for TBT...
by Matt DeVillier (Code Review) 04 Apr '25

04 Apr '25

Attention is currently required from: Sean Rhodes. Matt DeVillier has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/87163?usp=email ) Change subject: mb/starlabs/{starbook/adl_n,starlite_adl}: Add missing config for TBT LSX 2 ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/87163?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id7cf723e354a98a760b9535309d1d9a8189d21ad Gerrit-Change-Number: 87163 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Comment-Date: Fri, 04 Apr 2025 13:36:26 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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