coreboot-gerrit April 2025

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[M] Change in coreboot[main]: mb/starlabs/starbook/*: Tidy GPIO comments for debug connector
by Sean Rhodes (Code Review) 03 Apr '25

03 Apr '25

Sean Rhodes has submitted this change. ( https://review.coreboot.org/c/coreboot/+/87098?usp=email ) Change subject: mb/starlabs/starbook/*: Tidy GPIO comments for debug connector ...................................................................... mb/starlabs/starbook/*: Tidy GPIO comments for debug connector This is a non-functional change, and only makes the GPIOs easier to read. Change-Id: I5e271508fcd99c01f7de4e5dad7a1941ba1968ec Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87098 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c M src/mainboard/starlabs/starbook/variants/adl/gpio.c M src/mainboard/starlabs/starbook/variants/cml/gpio.c M src/mainboard/starlabs/starbook/variants/kbl/gpio.c M src/mainboard/starlabs/starbook/variants/mtl/gpio.c M src/mainboard/starlabs/starbook/variants/rpl/gpio.c M src/mainboard/starlabs/starbook/variants/tgl/gpio.c M src/mainboard/starlabs/starfighter/variants/rpl/gpio.c M src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c 9 files changed, 29 insertions(+), 36 deletions(-) Approvals: Matt DeVillier: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c b/src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c index 71b706d..d3fa51b 100644 --- a/src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c +++ b/src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c @@ -4,10 +4,9 @@ /* Early pad configuration in bootblock */ const struct pad_config early_gpio_table[] = { - /* H10: UART0 RXD Debug Connector */ - PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), - /* H11: UART0 TXD Debug Connector */ - PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), + /* Debug Connector */ + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), /* RXD */ + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), /* TXD */ }; const struct pad_config *variant_early_gpio_table(size_t *num) diff --git a/src/mainboard/starlabs/starbook/variants/adl/gpio.c b/src/mainboard/starlabs/starbook/variants/adl/gpio.c index 4cc9888..493ec7b 100644 --- a/src/mainboard/starlabs/starbook/variants/adl/gpio.c +++ b/src/mainboard/starlabs/starbook/variants/adl/gpio.c @@ -4,10 +4,9 @@ /* Early pad configuration in bootblock */ const struct pad_config early_gpio_table[] = { - /* H10: UART0 RXD Debug Connector */ - PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), - /* H11: UART0 TXD Debug Connector */ - PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), + /* Debug Connector */ + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), /* RXD */ + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), /* TXD */ }; const struct pad_config *variant_early_gpio_table(size_t *num) diff --git a/src/mainboard/starlabs/starbook/variants/cml/gpio.c b/src/mainboard/starlabs/starbook/variants/cml/gpio.c index e29cd81..3ef1506 100644 --- a/src/mainboard/starlabs/starbook/variants/cml/gpio.c +++ b/src/mainboard/starlabs/starbook/variants/cml/gpio.c @@ -9,10 +9,10 @@ /* Early pad configuration in bootblock */ const struct pad_config early_gpio_table[] = { - /* C20: UART2_RXD */ - PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), - /* C21: UART2_TXD */ - PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), + /* Debug Connector */ + PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* RXD */ + PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* TXD */ + /* E22: BRD_ID0 */ PAD_CFG_GPO(GPP_E22, 1, PLTRST), /* E23: BRD_ID1 */ diff --git a/src/mainboard/starlabs/starbook/variants/kbl/gpio.c b/src/mainboard/starlabs/starbook/variants/kbl/gpio.c index 9ab7414..ae01749 100644 --- a/src/mainboard/starlabs/starbook/variants/kbl/gpio.c +++ b/src/mainboard/starlabs/starbook/variants/kbl/gpio.c @@ -9,10 +9,9 @@ /* Early pad configuration in bootblock. */ const struct pad_config early_gpio_table[] = { - /* C20: UART2_RXD */ - PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), - /* C21: UART2_TXD */ - PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), + /* Debug Connector */ + PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* RXD */ + PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* TXD */ }; const struct pad_config *variant_early_gpio_table(size_t *num) diff --git a/src/mainboard/starlabs/starbook/variants/mtl/gpio.c b/src/mainboard/starlabs/starbook/variants/mtl/gpio.c index d1b915a..e7f66ff 100644 --- a/src/mainboard/starlabs/starbook/variants/mtl/gpio.c +++ b/src/mainboard/starlabs/starbook/variants/mtl/gpio.c @@ -4,10 +4,9 @@ /* Early pad configuration in bootblock */ const struct pad_config early_gpio_table[] = { - /* H08: UART0 RXD */ - PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1), - /* H09: UART0 TXD */ - PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1), + /* Debug Connector */ + PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1), /* RXD */ + PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1), /* TXD */ /* C00: SMB_CLK */ PAD_CFG_NF(GPP_C00, NONE, DEEP, NF1), diff --git a/src/mainboard/starlabs/starbook/variants/rpl/gpio.c b/src/mainboard/starlabs/starbook/variants/rpl/gpio.c index 542aa32..bae3564 100644 --- a/src/mainboard/starlabs/starbook/variants/rpl/gpio.c +++ b/src/mainboard/starlabs/starbook/variants/rpl/gpio.c @@ -4,10 +4,9 @@ /* Early pad configuration in bootblock */ const struct pad_config early_gpio_table[] = { - /* H10: UART0 RXD Debug Connector */ - PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), - /* H11: UART0 TXD Debug Connector */ - PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), + /* Debug Connector */ + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), /* RXD */ + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), /* TXD */ }; const struct pad_config *variant_early_gpio_table(size_t *num) diff --git a/src/mainboard/starlabs/starbook/variants/tgl/gpio.c b/src/mainboard/starlabs/starbook/variants/tgl/gpio.c index 2526f7f..7e30109 100644 --- a/src/mainboard/starlabs/starbook/variants/tgl/gpio.c +++ b/src/mainboard/starlabs/starbook/variants/tgl/gpio.c @@ -9,10 +9,9 @@ /* Early pad configuration in bootblock */ const struct pad_config early_gpio_table[] = { - /* C20: UART2_RXD_R */ - PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), - /* C21: UART2_TXD_R */ - PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), + /* Debug Connector */ + PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* RXD */ + PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* TXD */ }; const struct pad_config *variant_early_gpio_table(size_t *num) diff --git a/src/mainboard/starlabs/starfighter/variants/rpl/gpio.c b/src/mainboard/starlabs/starfighter/variants/rpl/gpio.c index bfd0674..6890c27 100644 --- a/src/mainboard/starlabs/starfighter/variants/rpl/gpio.c +++ b/src/mainboard/starlabs/starfighter/variants/rpl/gpio.c @@ -4,10 +4,10 @@ /* Early pad configuration in bootblock */ const struct pad_config early_gpio_table[] = { - /* H10: UART0 RXD Debug Connector */ - PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), - /* H11: UART0 TXD Debug Connector */ - PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), + /* Debug Connector */ + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), /* RXD */ + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), /* TXD */ + /* F12: Board ID 0 */ PAD_CFG_GPI_LOCK(GPP_F12, NONE, LOCK_CONFIG), /* F13: Board ID 1 */ diff --git a/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c b/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c index 67f9e40..8dea7a5 100644 --- a/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c +++ b/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c @@ -4,10 +4,9 @@ /* Early pad configuration in bootblock */ const struct pad_config early_gpio_table[] = { - /* H10: UART0 RXD Debug Connector */ - PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), - /* H11: UART0 TXD Debug Connector */ - PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), + /* Debug Connector */ + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), /* RXD */ + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), /* TXD */ }; const struct pad_config *variant_early_gpio_table(size_t *num) -- To view, visit https://review.coreboot.org/c/coreboot/+/87098?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5e271508fcd99c01f7de4e5dad7a1941ba1968ec Gerrit-Change-Number: 87098 Gerrit-PatchSet: 3 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: mb/starlabs/starlite_adl: Remove the VGPIO config
by Sean Rhodes (Code Review) 03 Apr '25

03 Apr '25

Sean Rhodes has submitted this change. ( https://review.coreboot.org/c/coreboot/+/87097?usp=email ) Change subject: mb/starlabs/starlite_adl: Remove the VGPIO config ...................................................................... mb/starlabs/starlite_adl: Remove the VGPIO config These aren't required, so remove the config and let FSP handle it. Change-Id: I143a779950773823746e838cf29209b6e3bb87ad Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87097 Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c 1 file changed, 0 insertions(+), 31 deletions(-) Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved diff --git a/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c b/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c index 8a0b804..67f9e40 100644 --- a/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c +++ b/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c @@ -448,37 +448,6 @@ PAD_NC(GPP_R6, NONE), /* R7: Not Connected */ PAD_NC(GPP_R7, NONE), - - /* CNV_BTEN */ - PAD_CFG_GPO(GPP_VGPIO_0, 1, DEEP), - /* CNV_BT_HOST_WAKEB */ - PAD_NC(GPP_VGPIO_4, NONE), - /* CNV_BT_IF_SELECT */ - PAD_CFG_GPO(GPP_VGPIO_5, 1, DEEP), - /* vCNV_BT_UART_TXD */ - PAD_NC(GPP_VGPIO_6, NONE), - /* vCNV_BT_UART_RXD */ - PAD_NC(GPP_VGPIO_7, NONE), - /* vCNV_BT_UART_CTS_B */ - PAD_NC(GPP_VGPIO_8, NONE), - /* vCNV_BT_UART_RTS_B */ - PAD_NC(GPP_VGPIO_9, NONE), - /* vUART0_TXD */ - PAD_NC(GPP_VGPIO_18, NONE), - /* vUART0_RXD */ - PAD_NC(GPP_VGPIO_19, NONE), - /* vUART0_CTS_B */ - PAD_NC(GPP_VGPIO_20, NONE), - /* vUART0_RTS_B */ - PAD_NC(GPP_VGPIO_21, NONE), - /* BT_I2S_BCLK */ - PAD_NC(GPP_VGPIO_30, NONE), - /* BT_I2S_SYNC */ - PAD_NC(GPP_VGPIO_31, NONE), - /* BT_I2S_SDO */ - PAD_NC(GPP_VGPIO_32, NONE), - /* BT_I2S_SDI */ - PAD_NC(GPP_VGPIO_33, NONE), }; const struct pad_config *variant_gpio_table(size_t *num) -- To view, visit https://review.coreboot.org/c/coreboot/+/87097?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I143a779950773823746e838cf29209b6e3bb87ad Gerrit-Change-Number: 87097 Gerrit-PatchSet: 3 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: mb/starlabs/starbook/adl_n: Set CNVi strap to disabled
by Sean Rhodes (Code Review) 03 Apr '25

03 Apr '25

Sean Rhodes has submitted this change. ( https://review.coreboot.org/c/coreboot/+/87084?usp=email ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/starlabs/starbook/adl_n: Set CNVi strap to disabled ...................................................................... mb/starlabs/starbook/adl_n: Set CNVi strap to disabled Set GPP_F2 to output high, to indicate that CNVi is disabled. Change-Id: I82f3ce699d5e823e1ce942acb7a0ba1bd548d9a0 Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87084 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/starlabs/starbook/variants/adl_n/gpio.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved diff --git a/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c b/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c index 9edd864..7d15cb9 100644 --- a/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c +++ b/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c @@ -86,7 +86,7 @@ PAD_CFG_GPO(GPP_C5, 0, RSMRST), /* eSPI [ Enabled / Disabled ] */ PAD_CFG_GPO(GPP_E6, 0, RSMRST), /* JTAG ODT [ Disabled / Enabled ] */ PAD_CFG_GPO(GPP_H1, 0, RSMRST), /* BFX Strap 2 Bit 3 [ Disabled / Enabled ] */ - PAD_CFG_GPO(GPP_F2, 0, RSMRST), /* M.2 CNVi [ Enabled / Disabled ] */ + PAD_CFG_GPO(GPP_F2, 1, RSMRST), /* M.2 CNVi [ Enabled / Disabled ] */ PAD_CFG_GPO(GPP_E19, 0, RSMRST), /* TBT LSX #0 [ 1.8V / 3.3V ] */ PAD_CFG_GPO(GPP_E21, 0, RSMRST), /* TBT LSX #1 [ 1.8V / 3.3V ] */ PAD_CFG_GPO(GPP_D12, 0, RSMRST), /* TBT LSX #3 [ 1.8V / 3.3V ] */ -- To view, visit https://review.coreboot.org/c/coreboot/+/87084?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I82f3ce699d5e823e1ce942acb7a0ba1bd548d9a0 Gerrit-Change-Number: 87084 Gerrit-PatchSet: 3 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: mb/starlabs/starbook/adl_n: Reconfigure PCH Strap GPIOs
by Sean Rhodes (Code Review) 03 Apr '25

03 Apr '25

Sean Rhodes has submitted this change. ( https://review.coreboot.org/c/coreboot/+/87083?usp=email ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/starlabs/starbook/adl_n: Reconfigure PCH Strap GPIOs ...................................................................... mb/starlabs/starbook/adl_n: Reconfigure PCH Strap GPIOs Configure all strap GPIOs as outputs, rather than some being not connected. This doesn't change anything, but is more explicit. Set these all to sample on RSMRST. Change-Id: I779b6bc486b68e8df50347540364901507a7102c Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87083 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/starlabs/starbook/variants/adl_n/gpio.c 1 file changed, 11 insertions(+), 11 deletions(-) Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved diff --git a/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c b/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c index 43f2213..9edd864 100644 --- a/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c +++ b/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c @@ -81,17 +81,17 @@ /* Config Straps [ Low / High ] */ PAD_CFG_GPO(GPP_B14, 0, RSMRST), /* Top Swap [ Disabled / Enabled ] */ - PAD_NC(GPP_B18, NONE), /* Reboot Support [ Enabled / Disabled ] */ - PAD_CFG_GPO(GPP_C2, 1, PLTRST), /* TLS Confidentiality [ Disabled / Enabled ] */ - PAD_CFG_GPO(GPP_C5, 0, PLTRST), /* eSPI [ Enabled / Disabled ] */ - PAD_CFG_GPO(GPP_E6, 0, DEEP), /* JTAG ODT [ Disabled / Enabled ] */ - PAD_CFG_GPO(GPP_H1, 0, DEEP), /* BFX Strap 2 Bit 3 [ Disabled / Enabled ] */ - PAD_NC(GPP_F2, NONE), /* M.2 CNVi [ Enabled / Disabled ] */ - PAD_NC(GPP_E19, NONE), /* TBT LSX #0 [ 1.8V / 3.3V ] */ - PAD_NC(GPP_E21, NONE), /* TBT LSX #1 [ 1.8V / 3.3V ] */ - PAD_NC(GPP_D12, NONE), /* TBT LSX #3 [ 1.8V / 3.3V ] */ - PAD_CFG_GPO(GPP_F7, 0, DEEP), /* MCRO LDO [ Disabled / Bypass ] */ - PAD_CFG_GPO(GPD7, 0, PWROK), /* RTC Clock Delay [ Disabled / 95ms ] */ + PAD_CFG_GPO(GPP_B18, 0, RSMRST), /* Reboot Support [ Enabled / Disabled ] */ + PAD_CFG_GPO(GPP_C2, 1, RSMRST), /* TLS Confidentiality [ Disabled / Enabled ] */ + PAD_CFG_GPO(GPP_C5, 0, RSMRST), /* eSPI [ Enabled / Disabled ] */ + PAD_CFG_GPO(GPP_E6, 0, RSMRST), /* JTAG ODT [ Disabled / Enabled ] */ + PAD_CFG_GPO(GPP_H1, 0, RSMRST), /* BFX Strap 2 Bit 3 [ Disabled / Enabled ] */ + PAD_CFG_GPO(GPP_F2, 0, RSMRST), /* M.2 CNVi [ Enabled / Disabled ] */ + PAD_CFG_GPO(GPP_E19, 0, RSMRST), /* TBT LSX #0 [ 1.8V / 3.3V ] */ + PAD_CFG_GPO(GPP_E21, 0, RSMRST), /* TBT LSX #1 [ 1.8V / 3.3V ] */ + PAD_CFG_GPO(GPP_D12, 0, RSMRST), /* TBT LSX #3 [ 1.8V / 3.3V ] */ + PAD_CFG_GPO(GPP_F7, 0, RSMRST), /* MCRO LDO [ Disabled / Bypass ] */ + PAD_CFG_GPO(GPD7, 0, RSMRST), /* RTC Clock Delay [ Disabled / 95ms ] */ PAD_NC(GPD2, NONE), PAD_NC(GPD6, NONE), -- To view, visit https://review.coreboot.org/c/coreboot/+/87083?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I779b6bc486b68e8df50347540364901507a7102c Gerrit-Change-Number: 87083 Gerrit-PatchSet: 4 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in coreboot[main]: mb/starlabs/starbook/adl_n: Remove comments for GPIOs that aren't con...
by Sean Rhodes (Code Review) 03 Apr '25

03 Apr '25

Sean Rhodes has submitted this change. ( https://review.coreboot.org/c/coreboot/+/87082?usp=email ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/starlabs/starbook/adl_n: Remove comments for GPIOs that aren't connected ...................................................................... mb/starlabs/starbook/adl_n: Remove comments for GPIOs that aren't connected This is a non-functional change; it just makes it easier to read. Change-Id: Ib3f87c6e3e83d57c4e6969c3aac7cae02d750a5c Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87082 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/starlabs/starbook/variants/adl_n/gpio.c 1 file changed, 0 insertions(+), 149 deletions(-) Approvals: Matt DeVillier: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c b/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c index 19b3cc8..43f2213 100644 --- a/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c +++ b/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c @@ -99,312 +99,163 @@ PAD_NC(GPD10, NONE), PAD_NC(GPD11, NONE), - /* A5: Not Connected */ PAD_NC(GPP_A5, NONE), - /* A6: Not Connected */ PAD_NC(GPP_A6, NONE), - /* A7: Embedded Controller SCI */ PAD_NC(GPP_A7, NONE), - /* A8: Not Connected */ PAD_NC(GPP_A8, NONE), - /* A11: Not Connected */ PAD_NC(GPP_A11, NONE), - /* A12: Not Connected */ PAD_NC(GPP_A12, NONE), - /* A14: Test Point 45 */ PAD_NC(GPP_A14, NONE), - /* A15: Test Point 52 */ PAD_NC(GPP_A15, NONE), - /* A16: USB OverCurrent 3 */ PAD_NC(GPP_A16, NONE), - /* A17: Not Connected */ PAD_NC(GPP_A17, NONE), - /* A20: Test Point 44 */ PAD_NC(GPP_A20, NONE), - /* A21: Fingerprint Reader Interrupt */ PAD_NC(GPP_A21, NONE), - /* A22: Fingerprint Reader Reset */ PAD_NC(GPP_A22, NONE), - /* A23: Not Connected */ PAD_NC(GPP_A23, NONE), - - /* B3: Not Connected */ PAD_NC(GPP_B3, NONE), - /* B4: Not Connected */ PAD_NC(GPP_B4, NONE), - /* B5: I2C 2 SDA Touch Panel SDA */ PAD_NC(GPP_B5, NONE), - /* B6: I2C 2 SCL Touch Panel Clock */ PAD_NC(GPP_B6, NONE), - /* B9: Not Connected */ PAD_NC(GPP_B9, NONE), - /* B10: Not Connected */ PAD_NC(GPP_B10, NONE), - /* B11: Not Connected */ PAD_NC(GPP_B11, NONE), - /* B12: PM SLP S0 */ PAD_NC(GPP_B12, NONE), - /* B15: Not Connected */ PAD_NC(GPP_B15, NONE), - /* B16: Not Connected */ PAD_NC(GPP_B16, NONE), - /* B17: Not Connected */ PAD_NC(GPP_B17, NONE), - /* B19: Not Connected */ PAD_NC(GPP_B19, NONE), - /* B20: Not Connected */ PAD_NC(GPP_B20, NONE), - /* B21: Not Connected */ PAD_NC(GPP_B21, NONE), - /* B22: Not Connected */ PAD_NC(GPP_B22, NONE), - /* B23: Not used MiPi Camera */ PAD_NC(GPP_B23, NONE), - /* B24: Not Connected */ PAD_NC(GPP_B24, NONE), - /* B25: Not Connected */ PAD_NC(GPP_B25, NONE), - /* C3: SML 0 Clock */ PAD_NC(GPP_C3, NONE), - /* C4: SML 0 Data */ PAD_NC(GPP_C4, NONE), - /* C6: SML 1 Clock */ PAD_NC(GPP_C6, NONE), - /* C7: SML 1 Data */ PAD_NC(GPP_C7, NONE), - /* C8: Not Connected */ PAD_NC(GPP_C8, NONE), - /* C9: Not Connected */ PAD_NC(GPP_C9, NONE), - /* C10: Not Connected */ PAD_NC(GPP_C10, NONE), - /* C11: Not Connected */ PAD_NC(GPP_C11, NONE), - /* C12: Not Connected */ PAD_NC(GPP_C12, NONE), - /* C13: Not Connected */ PAD_NC(GPP_C13, NONE), - /* C14: Not Connected */ PAD_NC(GPP_C14, NONE), - /* C15: Not Connected */ PAD_NC(GPP_C15, NONE), - /* C16: Not Connected */ PAD_NC(GPP_C16, NONE), - /* C17: Not Connected */ PAD_NC(GPP_C17, NONE), - /* C18: Not Connected */ PAD_NC(GPP_C18, NONE), - /* C19: Not Connected */ PAD_NC(GPP_C19, NONE), - /* C20: Not Connected */ PAD_NC(GPP_C20, NONE), - /* C21: Not Connected */ PAD_NC(GPP_C21, NONE), - /* C22: Not Connected */ PAD_NC(GPP_C22, NONE), - /* C23: Not Connected */ PAD_NC(GPP_C23, NONE), - /* D0: Not used Audio ID 0 */ PAD_NC(GPP_D0, NONE), - /* D1: Not used Audio ID 1 */ PAD_NC(GPP_D1, NONE), - /* D2: Not used Audio ID 2 */ PAD_NC(GPP_D2, NONE), - /* D3: Not Connected */ PAD_NC(GPP_D3, NONE), - /* D4: Not Connected */ PAD_NC(GPP_D4, NONE), - /* D7: Clock Request 2 */ PAD_NC(GPP_D7, NONE), - /* D8: Clock Request 3 */ PAD_NC(GPP_D8, NONE), - /* D9: GSPI 2 FPS */ PAD_NC(GPP_D9, NONE), - /* D10: GSPI 2 Clock */ PAD_NC(GPP_D10, NONE), - /* D11: GSPI 2 MISO FPS */ PAD_NC(GPP_D11, NONE), - /* D13: Wireless LAN Wake */ PAD_NC(GPP_D13, NONE), - /* D14: CPU M.2 SSD Power Enable */ PAD_NC(GPP_D14, NONE), - /* D15: Not Connected */ PAD_NC(GPP_D15, NONE), - /* D17: Not used Fingerprint ID */ PAD_NC(GPP_D17, NONE), - /* D18: Not Connected */ PAD_NC(GPP_D18, NONE), - /* D19: Test Point 21 */ PAD_NC(GPP_D19, NONE), - /* E0: SATA x PCIe */ PAD_NC(GPP_E0, NONE), - /* E1: Not used Accelerometer Interrupt */ PAD_NC(GPP_E1, NONE), - /* E2: Not Connected */ PAD_NC(GPP_E2, NONE), - /* E4: Test Point 14 */ PAD_NC(GPP_E4, NONE), - /* E5: Not Connected */ PAD_NC(GPP_E5, NONE), - /* E7: Embedded Controller SMI */ PAD_NC(GPP_E7, NONE), - /* E9: USB OverCurrent 0 */ PAD_NC(GPP_E9, NONE), - /* E10: PWD Amplifier Input */ PAD_NC(GPP_E10, NONE), - /* E13: Not connected */ PAD_NC(GPP_E13, NONE), - /* E15: Not Connected */ PAD_NC(GPP_E15, NONE), - /* E16: Not Connected */ PAD_NC(GPP_E16, NONE), - /* E17: Not Connected */ PAD_NC(GPP_E17, NONE), - /* E18: Not Connected */ PAD_NC(GPP_E18, NONE), - /* E20: Not Connected */ PAD_NC(GPP_E20, NONE), - /* E22: Not Connected */ PAD_NC(GPP_E22, NONE), - /* E23: Not Connected */ PAD_NC(GPP_E23, NONE), - /* F0: CNV BRI Data */ PAD_NC(GPP_F0, NONE), - /* F1: CNV BRI Response */ PAD_NC(GPP_F1, NONE), - /* F3: CNV RGI Response */ PAD_NC(GPP_F3, NONE), - /* F4: CNV RF Reset */ PAD_NC(GPP_F4, NONE), - /* F5: Not used MODEM_CLKREQ */ PAD_NC(GPP_F5, NONE), - /* F6: CNV PA Blanking */ PAD_NC(GPP_F6, NONE), - /* F8: Not Connected */ PAD_NC(GPP_F8, NONE), - /* F9: */ PAD_NC(GPP_F9, NONE), - /* F10: Not Connected */ PAD_NC(GPP_F10, NONE), - /* F11: TPM ID */ PAD_NC(GPP_F11, NONE), - /* F12: Not Connected */ PAD_NC(GPP_F12, NONE), - /* F13: Not Connected */ PAD_NC(GPP_F13, NONE), - /* F14: Not Connected */ PAD_NC(GPP_F14, NONE), - /* F15: Not used */ PAD_NC(GPP_F15, NONE), - /* F16: Not Connected */ PAD_NC(GPP_F16, NONE), - /* F17: Not used */ PAD_NC(GPP_F17, NONE), - /* F18: Not used */ PAD_NC(GPP_F18, NONE), - /* F19: Not Connected */ PAD_NC(GPP_F19, NONE), - /* F20: Not Connected */ PAD_NC(GPP_F20, NONE), - /* F21: Not Connected */ PAD_NC(GPP_F21, NONE), - /* F22: Not Connected */ PAD_NC(GPP_F22, NONE), - /* F23: Not Connected */ PAD_NC(GPP_F23, NONE), - /* H3: Not Connected */ PAD_NC(GPP_H3, NONE), - /* H4: I2C 0 SDA Touchpad */ PAD_NC(GPP_H4, NONE), - /* H5: I2C 0 SCL Touchpad */ PAD_NC(GPP_H5, NONE), - /* H6: Not Connected */ PAD_NC(GPP_H6, NONE), - /* H7: Not Connected */ PAD_NC(GPP_H7, NONE), - /* H8: I2C 4 SDA GSensor */ PAD_NC(GPP_H8, NONE), - /* H9: I2C 4 SDL GSensor */ PAD_NC(GPP_H9, NONE), - /* H12: Not Connected */ PAD_NC(GPP_H12, NONE), - /* H13: PCH M.2 SSD Device Sleep */ PAD_NC(GPP_H13, NONE), - /* H14: Not Connected */ PAD_NC(GPP_H14, NONE), - /* H16: Not Connected */ PAD_NC(GPP_H16, NONE), - /* H19: Clock Request 4 CPU M.2 SSD */ PAD_NC(GPP_H19, NONE), - /* H20: Not Connected */ PAD_NC(GPP_H20, NONE), - /* H21: Not Connected */ PAD_NC(GPP_H21, NONE), - /* H22: Not Connected */ PAD_NC(GPP_H22, NONE), - /* H23: Clock Request 5 */ PAD_NC(GPP_H23, NONE), - /* S0: Not Connected */ PAD_NC(GPP_S0, NONE), - /* S1: Not Connected */ PAD_NC(GPP_S1, NONE), - /* S2: DMIC Clock */ PAD_NC(GPP_S2, NONE), - /* S3: DMIC Data */ PAD_NC(GPP_S3, NONE), - /* S4: Not Connected */ PAD_NC(GPP_S4, NONE), - /* S5: Not Connected */ PAD_NC(GPP_S5, NONE), - /* S6: Not Connected */ PAD_NC(GPP_S6, NONE), - /* S7: Not Connected */ PAD_NC(GPP_S7, NONE), - /* T0: Not Connected */ PAD_NC(GPP_T0, NONE), - /* T1: Not Connected */ PAD_NC(GPP_T1, NONE), - /* T2: Not Connected */ PAD_NC(GPP_T2, NONE), - /* T3: Not Connected */ PAD_NC(GPP_T3, NONE), - /* T4: Not Connected */ PAD_NC(GPP_T4, NONE), - /* T5: Not Connected */ PAD_NC(GPP_T5, NONE), - /* T6: Not Connected */ PAD_NC(GPP_T6, NONE), - /* T7: Not Connected */ PAD_NC(GPP_T7, NONE), - /* T8: Not Connected */ PAD_NC(GPP_T8, NONE), - /* T9: Not Connected */ PAD_NC(GPP_T9, NONE), - /* T10: Not Connected */ PAD_NC(GPP_T10, NONE), - /* T11: Not Connected */ PAD_NC(GPP_T11, NONE), - /* T12: Not Connected */ PAD_NC(GPP_T12, NONE), - /* T13: Not Connected */ PAD_NC(GPP_T13, NONE), - /* T14: Not Connected */ PAD_NC(GPP_T14, NONE), - /* T15: Not Connected */ PAD_NC(GPP_T15, NONE), PAD_NC(GPP_R5, NONE), - /* R6: Not Connected */ PAD_NC(GPP_R6, NONE), - /* R7: Not Connected */ PAD_NC(GPP_R7, NONE), }; -- To view, visit https://review.coreboot.org/c/coreboot/+/87082?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib3f87c6e3e83d57c4e6969c3aac7cae02d750a5c Gerrit-Change-Number: 87082 Gerrit-PatchSet: 3 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: mb/starlabs/starbook/adl_n: Disconnect GPP_F10
by Sean Rhodes (Code Review) 03 Apr '25

03 Apr '25

Sean Rhodes has submitted this change. ( https://review.coreboot.org/c/coreboot/+/87081?usp=email ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/starlabs/starbook/adl_n: Disconnect GPP_F10 ...................................................................... mb/starlabs/starbook/adl_n: Disconnect GPP_F10 This GPIO is not connected so configure it accordingly. Change-Id: Ie85d69e0a2a423261038688c176b32abe7bd8134 Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87081 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/starlabs/starbook/variants/adl_n/gpio.c 1 file changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved diff --git a/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c b/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c index 680126d..19b3cc8 100644 --- a/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c +++ b/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c @@ -289,8 +289,8 @@ PAD_NC(GPP_F8, NONE), /* F9: */ PAD_NC(GPP_F9, NONE), - /* F10: Weak Internal PD 20K */ - PAD_CFG_GPO(GPP_F10, 0, DEEP), + /* F10: Not Connected */ + PAD_NC(GPP_F10, NONE), /* F11: TPM ID */ PAD_NC(GPP_F11, NONE), /* F12: Not Connected */ -- To view, visit https://review.coreboot.org/c/coreboot/+/87081?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie85d69e0a2a423261038688c176b32abe7bd8134 Gerrit-Change-Number: 87081 Gerrit-PatchSet: 3 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in coreboot[main]: mb/starlabs/starbook/adl_n: Tidy GPIO comments for the PCH Straps
by Sean Rhodes (Code Review) 03 Apr '25

03 Apr '25

Sean Rhodes has submitted this change. ( https://review.coreboot.org/c/coreboot/+/87080?usp=email ) Change subject: mb/starlabs/starbook/adl_n: Tidy GPIO comments for the PCH Straps ...................................................................... mb/starlabs/starbook/adl_n: Tidy GPIO comments for the PCH Straps This is a non-functional change, and only makes the GPIOs easier to read. Change-Id: I658cd6ddf2d418da0e36a8e1969041a696a10d87 Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87080 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/starlabs/starbook/variants/adl_n/gpio.c 1 file changed, 14 insertions(+), 36 deletions(-) Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved diff --git a/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c b/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c index e7a68c2..680126d 100644 --- a/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c +++ b/src/mainboard/starlabs/starbook/variants/adl_n/gpio.c @@ -79,10 +79,22 @@ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* Data */ PAD_CFG_GPO(GPP_E8, 1, DEEP), /* DRAM Sleep */ + /* Config Straps [ Low / High ] */ + PAD_CFG_GPO(GPP_B14, 0, RSMRST), /* Top Swap [ Disabled / Enabled ] */ + PAD_NC(GPP_B18, NONE), /* Reboot Support [ Enabled / Disabled ] */ + PAD_CFG_GPO(GPP_C2, 1, PLTRST), /* TLS Confidentiality [ Disabled / Enabled ] */ + PAD_CFG_GPO(GPP_C5, 0, PLTRST), /* eSPI [ Enabled / Disabled ] */ + PAD_CFG_GPO(GPP_E6, 0, DEEP), /* JTAG ODT [ Disabled / Enabled ] */ + PAD_CFG_GPO(GPP_H1, 0, DEEP), /* BFX Strap 2 Bit 3 [ Disabled / Enabled ] */ + PAD_NC(GPP_F2, NONE), /* M.2 CNVi [ Enabled / Disabled ] */ + PAD_NC(GPP_E19, NONE), /* TBT LSX #0 [ 1.8V / 3.3V ] */ + PAD_NC(GPP_E21, NONE), /* TBT LSX #1 [ 1.8V / 3.3V ] */ + PAD_NC(GPP_D12, NONE), /* TBT LSX #3 [ 1.8V / 3.3V ] */ + PAD_CFG_GPO(GPP_F7, 0, DEEP), /* MCRO LDO [ Disabled / Bypass ] */ + PAD_CFG_GPO(GPD7, 0, PWROK), /* RTC Clock Delay [ Disabled / 95ms ] */ + PAD_NC(GPD2, NONE), PAD_NC(GPD6, NONE), - /* GPD7: Power Adapter Disable */ - PAD_CFG_GPO(GPD7, 0, PWROK), PAD_NC(GPD9, NONE), PAD_NC(GPD10, NONE), PAD_NC(GPD11, NONE), @@ -133,20 +145,12 @@ PAD_NC(GPP_B11, NONE), /* B12: PM SLP S0 */ PAD_NC(GPP_B12, NONE), - /* B14: Top Swap Override Weak Internal PD 20K - High: Enabled - Low: Disabled */ - PAD_CFG_GPO(GPP_B14, 0, PLTRST), /* B15: Not Connected */ PAD_NC(GPP_B15, NONE), /* B16: Not Connected */ PAD_NC(GPP_B16, NONE), /* B17: Not Connected */ PAD_NC(GPP_B17, NONE), - /* B18: Reboot Support Weak Internal PD 20K - High: Disabled - Low: Enabled */ - PAD_NC(GPP_B18, NONE), /* B19: Not Connected */ PAD_NC(GPP_B19, NONE), /* B20: Not Connected */ @@ -162,18 +166,10 @@ /* B25: Not Connected */ PAD_NC(GPP_B25, NONE), - /* C2: TLS Confidentiality Weak Internal PD 20K - Low: Disabled - High: Enabled */ - PAD_CFG_GPO(GPP_C2, 1, PLTRST), /* C3: SML 0 Clock */ PAD_NC(GPP_C3, NONE), /* C4: SML 0 Data */ PAD_NC(GPP_C4, NONE), - /* C5: Boot Strap Weak Internal PD 20K - Low: ESPI - High: Disabled */ - PAD_CFG_GPO(GPP_C5, 0, PLTRST), /* C6: SML 1 Clock */ PAD_NC(GPP_C6, NONE), /* C7: SML 1 Data */ @@ -231,8 +227,6 @@ PAD_NC(GPP_D10, NONE), /* D11: GSPI 2 MISO FPS */ PAD_NC(GPP_D11, NONE), - /* D12: GSPI 2 MOSI FPS */ - PAD_NC(GPP_D12, NONE), /* D13: Wireless LAN Wake */ PAD_NC(GPP_D13, NONE), /* D14: CPU M.2 SSD Power Enable */ @@ -256,10 +250,6 @@ PAD_NC(GPP_E4, NONE), /* E5: Not Connected */ PAD_NC(GPP_E5, NONE), - /* E6: JTAG ODT No internal PD - Low: Disabled - High: Enabled */ - PAD_CFG_GPO(GPP_E6, 0, DEEP), /* E7: Embedded Controller SMI */ PAD_NC(GPP_E7, NONE), /* E9: USB OverCurrent 0 */ @@ -276,12 +266,8 @@ PAD_NC(GPP_E17, NONE), /* E18: Not Connected */ PAD_NC(GPP_E18, NONE), - /* E19: Thunderbolt LSX RXD */ - PAD_NC(GPP_E19, NONE), /* E20: Not Connected */ PAD_NC(GPP_E20, NONE), - /* E21: Not Connected */ - PAD_NC(GPP_E21, NONE), /* E22: Not Connected */ PAD_NC(GPP_E22, NONE), /* E23: Not Connected */ @@ -291,8 +277,6 @@ PAD_NC(GPP_F0, NONE), /* F1: CNV BRI Response */ PAD_NC(GPP_F1, NONE), - /* F2: CNV RGI Data */ - PAD_NC(GPP_F2, NONE), /* F3: CNV RGI Response */ PAD_NC(GPP_F3, NONE), /* F4: CNV RF Reset */ @@ -301,10 +285,6 @@ PAD_NC(GPP_F5, NONE), /* F6: CNV PA Blanking */ PAD_NC(GPP_F6, NONE), - /* F7: TBT LSX VCCIO Weak Internal PD 20K - Low: 1.8V - High: 3.3V */ - PAD_CFG_GPO(GPP_F7, 0, DEEP), /* F8: Not Connected */ PAD_NC(GPP_F8, NONE), /* F9: */ @@ -338,8 +318,6 @@ /* F23: Not Connected */ PAD_NC(GPP_F23, NONE), - /* H1: BFX Strap 2 Bit 3 Weak Internal PD 20K */ - PAD_CFG_GPO(GPP_H1, 0, DEEP), /* H3: Not Connected */ PAD_NC(GPP_H3, NONE), /* H4: I2C 0 SDA Touchpad */ -- To view, visit https://review.coreboot.org/c/coreboot/+/87080?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I658cd6ddf2d418da0e36a8e1969041a696a10d87 Gerrit-Change-Number: 87080 Gerrit-PatchSet: 4 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: drivers/intel/touch: Conditionally add ACPI _PRW based on wake source
by Paul Menzel (Code Review) 03 Apr '25

03 Apr '25

Attention is currently required from: Cliff Huang, Intel coreboot Reviewers, Jérémy Compostella, Kyoung Il Kim. Paul Menzel has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/87085?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: drivers/intel/touch: Conditionally add ACPI _PRW based on wake source ...................................................................... Patch Set 4: (2 comments) Patchset: PS4: yb Commit Message: https://review.coreboot.org/c/coreboot/+/87085/comment/7ae49315_f6968d29?us… : PS4, Line 22: Verify that : the THC ACPI tables are correctly generated in the SSDT. Please add exactly how it should look like. -- To view, visit https://review.coreboot.org/c/coreboot/+/87085?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I56fc8486c7494ff37c1d580d57838fee286128a6 Gerrit-Change-Number: 87085 Gerrit-PatchSet: 4 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Kyoung Il Kim <kyoung.il.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Kyoung Il Kim <kyoung.il.kim(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Comment-Date: Thu, 03 Apr 2025 18:47:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: mb/google/fatcat: Increase sagv_freq_mhz for work point #1 and #3
by Subrata Banik (Code Review) 03 Apr '25

03 Apr '25

Attention is currently required from: Jayvik Desai, Kapil Porwal, Paul Menzel, Pranava Y N. Subrata Banik has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/87087?usp=email ) Change subject: mb/google/fatcat: Increase sagv_freq_mhz for work point #1 and #3 ...................................................................... Patch Set 5: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/87087/comment/a6448695_04d25d12?us… : PS4, Line 7: Update > More specific: Increase Acknowledged -- To view, visit https://review.coreboot.org/c/coreboot/+/87087?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id0b25adeed4b3f3e1c37d17901006a2db2d21223 Gerrit-Change-Number: 87087 Gerrit-PatchSet: 5 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Thu, 03 Apr 2025 18:13:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>

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[XS] Change in coreboot[main]: mb/google/fatcat: Increase sagv_freq_mhz for work point #1 and #3
by Subrata Banik (Code Review) 03 Apr '25

03 Apr '25

Attention is currently required from: Jayvik Desai, Kapil Porwal, Pranava Y N, Subrata Banik. Hello Jayvik Desai, Kapil Porwal, Paul Menzel, Pranava Y N, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/87087?usp=email to look at the new patch set (#5). Change subject: mb/google/fatcat: Increase sagv_freq_mhz for work point #1 and #3 ...................................................................... mb/google/fatcat: Increase sagv_freq_mhz for work point #1 and #3 Update the SaGV frequency registers - (`sagv_freq_mhz[1]`) in the devicetree from "3200" to "4800". - (`sagv_freq_mhz[3]`) in the devicetree from "6400" to "6800". This change likely to improve the device performance. BUG=b:328770565, b:407862619 TEST=Able to reduce the boot time by 18ms. Change-Id: Id0b25adeed4b3f3e1c37d17901006a2db2d21223 Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/87087/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/87087?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id0b25adeed4b3f3e1c37d17901006a2db2d21223 Gerrit-Change-Number: 87087 Gerrit-PatchSet: 5 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com>

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