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The change is no longer submittable: All-Comments-Resolved is unsatisfied now.
Change subject: Add allocation of a buffer for pvmfw within cbmem
......................................................................
Patch Set 3:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/87107/comment/d183d9bf_f0510f92?us… :
PS3, Line 9: his change adds
Add …
https://review.coreboot.org/c/coreboot/+/87107/comment/bc001915_37f32b38?us… :
PS3, Line 17: TEST=Check if pvmfw buffer is available for depthcharge
How do you check it?
File src/vendorcode/google/Kconfig:
https://review.coreboot.org/c/coreboot/+/87107/comment/4370d1ae_b6ac7bcf?us… :
PS3, Line 45: pvmfw
Please elaborate in the description.
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Change subject: util/amdfwtool: Move needs_ish and combo_new_rab to data_parse.c
......................................................................
Patch Set 2: Code-Review+1
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Change subject: google/chromeec: Add function to report the SKU ID
......................................................................
Patch Set 13:
(1 comment)
File src/ec/google/chromeec/Makefile.mk:
https://review.coreboot.org/c/coreboot/+/86810/comment/730b74d9_88573e13?us… :
PS12, Line 14: y
> > Ok, you mean remove CPP checks and rely on Kconfig to use sku_id implementation by moving google_c […]
I moved google_chromeec_get_board_sku to ec.c
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Change subject: mb/google/brya: Add support to get sku ID
......................................................................
Patch Set 16:
(2 comments)
Patchset:
PS2:
> Apologies for my late response. […]
Done
File src/mainboard/google/brya/Kconfig:
https://review.coreboot.org/c/coreboot/+/86599/comment/14a1cfc6_0a0eea66?us… :
PS15, Line 26: EC_GOOGLE_CHROMEEC_SKUID
> looks like you have remove this Kconfig in previous CL https://review.coreboot. […]
yes, as google_chromeec_get_board_sku was no longer controlled by CONFIG_EC_GOOGLE_CHROMEEC_SKUID
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Hello Boris Mittelberg, Caveh Jalali, Dinesh Gehlot, Eran Mitrani, Eric Lai, Hung-Te Lin, Jakub "Kuba" Czapiga, Jason Nien, Jayvik Desai, Julius Werner, Kapil Porwal, Martin Roth, Nick Vaccaro, Pranava Y N, Subrata Banik, Tarun, Yidi Lin, build bot (Jenkins),
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Code-Review+1 by Julius Werner, Code-Review+1 by Yidi Lin, Verified+1 by build bot (Jenkins)
Change subject: google/chromeec: Add function to report the SKU ID
......................................................................
google/chromeec: Add function to report the SKU ID
Add implementation of sku_id function that reports the SKU ID
information by making use of ChromeOS EC host command. This function
can replace redundant sku_id function definitions across boards that
rely on ChromeOS EC host command to report the SKU ID information.
The boards that relying on ChromeOS EC host command for SKU information
without any board specific quirks can select EC_GOOGLE_CHROMEEC_SKUID
to make use of common sku_id function.
BUG=b:396366352
TEST=Verify zork boot log reports the correct the SKU ID information
Change-Id: I958cc88bf316dd2327b6545c5a37e8010e96c5d7
Signed-off-by: Aamir Bohra <aamirbohra(a)google.com>
---
M src/ec/google/chromeec/ec.c
M src/ec/google/chromeec/ec_skuid.c
M src/mainboard/google/brox/Kconfig
M src/mainboard/google/brya/Kconfig
M src/mainboard/google/cherry/Kconfig
M src/mainboard/google/corsola/Kconfig
M src/mainboard/google/dedede/Kconfig
M src/mainboard/google/fatcat/Kconfig
M src/mainboard/google/geralt/Kconfig
M src/mainboard/google/guybrush/Kconfig
M src/mainboard/google/hatch/Kconfig
M src/mainboard/google/herobrine/Kconfig
M src/mainboard/google/myst/Kconfig
M src/mainboard/google/ocelot/Kconfig
M src/mainboard/google/octopus/Kconfig
M src/mainboard/google/puff/Kconfig
M src/mainboard/google/rauru/Kconfig
M src/mainboard/google/rex/Kconfig
M src/mainboard/google/skyrim/Kconfig
M src/mainboard/google/volteer/Kconfig
M src/mainboard/google/zork/sku_id.c
M src/mainboard/intel/ptlrvp/Kconfig
M src/mainboard/intel/shadowmountain/Kconfig
23 files changed, 16 insertions(+), 35 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/86810/13
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Change subject: ec/google/chromeec: Add Kconfig for ChromeEC SMBIOS APIs
......................................................................
ec/google/chromeec: Add Kconfig for ChromeEC SMBIOS APIs
ChromeEC support information for SKU, OEM name and manufacturer name
using EC host commands. Instead of tying it up with SKU ID Kconfig
define a new Kconfig that clearly describes and allow adding support
for SMBIOS APIs based on ChromeEC host command.
BUG=b:396366352
TEST=Verify ec_smbios still compiles for required boards.
Change-Id: I665a3276aa6dc01571657359d17f292efc601d63
Signed-off-by: Aamir Bohra <aamirbohra(a)google.com>
---
M src/ec/google/chromeec/Kconfig
M src/ec/google/chromeec/Makefile.mk
M src/mainboard/google/brox/Kconfig
M src/mainboard/google/brya/Kconfig
M src/mainboard/google/dedede/Kconfig
M src/mainboard/google/fatcat/Kconfig
M src/mainboard/google/guybrush/Kconfig
M src/mainboard/google/hatch/Kconfig
M src/mainboard/google/myst/Kconfig
M src/mainboard/google/ocelot/Kconfig
M src/mainboard/google/octopus/Kconfig
M src/mainboard/google/puff/Kconfig
M src/mainboard/google/rex/Kconfig
M src/mainboard/google/skyrim/Kconfig
M src/mainboard/google/volteer/Kconfig
M src/mainboard/google/zork/Kconfig
M src/mainboard/intel/ptlrvp/Kconfig
M src/mainboard/intel/shadowmountain/Kconfig
18 files changed, 24 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/86993/4
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Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/87061?usp=email )
Change subject: mb/google/brya/var/gimble: Enable RTD3 for SSD to resolve S0ix issue
......................................................................
mb/google/brya/var/gimble: Enable RTD3 for SSD to resolve S0ix issue
Some SSDs block the CPU from reaching C10 during the S0ix suspend
without the RTD3 configuration. Add PCIe RTD3 support so NVMe gets
placed into D3 state when entering S0ix.
Enable and reset GPIOs are configured as per pin mapping in gpio.c.
BUG=b:391612392
TEST=Run suspend_stress_test on gimble device and verify that the
device suspends to S0ix.
Change-Id: Iac9eb63639cbb0c7708d5b2bb30aca20e09db3e7
Signed-off-by: Pranava Y N <pranavayn(a)google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87061
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Jayvik Desai <jayvik(a)google.com>
Reviewed-by: Kapil Porwal <kapilporwal(a)google.com>
---
M src/mainboard/google/brya/variants/gimble/overridetree.cb
1 file changed, 9 insertions(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Kapil Porwal: Looks good to me, approved
Jayvik Desai: Looks good to me, approved
diff --git a/src/mainboard/google/brya/variants/gimble/overridetree.cb b/src/mainboard/google/brya/variants/gimble/overridetree.cb
index 4f1bcdc..762c3ff 100644
--- a/src/mainboard/google/brya/variants/gimble/overridetree.cb
+++ b/src/mainboard/google/brya/variants/gimble/overridetree.cb
@@ -159,6 +159,15 @@
device generic 0 on end
end
end #PCIE8 SD card
+ device ref pcie_rp9 on
+ chip soc/intel/common/block/pcie/rtd3
+ register "is_storage" = "true"
+ register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D11)"
+ register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B4)"
+ register "srcclk_pin" = "1"
+ device generic 0 on end
+ end
+ end #PCIE9-12 SSD
device ref i2c0 on
chip drivers/i2c/generic
register "hid" = ""10EC5682""
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Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: Iac9eb63639cbb0c7708d5b2bb30aca20e09db3e7
Gerrit-Change-Number: 87061
Gerrit-PatchSet: 3
Gerrit-Owner: Pranava Y N <pranavayn(a)google.com>
Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com>
Gerrit-Reviewer: Eric Lai <ericllai(a)google.com>
Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com>
Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com>
Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org>
Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/87058?usp=email )
Change subject: mb/google/brya/var/redrix: Enable RTD3 for SSD to resolve S0ix issue
......................................................................
mb/google/brya/var/redrix: Enable RTD3 for SSD to resolve S0ix issue
Some SSDs block the CPU from reaching C10 during the S0ix suspend
without the RTD3 configuration. Add PCIe RTD3 support so NVMe gets
placed into D3 state when entering S0ix.
Enable and reset GPIOs are configured as per pin mapping in gpio.c.
BUG=b:391612392
TEST=Run suspend_stress_test on redrix device and verify that the
device suspends to S0ix.
Change-Id: I9d8bd6bb2c5aecf2fa67486cc81935d2ac7cd5ce
Signed-off-by: Pranava Y N <pranavayn(a)google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87058
Reviewed-by: Jayvik Desai <jayvik(a)google.com>
Reviewed-by: Kapil Porwal <kapilporwal(a)google.com>
Reviewed-by: Eric Lai <ericllai(a)google.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M src/mainboard/google/brya/variants/redrix/overridetree.cb
1 file changed, 9 insertions(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Eric Lai: Looks good to me, approved
Jayvik Desai: Looks good to me, approved
Kapil Porwal: Looks good to me, approved
diff --git a/src/mainboard/google/brya/variants/redrix/overridetree.cb b/src/mainboard/google/brya/variants/redrix/overridetree.cb
index 1a9f1d9..4b48697 100644
--- a/src/mainboard/google/brya/variants/redrix/overridetree.cb
+++ b/src/mainboard/google/brya/variants/redrix/overridetree.cb
@@ -327,6 +327,15 @@
device generic 0 on end
end
end #PCIE8 SD card
+ device ref pcie_rp9 on
+ chip soc/intel/common/block/pcie/rtd3
+ register "is_storage" = "true"
+ register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D11)"
+ register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B4)"
+ register "srcclk_pin" = "1"
+ device generic 0 on end
+ end
+ end #PCIE9-12 SSD
device ref i2c0 on
chip drivers/i2c/generic
register "hid" = ""RTL5682""
--
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Gerrit-MessageType: merged
Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: I9d8bd6bb2c5aecf2fa67486cc81935d2ac7cd5ce
Gerrit-Change-Number: 87058
Gerrit-PatchSet: 3
Gerrit-Owner: Pranava Y N <pranavayn(a)google.com>
Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com>
Gerrit-Reviewer: Eric Lai <ericllai(a)google.com>
Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com>
Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com>
Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org>
Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/87060?usp=email )
Change subject: mb/google/brya/var/mithrax: Enable RTD3 for SSD to resolve S0ix issue
......................................................................
mb/google/brya/var/mithrax: Enable RTD3 for SSD to resolve S0ix issue
Some SSDs block the CPU from reaching C10 during the S0ix suspend
without the RTD3 configuration. Add PCIe RTD3 support so NVMe gets
placed into D3 state when entering S0ix.
Enable and reset GPIOs are configured as per pin mapping in gpio.c.
BUG=b:391612392
TEST=Run suspend_stress_test on mithrax device and verify that the
device suspends to S0ix.
Change-Id: I5008ec5e153c3695b1d6aa1183515eba192deaa2
Signed-off-by: Pranava Y N <pranavayn(a)google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87060
Reviewed-by: Eric Lai <ericllai(a)google.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal(a)google.com>
Reviewed-by: Subrata Banik <subratabanik(a)google.com>
Reviewed-by: Jayvik Desai <jayvik(a)google.com>
---
M src/mainboard/google/brya/variants/mithrax/overridetree.cb
1 file changed, 9 insertions(+), 0 deletions(-)
Approvals:
Jayvik Desai: Looks good to me, approved
build bot (Jenkins): Verified
Kapil Porwal: Looks good to me, approved
Subrata Banik: Looks good to me, approved
Eric Lai: Looks good to me, approved
diff --git a/src/mainboard/google/brya/variants/mithrax/overridetree.cb b/src/mainboard/google/brya/variants/mithrax/overridetree.cb
index 15bebe2..6a85edf 100644
--- a/src/mainboard/google/brya/variants/mithrax/overridetree.cb
+++ b/src/mainboard/google/brya/variants/mithrax/overridetree.cb
@@ -218,6 +218,15 @@
device generic 0 on end
end
end #PCIE8 SD card
+ device ref pcie_rp9 on
+ chip soc/intel/common/block/pcie/rtd3
+ register "is_storage" = "true"
+ register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D11)"
+ register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B4)"
+ register "srcclk_pin" = "1"
+ device generic 0 on end
+ end
+ end #PCIE9-12 SSD
device ref i2c0 on
chip drivers/i2c/generic
register "hid" = ""RTL5682""
--
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Gerrit-MessageType: merged
Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: I5008ec5e153c3695b1d6aa1183515eba192deaa2
Gerrit-Change-Number: 87060
Gerrit-PatchSet: 4
Gerrit-Owner: Pranava Y N <pranavayn(a)google.com>
Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com>
Gerrit-Reviewer: Eric Lai <ericllai(a)google.com>
Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com>
Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com>
Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org>
Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>