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Change subject: mb/google/nissa/var/rull: Enable early EC software sync for Rull
......................................................................
Patch Set 3: Code-Review+2
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Change subject: mb/google/nissa/var/rull: Enable early EC software sync for Rull
......................................................................
Patch Set 3:
(1 comment)
File src/mainboard/google/brya/Kconfig:
https://review.coreboot.org/c/coreboot/+/87104/comment/52835861_fe82da4b?us… :
PS2, Line 563: VBOOT_EARLY_EC_SYNC
> select this inside vboot section with board Kconfig name
Done
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Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Pranava Y N.
Hello Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/87104?usp=email
to look at the new patch set (#3).
The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)
Change subject: mb/google/nissa/var/rull: Enable early EC software sync for Rull
......................................................................
mb/google/nissa/var/rull: Enable early EC software sync for Rull
Enable `VBOOT_EARLY_EC_SYNC` for rull device. This enables EC software
sync in romstage. This is useful to achieve full USB-PD negotiation
early in the boot flow. It eliminates a problem seen in rull devices
where PMC is wrongly configured in depthcharge during the EC-sync
scenario which prevents USB devices from getting detected when
connected via a self-powered USB hub.
BUG=b:386920751
TEST=Verify detection and booting to OS from USB drive connected to the
Servo v4 debugger (self-powered hub) during the EC-sync scenario.
Change-Id: Ie36794a8a2c0bcd4ba77f3ad844a30f28f59403f
Signed-off-by: Pranava Y N <pranavayn(a)google.com>
---
M src/mainboard/google/brya/Kconfig
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/87104/3
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Change subject: mb/google/fatcat: Allow board-specific FSP-M UPD override
......................................................................
mb/google/fatcat: Allow board-specific FSP-M UPD override
This commit introduces a mechanism to allow mainboards to override
the default FSP-M UPDs for Panther Lake.
- Adds `variant_update_soc_memory_init_params` as a weak function
in `variants.h` and `romstage.c` for board-specific implementations.
- In `romstage.c`, `mainboard_memory_init_params` now calls
`variant_update_soc_memory_init_params` to apply board-specific
overrides to the FSP-M UPDs.
This enables finer-grained control over memory initialization parameters
at the variant level.
BUG=b:328770565
TEST=Able to build and boot google/fatcat.
Change-Id: I403bc4270ef526363defa6cd7d22741ad42a8a76
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
---
M src/mainboard/google/fatcat/romstage.c
M src/mainboard/google/fatcat/variants/baseboard/include/baseboard/variants.h
2 files changed, 11 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/87089/3
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Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/87092?usp=email )
Change subject: commonlib/storage: Avoid build error when CONFIG_PCI is disabled
......................................................................
commonlib/storage: Avoid build error when CONFIG_PCI is disabled
When CONFIG_PCI is disabled, but COMMONLIB_STORAGE and
COMMONLIB_STORAGE_SD are enabled, the compilation of
pci_sdhci.c fails. This is because the code attempts to use
pci_s_read_config32() with the PCI_BASE_ADDRESS_0 macro, which
are only defined when CONFIG_PCI is enabled.
Add an early return NULL check based on !CONFIG(PCI) at the
beginning of new_pci_sdhci_controller(). This prevents the
compiler from attempting to process the PCI-specific code path
when PCI support is not configured, resolving the build failure
in this specific Kconfig scenario.
TEST=Able to build herobrine.
Change-Id: I5c70d9b9ebcac13b47bba2c260fdf2ad7d56d4d7
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87092
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal(a)google.com>
---
M src/commonlib/storage/pci_sdhci.c
1 file changed, 4 insertions(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Kapil Porwal: Looks good to me, approved
diff --git a/src/commonlib/storage/pci_sdhci.c b/src/commonlib/storage/pci_sdhci.c
index f7922d4..51b44de 100644
--- a/src/commonlib/storage/pci_sdhci.c
+++ b/src/commonlib/storage/pci_sdhci.c
@@ -2,6 +2,7 @@
#include <commonlib/sdhci.h>
#include <device/pci.h>
+#include <device/pci_def.h>
#include <device/pci_ops.h>
#include <stdint.h>
@@ -42,6 +43,9 @@
{
uintptr_t addr;
+ if (!CONFIG(PCI))
+ return NULL;
+
addr = pci_s_read_config32(dev, PCI_BASE_ADDRESS_0);
if (addr == ((uint32_t)~0)) {
sdhc_error("Error: PCI SDHCI not found\n");
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