coreboot-gerrit April 2025

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[S] Change in coreboot[main]: google/chromeec: Add function to report the SKU ID
by Matt DeVillier (Code Review) 05 Apr '25

05 Apr '25

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86810?usp=email ) Change subject: google/chromeec: Add function to report the SKU ID ...................................................................... google/chromeec: Add function to report the SKU ID Add implementation of sku_id function that reports the SKU ID information by making use of ChromeOS EC host command. This function can replace redundant sku_id function definitions across boards that rely on ChromeOS EC host command to report the SKU ID information. The boards that relying on ChromeOS EC host command for SKU information without any board specific quirks can select EC_GOOGLE_CHROMEEC_SKUID to make use of common sku_id function. Brya, zork, rex, fatcat, brox and dedede boards select EC_GOOGLE_CHROMEEC_SKUID to use ChromeOS EC sku_id function. BUG=b:396366352 TEST=Verify zork and brya boot log reports the correct the SKU ID information Change-Id: I958cc88bf316dd2327b6545c5a37e8010e96c5d7 Signed-off-by: Aamir Bohra <aamirbohra(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86810 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> --- M src/ec/google/chromeec/ec.c M src/ec/google/chromeec/ec_skuid.c M src/mainboard/google/cherry/Kconfig M src/mainboard/google/corsola/Kconfig M src/mainboard/google/geralt/Kconfig M src/mainboard/google/guybrush/Kconfig M src/mainboard/google/hatch/Kconfig M src/mainboard/google/herobrine/Kconfig M src/mainboard/google/myst/Kconfig M src/mainboard/google/ocelot/Kconfig M src/mainboard/google/octopus/Kconfig M src/mainboard/google/puff/Kconfig M src/mainboard/google/rauru/Kconfig M src/mainboard/google/skyrim/Kconfig M src/mainboard/google/volteer/Kconfig M src/mainboard/google/zork/sku_id.c M src/mainboard/intel/ptlrvp/Kconfig M src/mainboard/intel/shadowmountain/Kconfig 18 files changed, 16 insertions(+), 30 deletions(-) Approvals: Subrata Banik: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c index 5844071..993bddf 100644 --- a/src/ec/google/chromeec/ec.c +++ b/src/ec/google/chromeec/ec.c @@ -689,6 +689,19 @@ return cbi_get_uint32(id, CBI_TAG_SKU_ID); } +uint32_t google_chromeec_get_board_sku(void) +{ + static uint32_t sku_id = CROS_SKU_UNKNOWN; + + if (sku_id != CROS_SKU_UNKNOWN) + return sku_id; + + if (google_chromeec_cbi_get_sku_id(&sku_id)) + sku_id = CROS_SKU_UNKNOWN; + + return sku_id; +} + int google_chromeec_cbi_get_fw_config(uint64_t *fw_config) { uint32_t config; diff --git a/src/ec/google/chromeec/ec_skuid.c b/src/ec/google/chromeec/ec_skuid.c index c0e079c..7acf0c4 100644 --- a/src/ec/google/chromeec/ec_skuid.c +++ b/src/ec/google/chromeec/ec_skuid.c @@ -1,16 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ +#include <boardid.h> #include <ec/google/chromeec/ec.h> -uint32_t google_chromeec_get_board_sku(void) +uint32_t sku_id(void) { - static uint32_t sku_id = CROS_SKU_UNKNOWN; - - if (sku_id != CROS_SKU_UNKNOWN) - return sku_id; - - if (google_chromeec_cbi_get_sku_id(&sku_id)) - sku_id = CROS_SKU_UNKNOWN; - - return sku_id; + return google_chromeec_get_board_sku(); } diff --git a/src/mainboard/google/cherry/Kconfig b/src/mainboard/google/cherry/Kconfig index e301185..2e4b3d3 100644 --- a/src/mainboard/google/cherry/Kconfig +++ b/src/mainboard/google/cherry/Kconfig @@ -19,7 +19,6 @@ select SPI_FLASH_INCLUDE_ALL_DRIVERS select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_BOARDID - select EC_GOOGLE_CHROMEEC_SKUID select EC_GOOGLE_CHROMEEC_SPI select I2C_TPM if VBOOT select TPM_GOOGLE_CR50 if VBOOT diff --git a/src/mainboard/google/corsola/Kconfig b/src/mainboard/google/corsola/Kconfig index d8643fd..1f249ac 100644 --- a/src/mainboard/google/corsola/Kconfig +++ b/src/mainboard/google/corsola/Kconfig @@ -48,7 +48,6 @@ select COMMONLIB_STORAGE_MMC select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_BOARDID - select EC_GOOGLE_CHROMEEC_SKUID select EC_GOOGLE_CHROMEEC_SPI select SPI_TPM if VBOOT select TPM_GOOGLE_TI50 if VBOOT diff --git a/src/mainboard/google/geralt/Kconfig b/src/mainboard/google/geralt/Kconfig index dbc155c..80975ad 100644 --- a/src/mainboard/google/geralt/Kconfig +++ b/src/mainboard/google/geralt/Kconfig @@ -29,7 +29,6 @@ select COMMONLIB_STORAGE_MMC select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_BOARDID - select EC_GOOGLE_CHROMEEC_SKUID select EC_GOOGLE_CHROMEEC_SPI select I2C_TPM if VBOOT select MAINBOARD_HAS_TPM2 if VBOOT diff --git a/src/mainboard/google/guybrush/Kconfig b/src/mainboard/google/guybrush/Kconfig index 7ca4bcb..8c85f97 100644 --- a/src/mainboard/google/guybrush/Kconfig +++ b/src/mainboard/google/guybrush/Kconfig @@ -21,7 +21,6 @@ select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_BOARDID select EC_GOOGLE_CHROMEEC_ESPI - select EC_GOOGLE_CHROMEEC_SKUID select EC_GOOGLE_CHROMEEC_SMBIOS select ELOG select ELOG_GSMI diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index e04ca94..82a6326 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -16,7 +16,6 @@ select EC_GOOGLE_CHROMEEC_BOARDID select EC_GOOGLE_CHROMEEC_ESPI select EC_GOOGLE_CHROMEEC_I2C_TUNNEL - select EC_GOOGLE_CHROMEEC_SKUID select EC_GOOGLE_CHROMEEC_SMBIOS select GOOGLE_SMBIOS_MAINBOARD_VERSION select HAVE_ACPI_RESUME diff --git a/src/mainboard/google/herobrine/Kconfig b/src/mainboard/google/herobrine/Kconfig index 8758fb9..af56814 100644 --- a/src/mainboard/google/herobrine/Kconfig +++ b/src/mainboard/google/herobrine/Kconfig @@ -24,7 +24,6 @@ select COMMON_CBFS_SPI_WRAPPER select EC_GOOGLE_CHROMEEC if !BOARD_GOOGLE_SENOR select EC_GOOGLE_CHROMEEC_RTC if !BOARD_GOOGLE_SENOR - select EC_GOOGLE_CHROMEEC_SKUID if !BOARD_GOOGLE_SENOR select EC_GOOGLE_CHROMEEC_SPI if !BOARD_GOOGLE_SENOR select RTC if !BOARD_GOOGLE_SENOR select MISSING_BOARD_RESET if BOARD_GOOGLE_SENOR diff --git a/src/mainboard/google/myst/Kconfig b/src/mainboard/google/myst/Kconfig index 7e882b7..e405316 100644 --- a/src/mainboard/google/myst/Kconfig +++ b/src/mainboard/google/myst/Kconfig @@ -20,7 +20,6 @@ select DRIVERS_UART_ACPI select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_ESPI - select EC_GOOGLE_CHROMEEC_SKUID select EC_GOOGLE_CHROMEEC_SMBIOS select EC_GOOGLE_CHROMEEC_BOARDID select ELOG diff --git a/src/mainboard/google/ocelot/Kconfig b/src/mainboard/google/ocelot/Kconfig index 16dcdcb..8383c8f 100644 --- a/src/mainboard/google/ocelot/Kconfig +++ b/src/mainboard/google/ocelot/Kconfig @@ -20,7 +20,6 @@ select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_BOARDID select EC_GOOGLE_CHROMEEC_ESPI - select EC_GOOGLE_CHROMEEC_SKUID select EC_GOOGLE_CHROMEEC_SMBIOS select FW_CONFIG select FW_CONFIG_SOURCE_CHROMEEC_CBI diff --git a/src/mainboard/google/octopus/Kconfig b/src/mainboard/google/octopus/Kconfig index d8ac777..9ae9e4c 100644 --- a/src/mainboard/google/octopus/Kconfig +++ b/src/mainboard/google/octopus/Kconfig @@ -15,7 +15,6 @@ select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_BOARDID select EC_GOOGLE_CHROMEEC_ESPI - select EC_GOOGLE_CHROMEEC_SKUID select EC_GOOGLE_CHROMEEC_SMBIOS select GOOGLE_SMBIOS_MAINBOARD_VERSION select HAVE_ACPI_RESUME diff --git a/src/mainboard/google/puff/Kconfig b/src/mainboard/google/puff/Kconfig index 8ef3231..d5786a5 100644 --- a/src/mainboard/google/puff/Kconfig +++ b/src/mainboard/google/puff/Kconfig @@ -17,7 +17,6 @@ select EC_GOOGLE_CHROMEEC_BOARDID select EC_GOOGLE_CHROMEEC_ESPI select EC_GOOGLE_CHROMEEC_I2C_TUNNEL - select EC_GOOGLE_CHROMEEC_SKUID select EC_GOOGLE_CHROMEEC_SMBIOS select FW_CONFIG select FW_CONFIG_SOURCE_CHROMEEC_CBI diff --git a/src/mainboard/google/rauru/Kconfig b/src/mainboard/google/rauru/Kconfig index 06d8546..b32923d 100644 --- a/src/mainboard/google/rauru/Kconfig +++ b/src/mainboard/google/rauru/Kconfig @@ -28,7 +28,6 @@ select CHROMEOS_USE_EC_WATCHDOG_FLAG if CHROMEOS select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_BOARDID - select EC_GOOGLE_CHROMEEC_SKUID select EC_GOOGLE_CHROMEEC_SPI select I2C_TPM if VBOOT select MAINBOARD_HAS_TPM2 if VBOOT diff --git a/src/mainboard/google/skyrim/Kconfig b/src/mainboard/google/skyrim/Kconfig index ebbc0af..e1718bb2 100644 --- a/src/mainboard/google/skyrim/Kconfig +++ b/src/mainboard/google/skyrim/Kconfig @@ -49,7 +49,6 @@ select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_BOARDID select EC_GOOGLE_CHROMEEC_ESPI - select EC_GOOGLE_CHROMEEC_SKUID select EC_GOOGLE_CHROMEEC_SMBIOS select ELOG select ELOG_GSMI diff --git a/src/mainboard/google/volteer/Kconfig b/src/mainboard/google/volteer/Kconfig index f708327..fdda53b 100644 --- a/src/mainboard/google/volteer/Kconfig +++ b/src/mainboard/google/volteer/Kconfig @@ -23,7 +23,6 @@ select EC_GOOGLE_CHROMEEC_BOARDID select EC_GOOGLE_CHROMEEC_INCLUDE_SSFC_IN_FW_CONFIG select EC_GOOGLE_CHROMEEC_LPC - select EC_GOOGLE_CHROMEEC_SKUID select EC_GOOGLE_CHROMEEC_SMBIOS select ENABLE_TCSS_USB_DETECTION if !CHROMEOS select FW_CONFIG diff --git a/src/mainboard/google/zork/sku_id.c b/src/mainboard/google/zork/sku_id.c index 82ee355..34f7d98 100644 --- a/src/mainboard/google/zork/sku_id.c +++ b/src/mainboard/google/zork/sku_id.c @@ -4,11 +4,6 @@ #include <baseboard/variants.h> #include <ec/google/chromeec/ec.h> -uint32_t sku_id(void) -{ - return google_chromeec_get_board_sku(); -} - /* An unprovisioned SKU ID indicates we're in the factory booting prior to proper SKU ID provisioning. */ int boot_is_factory_unprovisioned(void) diff --git a/src/mainboard/intel/ptlrvp/Kconfig b/src/mainboard/intel/ptlrvp/Kconfig index eed44e7..73e170d 100644 --- a/src/mainboard/intel/ptlrvp/Kconfig +++ b/src/mainboard/intel/ptlrvp/Kconfig @@ -19,7 +19,6 @@ select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_BOARDID select EC_GOOGLE_CHROMEEC_ESPI - select EC_GOOGLE_CHROMEEC_SKUID select EC_GOOGLE_CHROMEEC_SMBIOS select FW_CONFIG select FW_CONFIG_SOURCE_CHROMEEC_CBI diff --git a/src/mainboard/intel/shadowmountain/Kconfig b/src/mainboard/intel/shadowmountain/Kconfig index 8c26e44..1dfca4b 100644 --- a/src/mainboard/intel/shadowmountain/Kconfig +++ b/src/mainboard/intel/shadowmountain/Kconfig @@ -15,7 +15,6 @@ select DRIVERS_USB_ACPI select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_BOARDID - select EC_GOOGLE_CHROMEEC_SKUID select EC_GOOGLE_CHROMEEC_SMBIOS select EC_GOOGLE_CHROMEEC_LPC select HAVE_ACPI_RESUME -- To view, visit https://review.coreboot.org/c/coreboot/+/86810?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I958cc88bf316dd2327b6545c5a37e8010e96c5d7 Gerrit-Change-Number: 86810 Gerrit-PatchSet: 16 Gerrit-Owner: Aamir Bohra <aamirbohra(a)google.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jakub "Kuba" Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Yu-Ping Wu <yupingso(a)google.com>

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[S] Change in coreboot[main]: ec/google/chromeec: Add Kconfig for ChromeEC SMBIOS APIs
by Matt DeVillier (Code Review) 05 Apr '25

05 Apr '25

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86993?usp=email ) Change subject: ec/google/chromeec: Add Kconfig for ChromeEC SMBIOS APIs ...................................................................... ec/google/chromeec: Add Kconfig for ChromeEC SMBIOS APIs ChromeEC support information for SKU, OEM name and manufacturer name using EC host commands. Instead of tying it up with SKU ID Kconfig define a new Kconfig that clearly describes and allow adding support for SMBIOS APIs based on ChromeEC host command. BUG=b:396366352 TEST=Verify ec_smbios still compiles for required boards. Change-Id: I665a3276aa6dc01571657359d17f292efc601d63 Signed-off-by: Aamir Bohra <aamirbohra(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86993 Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/ec/google/chromeec/Kconfig M src/ec/google/chromeec/Makefile.mk M src/mainboard/google/brox/Kconfig M src/mainboard/google/brya/Kconfig M src/mainboard/google/dedede/Kconfig M src/mainboard/google/fatcat/Kconfig M src/mainboard/google/guybrush/Kconfig M src/mainboard/google/hatch/Kconfig M src/mainboard/google/myst/Kconfig M src/mainboard/google/ocelot/Kconfig M src/mainboard/google/octopus/Kconfig M src/mainboard/google/puff/Kconfig M src/mainboard/google/rex/Kconfig M src/mainboard/google/skyrim/Kconfig M src/mainboard/google/volteer/Kconfig M src/mainboard/google/zork/Kconfig M src/mainboard/intel/ptlrvp/Kconfig M src/mainboard/intel/shadowmountain/Kconfig 18 files changed, 24 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Kapil Porwal: Looks good to me, approved Subrata Banik: Looks good to me, approved diff --git a/src/ec/google/chromeec/Kconfig b/src/ec/google/chromeec/Kconfig index 851ebb9..bcd2b13 100644 --- a/src/ec/google/chromeec/Kconfig +++ b/src/ec/google/chromeec/Kconfig @@ -136,6 +136,12 @@ help Provides common routine for reporting the skuid to ChromeOS. +config EC_GOOGLE_CHROMEEC_SMBIOS + def_bool n + help + Enable support to get SKU and board information for SMBIOS table + using Chrome EC host commands. + config EC_GOOGLE_CHROMEEC_RTC bool "Enable ChromeOS EC RTC" help diff --git a/src/ec/google/chromeec/Makefile.mk b/src/ec/google/chromeec/Makefile.mk index 6465c2c..54d4040 100644 --- a/src/ec/google/chromeec/Makefile.mk +++ b/src/ec/google/chromeec/Makefile.mk @@ -16,8 +16,8 @@ ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC_SKUID) += ec_skuid.c ifeq ($(CONFIG_GENERATE_SMBIOS_TABLES),y) -romstage-$(CONFIG_EC_GOOGLE_CHROMEEC_SKUID) += ec_smbios.c -ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC_SKUID) += ec_smbios.c +romstage-$(CONFIG_EC_GOOGLE_CHROMEEC_SMBIOS) += ec_smbios.c +ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC_SMBIOS) += ec_smbios.c endif bootblock-y += ec.c diff --git a/src/mainboard/google/brox/Kconfig b/src/mainboard/google/brox/Kconfig index 6f50880..3b5d335 100644 --- a/src/mainboard/google/brox/Kconfig +++ b/src/mainboard/google/brox/Kconfig @@ -16,6 +16,7 @@ select EC_GOOGLE_CHROMEEC_BOARDID select EC_GOOGLE_CHROMEEC_ESPI select EC_GOOGLE_CHROMEEC_SKUID + select EC_GOOGLE_CHROMEEC_SMBIOS select ENABLE_TCSS_USB_DETECTION if !(SOC_INTEL_TCSS_USE_PDC_PMC_USBC_MUX_CONFIGURATION || CHROMEOS) select FW_CONFIG select FW_CONFIG_SOURCE_CHROMEEC_CBI diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index 9aaf789..8886901 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -23,6 +23,7 @@ select EC_GOOGLE_CHROMEEC_BOARDID select EC_GOOGLE_CHROMEEC_ESPI select EC_GOOGLE_CHROMEEC_SKUID + select EC_GOOGLE_CHROMEEC_SMBIOS select EDK2_UFS_ENABLE if EDK2_REPO_MRCHROMEBOX select ENABLE_TCSS_USB_DETECTION if !(SOC_INTEL_TCSS_USE_PDC_PMC_USBC_MUX_CONFIGURATION || CHROMEOS) select FW_CONFIG diff --git a/src/mainboard/google/dedede/Kconfig b/src/mainboard/google/dedede/Kconfig index cb61ecc..2f94fa6 100644 --- a/src/mainboard/google/dedede/Kconfig +++ b/src/mainboard/google/dedede/Kconfig @@ -21,6 +21,7 @@ select EC_GOOGLE_CHROMEEC_ESPI select EC_GOOGLE_CHROMEEC_INCLUDE_SSFC_IN_FW_CONFIG select EC_GOOGLE_CHROMEEC_SKUID + select EC_GOOGLE_CHROMEEC_SMBIOS select FW_CONFIG select FW_CONFIG_SOURCE_CHROMEEC_CBI select GOOGLE_SMBIOS_MAINBOARD_VERSION diff --git a/src/mainboard/google/fatcat/Kconfig b/src/mainboard/google/fatcat/Kconfig index 5773029..2679b14 100644 --- a/src/mainboard/google/fatcat/Kconfig +++ b/src/mainboard/google/fatcat/Kconfig @@ -21,6 +21,7 @@ select EC_GOOGLE_CHROMEEC_BOARDID select EC_GOOGLE_CHROMEEC_ESPI select EC_GOOGLE_CHROMEEC_SKUID + select EC_GOOGLE_CHROMEEC_SMBIOS select FW_CONFIG select FW_CONFIG_SOURCE_CHROMEEC_CBI select GENERATE_SMBIOS_TABLES diff --git a/src/mainboard/google/guybrush/Kconfig b/src/mainboard/google/guybrush/Kconfig index 92a5e00..7ca4bcb 100644 --- a/src/mainboard/google/guybrush/Kconfig +++ b/src/mainboard/google/guybrush/Kconfig @@ -22,6 +22,7 @@ select EC_GOOGLE_CHROMEEC_BOARDID select EC_GOOGLE_CHROMEEC_ESPI select EC_GOOGLE_CHROMEEC_SKUID + select EC_GOOGLE_CHROMEEC_SMBIOS select ELOG select ELOG_GSMI select FW_CONFIG diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index 493db33..e04ca94 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -17,6 +17,7 @@ select EC_GOOGLE_CHROMEEC_ESPI select EC_GOOGLE_CHROMEEC_I2C_TUNNEL select EC_GOOGLE_CHROMEEC_SKUID + select EC_GOOGLE_CHROMEEC_SMBIOS select GOOGLE_SMBIOS_MAINBOARD_VERSION select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES diff --git a/src/mainboard/google/myst/Kconfig b/src/mainboard/google/myst/Kconfig index c507777..7e882b7 100644 --- a/src/mainboard/google/myst/Kconfig +++ b/src/mainboard/google/myst/Kconfig @@ -21,6 +21,7 @@ select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_ESPI select EC_GOOGLE_CHROMEEC_SKUID + select EC_GOOGLE_CHROMEEC_SMBIOS select EC_GOOGLE_CHROMEEC_BOARDID select ELOG select ELOG_GSMI diff --git a/src/mainboard/google/ocelot/Kconfig b/src/mainboard/google/ocelot/Kconfig index b4adda2..16dcdcb 100644 --- a/src/mainboard/google/ocelot/Kconfig +++ b/src/mainboard/google/ocelot/Kconfig @@ -21,6 +21,7 @@ select EC_GOOGLE_CHROMEEC_BOARDID select EC_GOOGLE_CHROMEEC_ESPI select EC_GOOGLE_CHROMEEC_SKUID + select EC_GOOGLE_CHROMEEC_SMBIOS select FW_CONFIG select FW_CONFIG_SOURCE_CHROMEEC_CBI select GENERATE_SMBIOS_TABLES diff --git a/src/mainboard/google/octopus/Kconfig b/src/mainboard/google/octopus/Kconfig index 2676039..d8ac777 100644 --- a/src/mainboard/google/octopus/Kconfig +++ b/src/mainboard/google/octopus/Kconfig @@ -16,6 +16,7 @@ select EC_GOOGLE_CHROMEEC_BOARDID select EC_GOOGLE_CHROMEEC_ESPI select EC_GOOGLE_CHROMEEC_SKUID + select EC_GOOGLE_CHROMEEC_SMBIOS select GOOGLE_SMBIOS_MAINBOARD_VERSION select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES diff --git a/src/mainboard/google/puff/Kconfig b/src/mainboard/google/puff/Kconfig index 3e64f05..8ef3231 100644 --- a/src/mainboard/google/puff/Kconfig +++ b/src/mainboard/google/puff/Kconfig @@ -18,6 +18,7 @@ select EC_GOOGLE_CHROMEEC_ESPI select EC_GOOGLE_CHROMEEC_I2C_TUNNEL select EC_GOOGLE_CHROMEEC_SKUID + select EC_GOOGLE_CHROMEEC_SMBIOS select FW_CONFIG select FW_CONFIG_SOURCE_CHROMEEC_CBI select GOOGLE_SMBIOS_MAINBOARD_VERSION diff --git a/src/mainboard/google/rex/Kconfig b/src/mainboard/google/rex/Kconfig index 8dcd5cc..42e5512 100644 --- a/src/mainboard/google/rex/Kconfig +++ b/src/mainboard/google/rex/Kconfig @@ -16,6 +16,7 @@ select EC_GOOGLE_CHROMEEC_BOARDID select EC_GOOGLE_CHROMEEC_ESPI select EC_GOOGLE_CHROMEEC_SKUID + select EC_GOOGLE_CHROMEEC_SMBIOS select FW_CONFIG select FW_CONFIG_SOURCE_CHROMEEC_CBI select GOOGLE_SMBIOS_MAINBOARD_VERSION diff --git a/src/mainboard/google/skyrim/Kconfig b/src/mainboard/google/skyrim/Kconfig index 756db5f..ebbc0af 100644 --- a/src/mainboard/google/skyrim/Kconfig +++ b/src/mainboard/google/skyrim/Kconfig @@ -50,6 +50,7 @@ select EC_GOOGLE_CHROMEEC_BOARDID select EC_GOOGLE_CHROMEEC_ESPI select EC_GOOGLE_CHROMEEC_SKUID + select EC_GOOGLE_CHROMEEC_SMBIOS select ELOG select ELOG_GSMI select FW_CONFIG diff --git a/src/mainboard/google/volteer/Kconfig b/src/mainboard/google/volteer/Kconfig index 15a8ece..f708327 100644 --- a/src/mainboard/google/volteer/Kconfig +++ b/src/mainboard/google/volteer/Kconfig @@ -24,6 +24,7 @@ select EC_GOOGLE_CHROMEEC_INCLUDE_SSFC_IN_FW_CONFIG select EC_GOOGLE_CHROMEEC_LPC select EC_GOOGLE_CHROMEEC_SKUID + select EC_GOOGLE_CHROMEEC_SMBIOS select ENABLE_TCSS_USB_DETECTION if !CHROMEOS select FW_CONFIG select FW_CONFIG_SOURCE_CHROMEEC_CBI diff --git a/src/mainboard/google/zork/Kconfig b/src/mainboard/google/zork/Kconfig index 1b38d27..2cb2964 100644 --- a/src/mainboard/google/zork/Kconfig +++ b/src/mainboard/google/zork/Kconfig @@ -62,6 +62,7 @@ select EC_GOOGLE_CHROMEEC_I2C_TUNNEL select EC_GOOGLE_CHROMEEC_INCLUDE_SSFC_IN_FW_CONFIG select EC_GOOGLE_CHROMEEC_SKUID + select EC_GOOGLE_CHROMEEC_SMBIOS select EDK2_PCO_MMIO_EMMC if EDK2_REPO_MRCHROMEBOX select ELOG select ELOG_BOOT_COUNT diff --git a/src/mainboard/intel/ptlrvp/Kconfig b/src/mainboard/intel/ptlrvp/Kconfig index dd60855..eed44e7 100644 --- a/src/mainboard/intel/ptlrvp/Kconfig +++ b/src/mainboard/intel/ptlrvp/Kconfig @@ -20,6 +20,7 @@ select EC_GOOGLE_CHROMEEC_BOARDID select EC_GOOGLE_CHROMEEC_ESPI select EC_GOOGLE_CHROMEEC_SKUID + select EC_GOOGLE_CHROMEEC_SMBIOS select FW_CONFIG select FW_CONFIG_SOURCE_CHROMEEC_CBI select GENERATE_SMBIOS_TABLES diff --git a/src/mainboard/intel/shadowmountain/Kconfig b/src/mainboard/intel/shadowmountain/Kconfig index f01479b..8c26e44 100644 --- a/src/mainboard/intel/shadowmountain/Kconfig +++ b/src/mainboard/intel/shadowmountain/Kconfig @@ -16,6 +16,7 @@ select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_BOARDID select EC_GOOGLE_CHROMEEC_SKUID + select EC_GOOGLE_CHROMEEC_SMBIOS select EC_GOOGLE_CHROMEEC_LPC select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES -- To view, visit https://review.coreboot.org/c/coreboot/+/86993?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I665a3276aa6dc01571657359d17f292efc601d63 Gerrit-Change-Number: 86993 Gerrit-PatchSet: 5 Gerrit-Owner: Aamir Bohra <aamirbohra(a)google.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jakub "Kuba" Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: arch/x86/cpu: Add helper function to compute cache
by Matt DeVillier (Code Review) 05 Apr '25

05 Apr '25

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85638?usp=email ) Change subject: arch/x86/cpu: Add helper function to compute cache ...................................................................... arch/x86/cpu: Add helper function to compute cache Consider special requirements for computing cache size in certain SoCs, such as `soc/amd/glinda`. Use the helper function to implement SoC-specific logic for computing cache size. Change-Id: I60707de4c8242a8fbda8cb5b791a1db762d94449 Signed-off-by: Naresh Solanki <naresh.solanki(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85638 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/arch/x86/Kconfig M src/arch/x86/cpu_common.c M src/arch/x86/include/arch/cpu.h 3 files changed, 29 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved Angel Pons: Looks good to me, approved diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index 7ef1a6d..d78aa8f 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -453,4 +453,10 @@ help For platforms without writable PAM-F segment support. Put ROM table pointers (e.g. ACPI/SMBIOS low pointers) into EBDA. + +config SOC_FILL_CPU_CACHE_INFO + bool + default n + help + SoC selects this if it implements soc_fill_cpu_cache_info. endif diff --git a/src/arch/x86/cpu_common.c b/src/arch/x86/cpu_common.c index 5f7cd5d..d7d701d 100644 --- a/src/arch/x86/cpu_common.c +++ b/src/arch/x86/cpu_common.c @@ -212,11 +212,8 @@ return (cpuid_edx(5) >> (state * 4)) & 0xf; } -bool fill_cpu_cache_info(uint8_t level, struct cpu_cache_info *info) +bool x86_get_cpu_cache_info(uint8_t level, struct cpu_cache_info *info) { - if (!info) - return false; - uint32_t leaf = cpu_get_cache_info_leaf(); if (!leaf) return false; @@ -235,6 +232,16 @@ return true; } +bool fill_cpu_cache_info(uint8_t level, struct cpu_cache_info *info) +{ + if (!info) + return false; + + if (CONFIG(SOC_FILL_CPU_CACHE_INFO)) + return soc_fill_cpu_cache_info(level, info); + + return x86_get_cpu_cache_info(level, info); +} bool is_cache_sets_power_of_two(void) { diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h index 8bc6a18..3685561 100644 --- a/src/arch/x86/include/arch/cpu.h +++ b/src/arch/x86/include/arch/cpu.h @@ -331,6 +331,18 @@ bool fill_cpu_cache_info(uint8_t level, struct cpu_cache_info *info); /* + * soc_fill_cpu_cache_info is SoC specific implementation for fill_cpu_cache_info. + * This is intended to compute cache size for a particular level when generic + * implementation isn't accurate. + * Returns True if SoC handler was success else return False. + */ +bool soc_fill_cpu_cache_info(uint8_t level, struct cpu_cache_info *info); + +/* + * x86_get_cpu_cache_info is generic x86 implementation. + */ +bool x86_get_cpu_cache_info(uint8_t level, struct cpu_cache_info *info); +/* * Determines whether the number of cache sets is a power of two. * * Cache designs often favor power-of-two set counts for efficient indexing -- To view, visit https://review.coreboot.org/c/coreboot/+/85638?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I60707de4c8242a8fbda8cb5b791a1db762d94449 Gerrit-Change-Number: 85638 Gerrit-PatchSet: 9 Gerrit-Owner: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Marvin Drees <marvin.drees(a)9elements.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: NyeonWoo Kim Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andy Ebrahiem <ahmet.ebrahiem(a)9elements.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com>

1 0

[M] Change in coreboot[main]: mb/google/fatcat: Add Intel Touch support for touchscreen and touchpad
by Matt DeVillier (Code Review) 05 Apr '25

05 Apr '25

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85200?usp=email ) ( 40 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/google/fatcat: Add Intel Touch support for touchscreen and touchpad ...................................................................... mb/google/fatcat: Add Intel Touch support for touchscreen and touchpad This commit introduces support for touch functionalities on the Google Fatcat board( Please see docu # 818597). Changes include: - Configuration for building with the THC driver - Support for touchscreen devices in both THC-I2C and THC-SPI modes - Rework is necessary for touchscreen use in THC-SPI mode on Fatcat board - The ELAN BOM37A device is supported in THC-I2C mode - The ELAN BOM36 device is supported in THC-SPI mode - Support for the HYNITRON HFW68H touchpad device in THC-I2C mode - A rework is required to switch the interrupt pad from GPP_A13 to GPP_F18 for touchpad use in THC-I2C mode - Introduction of variant-specific touch.h header file - Wake support from S0ix state for both touchscreen and touchpad across multiple modes: LPSS-I2C, THC-I2C, and THC-SPI - PMC GPE DW0 is reconfigured to GPP_F for Touchpad in LPSS mode in variant.c for wake support BUG=none TEST= 1. Set the CBI firmware configuration for touchscreen to TOUCHSCREEN_LPSS_I2C and/or TOUCHPAD to TOUCHPAD_LPSS_I2C 2. Check the ACPI objects are generated in SSDT 3. The devices should be enumerated under the /sys/class/hidraw directory 4. The Touchscreen and/or touchpad should function properly The cursor on the screen should move accordingly 5. Test wake from S0ix state via touchscreen and touchpad inputs 6. Repeat the above for the THC CBI configurations: touchscreen: TOUCHSCREEN_THC_I2C touchpad: TOUCHPAD_THC_I2C Signed-off-by: Cliff Huang <cliff.huang(a)intel.com> Change-Id: I865dbb9eed648c8f35c7f469b27a13be993ff479 Reviewed-on: https://review.coreboot.org/c/coreboot/+/85200 Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/fatcat/Kconfig M src/mainboard/google/fatcat/variants/fatcat/fw_config.c M src/mainboard/google/fatcat/variants/fatcat/gpio.c M src/mainboard/google/fatcat/variants/fatcat/overridetree.cb M src/mainboard/google/fatcat/variants/fatcat/variant.c 5 files changed, 182 insertions(+), 16 deletions(-) Approvals: Kapil Porwal: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/google/fatcat/Kconfig b/src/mainboard/google/fatcat/Kconfig index 6bdf333..5773029 100644 --- a/src/mainboard/google/fatcat/Kconfig +++ b/src/mainboard/google/fatcat/Kconfig @@ -60,6 +60,7 @@ select BOARD_GOOGLE_BASEBOARD_FATCAT select DRIVERS_GENERIC_BAYHUB_LV2 select DRIVERS_GENERIC_MAX98357A + select DRIVERS_INTEL_TOUCH config BOARD_GOOGLE_FATCAT select BOARD_GOOGLE_MODEL_FATCAT diff --git a/src/mainboard/google/fatcat/variants/fatcat/fw_config.c b/src/mainboard/google/fatcat/variants/fatcat/fw_config.c index 668950c..afd8a63 100644 --- a/src/mainboard/google/fatcat/variants/fatcat/fw_config.c +++ b/src/mainboard/google/fatcat/variants/fatcat/fw_config.c @@ -351,6 +351,8 @@ PAD_NC(GPP_E17, NONE), /* GPP_E18: THC0_SPI1_INT_N_TCH_PNL1 */ PAD_NC(GPP_E18, NONE), + /* GPP_VGPIO3_THC0: THC0_WOT */ + PAD_NC(GPP_VGPIO3_THC0, NONE), }; static const struct pad_config touchscreen_lpss_i2c_enable_pads[] = { @@ -370,6 +372,8 @@ PAD_NC(GPP_E17, NONE), /* GPP_E18: THC0_SPI1_INT_N_TCH_PNL1 */ PAD_CFG_GPI_APIC(GPP_E18, NONE, PLTRST, LEVEL, NONE), + /* GPP_VGPIO3_THC0: THC0_WOT */ + PAD_NC(GPP_VGPIO3_THC0, NONE), }; static const struct pad_config touchscreen_thc_i2c_enable_pads[] = { @@ -388,7 +392,10 @@ /* GPP_E17: THC0_SPI1_CS0_N_TCH_PNL1 */ PAD_NC(GPP_E17, NONE), /* GPP_E18: THC0_SPI1_INT_N_TCH_PNL1 */ - PAD_CFG_GPI_APIC(GPP_E18, NONE, PLTRST, LEVEL, NONE), + /* NOTE: this SPI INT NF is also used in THC-I2C mode */ + PAD_CFG_NF(GPP_E18, NONE, DEEP, NF3), + /* GPP_VGPIO3_THC0: THC0_WOT */ + PAD_NC(GPP_VGPIO3_THC0, NONE), }; static const struct pad_config touchscreen_gspi_enable_pads[] = { @@ -407,7 +414,9 @@ /* GPP_E17: THC0_SPI1_CS0_N_TCH_PNL1 NF5: GSPI0 */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF5), /* GPP_E18: THC0_SPI1_INT_N_TCH_PNL1 */ - PAD_CFG_GPI_APIC(GPP_E18, NONE, PLTRST, EDGE_SINGLE, INVERT) + PAD_CFG_GPI_APIC(GPP_E18, NONE, PLTRST, EDGE_SINGLE, INVERT), + /* GPP_VGPIO3_THC0: THC0_WOT */ + PAD_NC(GPP_VGPIO3_THC0, NONE), }; static const struct pad_config touchscreen_thc_spi_enable_pads[] = { @@ -428,6 +437,8 @@ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF3), /* GPP_E18: THC0_SPI1_INT_N_TCH_PNL1 NF3: THC HID-SPI */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF3), + /* GPP_VGPIO3_THC0: THC0_WOT */ + PAD_NC(GPP_VGPIO3_THC0, NONE), }; static const struct pad_config touchpad_thc_i2c_enable_pads[] = { @@ -435,8 +446,12 @@ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), /* GPP_F13: NF1: THC_I2C1_SDA */ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), - /* GPP_F18: NF3: THC1_INT_N */ - PAD_CFG_NF(GPP_F18, NONE, DEEP, NF3) + /* GPP_F18: TCH_PAD_INT_N */ + /* NOTE: this SPI INT NF is also used in THC-I2C mode */ + /* NOTE: require rework to switch from GPP_A13 to GPP_F18 */ + PAD_CFG_NF(GPP_F18, NONE, DEEP, NF3), + /* GPP_VGPIO3_THC1: THC1_WOT */ + PAD_NC(GPP_VGPIO3_THC1, NONE), }; static const struct pad_config touchpad_lpss_i2c_enable_pads[] = { @@ -445,7 +460,10 @@ /* GPP_F13: THC_I2C1_SDA_TCH_PAD */ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF8), /* GPP_F18: TCH_PAD_INT_N */ - PAD_CFG_GPI_APIC(GPP_F18, NONE, PWROK, LEVEL, INVERT), + /* NOTE: require rework to switch from GPP_A13 to GPP_F18 */ + PAD_CFG_GPI_APIC(GPP_F18, NONE, PLTRST, LEVEL, INVERT), + /* GPP_VGPIO3_THC1: THC1_WOT */ + PAD_NC(GPP_VGPIO3_THC1, NONE), }; static const struct pad_config touchpad_i2c_disable_pads[] = { @@ -454,7 +472,20 @@ /* GPP_F13: THC_I2C1_SDA_TCH_PAD */ PAD_NC(GPP_F13, NONE), /* GPP_F18: TCH_PAD_INT_N */ + /* NOTE: require rework to switch from GPP_A13 to GPP_F18 */ PAD_NC(GPP_F18, NONE), + /* GPP_VGPIO3_THC1: THC1_WOT */ + PAD_NC(GPP_VGPIO3_THC1, NONE), +}; + +static const struct pad_config thc0_enable_wake[] = { + /* GPP_VGPIO3_THC0: THC0_WOT */ + PAD_CFG_GPI_APIC_DRIVER(GPP_VGPIO3_THC0, NONE, PLTRST, LEVEL, NONE), +}; + +static const struct pad_config thc1_enable_wake[] = { + /* GPP_VGPIO3_THC1: THC1_WOT */ + PAD_CFG_GPI_APIC_DRIVER(GPP_VGPIO3_THC1, NONE, PLTRST, LEVEL, NONE), }; static const struct pad_config ish_disable_pads[] = { @@ -558,6 +589,8 @@ void fw_config_gpio_padbased_override(struct pad_config *padbased_table) { + const struct soc_intel_pantherlake_config *config = config_of_soc(); + if (!fw_config_is_provisioned()) { printk(BIOS_WARNING, "FW_CONFIG is not provisioned, Exiting\n"); return; @@ -620,23 +653,31 @@ else GPIO_PADBASED_OVERRIDE(padbased_table, x1slot_pads); - if (fw_config_probe(FW_CONFIG(TOUCHPAD, TOUCHPAD_LPSS_I2C))) + if (fw_config_probe(FW_CONFIG(TOUCHPAD, TOUCHPAD_LPSS_I2C))) { GPIO_PADBASED_OVERRIDE(padbased_table, touchpad_lpss_i2c_enable_pads); - else if (fw_config_probe(FW_CONFIG(TOUCHPAD, TOUCHPAD_THC_I2C))) + } else if (fw_config_probe(FW_CONFIG(TOUCHPAD, TOUCHPAD_THC_I2C))) { GPIO_PADBASED_OVERRIDE(padbased_table, touchpad_thc_i2c_enable_pads); - else + if (config->thc_wake_on_touch[1]) + GPIO_PADBASED_OVERRIDE(padbased_table, thc1_enable_wake); + } else { GPIO_PADBASED_OVERRIDE(padbased_table, touchpad_i2c_disable_pads); + } - if (fw_config_probe(FW_CONFIG(TOUCHSCREEN, TOUCHSCREEN_LPSS_I2C))) + if (fw_config_probe(FW_CONFIG(TOUCHSCREEN, TOUCHSCREEN_LPSS_I2C))) { GPIO_PADBASED_OVERRIDE(padbased_table, touchscreen_lpss_i2c_enable_pads); - else if (fw_config_probe(FW_CONFIG(TOUCHSCREEN, TOUCHSCREEN_THC_I2C))) + } else if (fw_config_probe(FW_CONFIG(TOUCHSCREEN, TOUCHSCREEN_THC_I2C))) { GPIO_PADBASED_OVERRIDE(padbased_table, touchscreen_thc_i2c_enable_pads); - else if (fw_config_probe(FW_CONFIG(TOUCHSCREEN, TOUCHSCREEN_GSPI))) + if (config->thc_wake_on_touch[0]) + GPIO_PADBASED_OVERRIDE(padbased_table, thc0_enable_wake); + } else if (fw_config_probe(FW_CONFIG(TOUCHSCREEN, TOUCHSCREEN_GSPI))) { GPIO_PADBASED_OVERRIDE(padbased_table, touchscreen_gspi_enable_pads); - else if (fw_config_probe(FW_CONFIG(TOUCHSCREEN, TOUCHSCREEN_THC_SPI))) + } else if (fw_config_probe(FW_CONFIG(TOUCHSCREEN, TOUCHSCREEN_THC_SPI))) { GPIO_PADBASED_OVERRIDE(padbased_table, touchscreen_thc_spi_enable_pads); - else + if (config->thc_wake_on_touch[0]) + GPIO_PADBASED_OVERRIDE(padbased_table, thc0_enable_wake); + } else { GPIO_PADBASED_OVERRIDE(padbased_table, touchscreen_disable_pads); + } if (fw_config_probe(FW_CONFIG(ISH, ISH_DISABLE))) GPIO_PADBASED_OVERRIDE(padbased_table, ish_disable_pads); @@ -646,8 +687,26 @@ /* NOTE: disable PEG (x8 slot) and x4 slot wake for now */ GPIO_PADBASED_OVERRIDE(padbased_table, peg_x4slot_wake_disable_pads); - if (fw_config_probe(FW_CONFIG(FP, FP_PRESENT))) + /* + * *=========================================================================* + * | userage | GPP_E17 | + * *=========================================================================* + * | touchscreen in THC-SPI (with rework) | NF3: THC HID-SPI CS0 | + * *---------------------------------------*---------------------------------* + * | touchscreen in gSPI (with rework) | NF5: GSPI0 CS0 | + * *---------------------------------------*---------------------------------* + * | FPS present (without rework) | NF5: GSPI0 CS0 | + * *---------------------------------------*---------------------------------* + * + * NOTE: 1. CBI selecting TS THC-SPI or GSPI mode implies TS rework is applied for the board. + * 2. CBI selecting TS THC-SPI or TS GSPI with FSP present is invalid case. + */ + if (fw_config_probe(FW_CONFIG(TOUCHSCREEN, TOUCHSCREEN_GSPI)) || + fw_config_probe(FW_CONFIG(TOUCHSCREEN, TOUCHSCREEN_THC_SPI))) { + /* board has TS SPI rework and not FPS support */ + } else if (fw_config_probe(FW_CONFIG(FP, FP_PRESENT))) { GPIO_PADBASED_OVERRIDE(padbased_table, fp_enable_pads); - else + } else { GPIO_PADBASED_OVERRIDE(padbased_table, fp_disable_pads); + } } diff --git a/src/mainboard/google/fatcat/variants/fatcat/gpio.c b/src/mainboard/google/fatcat/variants/fatcat/gpio.c index 5214359..b1e77ec 100644 --- a/src/mainboard/google/fatcat/variants/fatcat/gpio.c +++ b/src/mainboard/google/fatcat/variants/fatcat/gpio.c @@ -265,6 +265,9 @@ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF8), /* GPP_F17: Not used */ PAD_CFG_GPI_INT(GPP_F17, NONE, PLTRST, EDGE_BOTH), + /* GPP_F18: TCH_PAD_INT_N */ + /* NOTE: require rework to switch from GPP_A13 to GPP_F18 */ + PAD_CFG_GPI_APIC(GPP_F18, NONE, PLTRST, LEVEL, INVERT), /* GPP_F19: GPP_PRIVACY_LED_CAM2 */ PAD_CFG_GPO(GPP_F19, 0, PLTRST), /* GPP_F20: GPP_PRIVACY_LED_CAM1_CVS_HST_WAKE */ diff --git a/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb b/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb index 741b5a4..c6a63c3 100644 --- a/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb +++ b/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb @@ -317,13 +317,66 @@ device ref iaa off end device ref thc0 on + register "thc_wake_on_touch[0]" = "true" probe TOUCHSCREEN TOUCHSCREEN_THC_SPI probe TOUCHSCREEN TOUCHSCREEN_THC_I2C # THC0 is function 0; hence it needs to be enabled when THC1 is to be enabled. probe TOUCHPAD TOUCHPAD_THC_I2C + chip drivers/intel/touch + register "name" = "INTEL_THC0_NAME" + register "mode" = "THC_HID_I2C_MODE" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F08)" + register "enable_delay_ms" = "2" + register "enable_off_delay_ms" = "2" + register "wake_on_touch" = "true" + # NOTE: Use GpioInt() in _CRS and does not use GPE. + register "wake_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPP_VGPIO3_THC0)" + register "active_ltr" = "1" + register "idle_ltr" = "0" + register "connected_device" = "TH_SENSOR_ELAN" + register "add_acpi_dma_property" = "true" + device generic 0 alias touch_0_i2c_elan on + probe TOUCHSCREEN TOUCHSCREEN_THC_I2C + end + end + chip drivers/intel/touch + register "name" = "INTEL_THC0_NAME" + register "mode" = "THC_HID_SPI_MODE" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F08)" + register "enable_delay_ms" = "2" + register "enable_off_delay_ms" = "2" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E16)" + register "reset_delay_ms" = "10" + register "reset_off_delay_ms" = "2" + register "wake_on_touch" = "true" + # NOTE: Use GpioInt() in _CRS and does not use GPE. + register "wake_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPP_VGPIO3_THC0)" + register "active_ltr" = "1" + register "idle_ltr" = "0" + register "connected_device" = "TH_SENSOR_ELAN" + register "soc_hidspi.write_mode" = "HIDSPI_WRITE_MODE_MULTI_SINGLE_SPI" + register "soc_hidspi.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E16)" + register "add_acpi_dma_property" = "true" + device generic 0 alias touch_0_spi_elan on + probe TOUCHSCREEN TOUCHSCREEN_THC_SPI + end + end end device ref thc1 on + register "thc_wake_on_touch[1]" = "true" probe TOUCHPAD TOUCHPAD_THC_I2C + chip drivers/intel/touch + register "name" = "INTEL_THC1_NAME" + register "mode" = "THC_HID_I2C_MODE" + register "wake_on_touch" = "true" + # NOTE: Use GpioInt() in _CRS and does not use GPE. + register "wake_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(GPP_VGPIO3_THC1)" + register "active_ltr" = "1" + register "idle_ltr" = "0" + register "connected_device" = "TH_SENSOR_HYNITRON" + register "add_acpi_dma_property" = "true" + device generic 0 alias touch_1_i2c_hynitron on end + end end device ref tbt_pcie_rp0 on end @@ -811,9 +864,11 @@ end # I2C3 device ref i2c4 on chip drivers/i2c/hid - register "generic.hid" = ""ELAN6918"" + register "generic.hid" = ""ELAN9048"" register "generic.desc" = ""ELAN Touchscreen"" register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E18_IRQ)" + # NOTE: pmc_gpe0_dw2 is GPP_E in baseboard devicetree.cb. + register "generic.wake" = "GPE0_DW2_18" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E16)" register "generic.reset_delay_ms" = "20" @@ -832,6 +887,8 @@ register "generic.hid" = ""HFW68H"" register "generic.desc" = ""Hynitron TOUCHPAD"" register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F18_IRQ)" + # NOTE: pmc_gpe0_dw0 will be overridden to GPP_F in variant.c. + register "generic.wake" = "GPE0_DW0_18" register "generic.uid" = "5" register "generic.detect" = "1" register "hid_desc_reg_offset" = "0x20" diff --git a/src/mainboard/google/fatcat/variants/fatcat/variant.c b/src/mainboard/google/fatcat/variants/fatcat/variant.c index 66c86cf..5ba7683 100644 --- a/src/mainboard/google/fatcat/variants/fatcat/variant.c +++ b/src/mainboard/google/fatcat/variants/fatcat/variant.c @@ -4,6 +4,8 @@ #include <fsp/api.h> #include <fw_config.h> #include <sar.h> +#include <soc/gpio_soc_defs.h> +#include <drivers/intel/touch/chip.h> const char *get_wifi_sar_cbfs_filename(void) { @@ -25,6 +27,50 @@ config->cnvi_bt_audio_offload = true; } } + + /* Touchscreen and touchpad WOT support: + * +===================+==================+=================+============================+ + * | touchsreen | touchpad | PMC_GPE0_DW0 | WOT | + * +===================+==================+==============================================+ + * | THC-SPI/THC-I2C | LPSS-I2C | GPP_F | TS, TP | + * +-------------------+------------------+----------------------------------------------+ + * | THC-SPI/THC-I2C | not used or | GPP_A (default) | TS | + * | | with WOT disabled| | | + * +-------------------+------------------+----------------------------------------------+ + * | THC-SPI/THC-I2C | THC-I2C | GPP_A (default) | TS, TP | + * +-------------------+------------------+----------------------------------------------+ + * | LPSS-SPI/LPSS-I2C | LPSS-I2C | GPP_F | TS via PMC_GPE0_DW2: GPP_E,| + * | | | | TP | + * +-------------------+------------------+----------------------------------------------+ + * | LPSS-SPI/LPSS-I2C | not used or | GPP_A (default) | TS via PMC_GPE0_DW2: GPP_E | + * | | with WOT disabled| | | + * +-------------------+------------------+----------------------------------------------+ + * | not used | not used or | GPP_A (default) | NA | + * | with WOT disabled | with WOT disabled| | | + * +===================+==================+=================+============================+ + */ + if (fw_config_probe(FW_CONFIG(TOUCHSCREEN, TOUCHSCREEN_THC_I2C))) { + config->thc_mode[0] = THC_HID_I2C_MODE; + } else if (fw_config_probe(FW_CONFIG(TOUCHSCREEN, TOUCHSCREEN_THC_SPI))) { + config->thc_mode[0] = THC_HID_SPI_MODE; + } else if (fw_config_probe(FW_CONFIG(TOUCHSCREEN, TOUCHSCREEN_GSPI))) { + config->serial_io_gspi_mode[PchSerialIoIndexGSPI0] = PchSerialIoPci; + } + + if (fw_config_probe(FW_CONFIG(TOUCHPAD, TOUCHPAD_LPSS_I2C))) { + /* touchpad: GPP_F18: GPE0_DW0_18 */ + if (config->thc_wake_on_touch[1]) + config->pmc_gpe0_dw0 = GPP_F; + } else if (fw_config_probe(FW_CONFIG(TOUCHPAD, TOUCHPAD_THC_I2C))) { + config->thc_mode[1] = THC_HID_I2C_MODE; + + if (fw_config_probe(FW_CONFIG(TOUCHSCREEN, TOUCHSCREEN_NONE))) + /* When THC0 is only enabled due to THC1 is enabled, we force THC0 + * to I2C mode so that kernel THC I2C driver will find it and put + * THC0 to low power state because no connected device is found. + */ + config->thc_mode[0] = THC_HID_I2C_MODE; + } } void variant_update_soc_memory_init_params(FSPM_UPD *memupd) -- To view, visit https://review.coreboot.org/c/coreboot/+/85200?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I865dbb9eed648c8f35c7f469b27a13be993ff479 Gerrit-Change-Number: 85200 Gerrit-PatchSet: 42 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Kyoung Il Kim <kyoung.il.kim(a)intel.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

1 0

[XS] Change in coreboot[main]: drivers/intel/touch: Conditionally add ACPI _PRW based on wake source
by Matt DeVillier (Code Review) 05 Apr '25

05 Apr '25

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/87085?usp=email ) ( 4 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: drivers/intel/touch: Conditionally add ACPI _PRW based on wake source ...................................................................... drivers/intel/touch: Conditionally add ACPI _PRW based on wake source This change addresses an issue in the touch driver where the ACPI _PRW method was added unconditionally. The ACPI _PRW method should only be generated when an Interrupt() resource is used in the _CRS method. When a GpioInt() resource is used instead, the _PRW method is not required. The ACPI generation code has been updated to conditionally add the _PRW method based on whether the wake source is a GPIO interrupt or an IRQ interrupt. Now, the _PRW method is only added when an IRQ pin is specified, which is consistent with ACPI requirements. BUG=none TEST=Configure the DRIVERS_INTEL_TOUCH option on a motherboard that has the necessary touch configurations with wake support. Verify that the THC ACPI tables are correctly generated in the SSDT. If wake_gpio (i.e. GpioInt()) is used for wake, no _PRW is generated for the device. Signed-off-by: Cliff Huang <cliff.huang(a)intel.com> Change-Id: I56fc8486c7494ff37c1d580d57838fee286128a6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/87085 Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/drivers/intel/touch/touch.c 1 file changed, 6 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Kapil Porwal: Looks good to me, approved diff --git a/src/drivers/intel/touch/touch.c b/src/drivers/intel/touch/touch.c index 0283312..a89d2e6 100644 --- a/src/drivers/intel/touch/touch.c +++ b/src/drivers/intel/touch/touch.c @@ -194,6 +194,10 @@ touch_acpi_name(dev)); acpigen_write_name("_CRS"); acpigen_write_resourcetemplate_header(); + /* + * NOTE: config->wake_gpio: uses GpioInt() in _CRS; PAD needs to be Driver Mode + * config->wake_irq: uses Interrupt() in _CRS; use GPE; PAD needs to be ACPI Mode + */ if (config->wake_gpio.pin_count) acpi_device_write_gpio(&config->wake_gpio); else if (config->wake_irq.pin) @@ -201,7 +205,8 @@ acpigen_write_resourcetemplate_footer(); acpigen_write_name_integer("_S0W", ACPI_DEVICE_SLEEP_D3_HOT); - acpigen_write_PRW(config->wake_gpe, 3); + if (config->wake_irq.pin) + acpigen_write_PRW(config->wake_gpe, 3); } static void touch_generate_acpi_i2cdev_dsd(const struct device *dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/87085?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I56fc8486c7494ff37c1d580d57838fee286128a6 Gerrit-Change-Number: 87085 Gerrit-PatchSet: 6 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Kyoung Il Kim <kyoung.il.kim(a)intel.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

1 0

[XS] Change in coreboot[main]: mb/starlabs/starbook/mtl: Correct SSD GPIO config
by Matt DeVillier (Code Review) 05 Apr '25

05 Apr '25

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/87127?usp=email ) Change subject: mb/starlabs/starbook/mtl: Correct SSD GPIO config ...................................................................... mb/starlabs/starbook/mtl: Correct SSD GPIO config The SSD uses GPP_A20 for reset, and GPP_H07 for enable. Correct the GPIO configuration and corresponding entry in the devicetree. Change-Id: I71196f65883803ba9bfc8228bb74f25795bb3a6c Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87127 Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/starlabs/starbook/variants/mtl/devicetree.cb M src/mainboard/starlabs/starbook/variants/mtl/gpio.c 2 files changed, 4 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved diff --git a/src/mainboard/starlabs/starbook/variants/mtl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/mtl/devicetree.cb index 9cd7831..b86e01b 100644 --- a/src/mainboard/starlabs/starbook/variants/mtl/devicetree.cb +++ b/src/mainboard/starlabs/starbook/variants/mtl/devicetree.cb @@ -214,7 +214,7 @@ chip soc/intel/common/block/pcie/rtd3 register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H07)" - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H00)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A20)" register "srcclk_pin" = "8" register "is_storage" = "true" register "add_acpi_dma_property" = "true" diff --git a/src/mainboard/starlabs/starbook/variants/mtl/gpio.c b/src/mainboard/starlabs/starbook/variants/mtl/gpio.c index fc03329..333d555 100644 --- a/src/mainboard/starlabs/starbook/variants/mtl/gpio.c +++ b/src/mainboard/starlabs/starbook/variants/mtl/gpio.c @@ -45,7 +45,7 @@ /* SSD */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), /* Clock Request 8 */ - PAD_CFG_GPO(GPP_H00, 1, PLTRST), /* Reset */ + PAD_CFG_GPO(GPP_A20, 1, PLTRST), /* Reset */ PAD_CFG_GPO(GPP_H07, 1, PLTRST), /* Enable */ /* Wireless */ @@ -200,8 +200,6 @@ PAD_NC(GPP_A18, NONE), /* A19: */ PAD_NC(GPP_A19, NONE), - /* A20: M.2_CPU_SSD_RESET_N */ - PAD_CFG_GPO(GPP_A20, 1, PLTRST), /* A22: */ PAD_NC(GPP_A22, NONE), /* A23: */ @@ -260,6 +258,8 @@ * Start: GPP_H00 * End: GPP_H23 */ + /* H00: */ + PAD_NC(GPP_H00, NONE), /* H03: */ PAD_NC(GPP_H03, NONE), /* H04: */ -- To view, visit https://review.coreboot.org/c/coreboot/+/87127?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I71196f65883803ba9bfc8228bb74f25795bb3a6c Gerrit-Change-Number: 87127 Gerrit-PatchSet: 6 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

[XS] Change in coreboot[main]: mb/starlabs/starbook/mtl: Disconnect SML1ALERT
by Matt DeVillier (Code Review) 05 Apr '25

05 Apr '25

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/87126?usp=email ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/starlabs/starbook/mtl: Disconnect SML1ALERT ...................................................................... mb/starlabs/starbook/mtl: Disconnect SML1ALERT This GPIO is not connected, so configure it accordingly. Change-Id: Idafd6fa727f6b3a9fbfe6543c53abeb736aa9f11 Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87126 Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/starlabs/starbook/variants/mtl/gpio.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved diff --git a/src/mainboard/starlabs/starbook/variants/mtl/gpio.c b/src/mainboard/starlabs/starbook/variants/mtl/gpio.c index cd46edb..fc03329 100644 --- a/src/mainboard/starlabs/starbook/variants/mtl/gpio.c +++ b/src/mainboard/starlabs/starbook/variants/mtl/gpio.c @@ -136,7 +136,7 @@ /* C04: SML0_DATA */ PAD_NC(GPP_C04, NONE), /* C08: SML1ALERT */ - PAD_CFG_NF(GPP_C08, NONE, DEEP, NF1), + PAD_NC(GPP_C08, NONE), /* C09: */ PAD_NC(GPP_C09, NONE), /* C10: */ -- To view, visit https://review.coreboot.org/c/coreboot/+/87126?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idafd6fa727f6b3a9fbfe6543c53abeb736aa9f11 Gerrit-Change-Number: 87126 Gerrit-PatchSet: 3 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

[M] Change in coreboot[main]: mb/starlabs/starbook/mtl: Reconfigure PCH Strap GPIOs
by Matt DeVillier (Code Review) 05 Apr '25

05 Apr '25

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/87125?usp=email ) Change subject: mb/starlabs/starbook/mtl: Reconfigure PCH Strap GPIOs ...................................................................... mb/starlabs/starbook/mtl: Reconfigure PCH Strap GPIOs Configure all strap GPIOs as outputs, rather than some being not connected. This doesn't change anything, but is more explicit. Set these all to sample on RSMRST. Change-Id: I53415716364222de713b3bf967419e5a45322e69 Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87125 Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/starlabs/starbook/variants/mtl/gpio.c 1 file changed, 11 insertions(+), 43 deletions(-) Approvals: Matt DeVillier: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/starlabs/starbook/variants/mtl/gpio.c b/src/mainboard/starlabs/starbook/variants/mtl/gpio.c index 25c3b0b..cd46edb 100644 --- a/src/mainboard/starlabs/starbook/variants/mtl/gpio.c +++ b/src/mainboard/starlabs/starbook/variants/mtl/gpio.c @@ -78,6 +78,17 @@ /* TPM */ PAD_CFG_GPI_APIC_LOW(GPP_F13, NONE, PLTRST), /* Interrupt */ + /* Config Straps [ Low / High ] */ + PAD_CFG_GPO(GPP_B14, 0, RSMRST), /* Top Swap [ Disabled / Enabled ] */ + PAD_CFG_GPO(GPP_B04, 0, RSMRST), /* Reboot Support [ Enabled / Disabled ] */ + PAD_CFG_GPO(GPP_C02, 1, RSMRST), /* TLS Confidentiality [ Disabled / Enabled ] */ + PAD_CFG_GPO(GPP_C05, 0, RSMRST), /* eSPI [ Enabled / Disabled ] */ + PAD_CFG_GPO(GPP_E06, 0, RSMRST), /* JTAG ODT [ Disabled / Enabled ] */ + PAD_CFG_GPO(GPP_F02, 0, RSMRST), /* M.2 CNVi [ Enabled / Disabled ] */ + PAD_CFG_GPO(GPP_H01, 0, RSMRST), /* Flash Recovery [ Disabled / Enabled ] */ + PAD_CFG_GPO(GPP_F20, 0, RSMRST), /* SVID [ Present / Disabled ] */ + PAD_CFG_GPO(GPP_F21, 0, RSMRST), /* CCD [ BSSB-LS / BALTIC ] */ + /* V02: PCIE_WAKE_LAN */ PAD_NC(GPP_V02, NONE), /* V06: GPD_6_SLP_A_N */ @@ -120,20 +131,10 @@ * Start: GPP_C00 * End: GPP_C23 */ - /* C02: TLS CONFIDENTIALITY - * HIGH: ENABLED - * LOW: DISABLED - * WEAK INTERNAL PD 20K */ - PAD_CFG_GPO(GPP_C02, 1, DEEP), /* C03: SML0_CLK */ PAD_NC(GPP_C03, NONE), /* C04: SML0_DATA */ PAD_NC(GPP_C04, NONE), - /* C05: ESPI - * HIGH: DISABLED - * LOW: ENABLED - * WEAK INTERNAL PD 20K */ - PAD_CFG_GPO(GPP_C05, 0, PLTRST), /* C08: SML1ALERT */ PAD_CFG_NF(GPP_C08, NONE, DEEP, NF1), /* C09: */ @@ -223,11 +224,6 @@ PAD_NC(GPP_E04, NONE), /* E05: */ PAD_NC(GPP_E05, NONE), - /* E06: JTAG ODT - * HIGH: ENABLED - * LOW: DISABLED - * 20K INTERNAL PU */ - PAD_CFG_GPO(GPP_E06, 0, DEEP), /* E07: */ PAD_NC(GPP_E07, NONE), /* E08: */ @@ -264,11 +260,6 @@ * Start: GPP_H00 * End: GPP_H23 */ - /* H01: FLASH RECOVERY - * HIGH: ENABLED - * LOW: DISABLED - * WEAK INTERNAL PD 20K */ - PAD_CFG_GPO(GPP_H01, 0, DEEP), /* H03: */ PAD_NC(GPP_H03, NONE), /* H04: */ @@ -305,8 +296,6 @@ PAD_NC(GPP_F00, NONE), /* F01: CNV_BRI_RSP */ PAD_NC(GPP_F01, NONE), - /* F02: CNV_RGI_DT */ - PAD_NC(GPP_F02, NONE), /* F03: CNV_RGI_RSP */ PAD_NC(GPP_F03, NONE), /* F04: CNVI_RF_RESET_N */ @@ -342,16 +331,6 @@ * LOW: SLAVE * WEAK INTERNAL PD 20K */ PAD_CFG_GPO(GPP_F19, 0, DEEP), - /* F20: SVID - * HIGH: PRESENT - * LOW: NOT PRESENT - * WEAK INTERNAL PD 20K */ - PAD_CFG_GPO(GPP_F20, 0, DEEP), - /* F21: CCD - * HIGH: BALTIC PEAK - * LOW: BSSB-LS - * WEAK INTERNAL PU 20K */ - PAD_CFG_GPO(GPP_F21, 0, DEEP), /* F22: */ PAD_NC(GPP_F22, NONE), /* F23: */ @@ -390,12 +369,6 @@ PAD_NC(GPP_B02, NONE), /* B03: */ PAD_NC(GPP_B03, NONE), - /* B04: REBOOT CONTROL - * HIGH: NO REBOOT - * LOW: REBOOT ENABLED - * WEAK INTERNAL PD 20K - */ - PAD_CFG_GPO(GPP_B04, 0, DEEP), /* B05: */ PAD_NC(GPP_B05, NONE), /* B06: */ @@ -412,11 +385,6 @@ PAD_NC(GPP_B11, NONE), /* B12: */ PAD_NC(GPP_B12, NONE), - /* B14: Top Swap Override - * HIGH: EMABLED - * LOW: DISABLED - * WEAK INTERNAL PD 20K */ - PAD_CFG_GPO(GPP_B14, 0, PLTRST), /* B15: */ PAD_NC(GPP_B15, NONE), /* B17: */ -- To view, visit https://review.coreboot.org/c/coreboot/+/87125?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I53415716364222de713b3bf967419e5a45322e69 Gerrit-Change-Number: 87125 Gerrit-PatchSet: 5 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: soc/amd/*/psp_verstage: Remove duplicate verstage-generic-ccopts
by Matt DeVillier (Code Review) 05 Apr '25

05 Apr '25

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86864?usp=email ) Change subject: soc/amd/*/psp_verstage: Remove duplicate verstage-generic-ccopts ...................................................................... soc/amd/*/psp_verstage: Remove duplicate verstage-generic-ccopts Also remove include folders that don't even exist. Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com> Change-Id: Ic64f5187e50b903af5461bfa4d57bb4951d3b501 Reviewed-on: https://review.coreboot.org/c/coreboot/+/86864 Reviewed-by: Ana Carolina Cabral <ana.cpmelo95(a)gmail.com> Reviewed-by: Andy Ebrahiem <ahmet.ebrahiem(a)9elements.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/cezanne/psp_verstage/Makefile.mk M src/soc/amd/glinda/psp_verstage/Makefile.mk M src/soc/amd/mendocino/psp_verstage/Makefile.mk M src/soc/amd/phoenix/psp_verstage/Makefile.mk 4 files changed, 0 insertions(+), 7 deletions(-) Approvals: Ana Carolina Cabral: Looks good to me, but someone else must approve Andy Ebrahiem: Looks good to me, but someone else must approve build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/soc/amd/cezanne/psp_verstage/Makefile.mk b/src/soc/amd/cezanne/psp_verstage/Makefile.mk index bb9cc47..36cffdf 100644 --- a/src/soc/amd/cezanne/psp_verstage/Makefile.mk +++ b/src/soc/amd/cezanne/psp_verstage/Makefile.mk @@ -2,8 +2,6 @@ verstage-generic-ccopts += -I$(src)/vendorcode/amd/psp_verstage/cezanne/include -verstage-generic-ccopts += -I$(src)/soc/amd/common/psp_verstage/include - subdirs-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += ../../common/psp_verstage verstage-y += svc.c diff --git a/src/soc/amd/glinda/psp_verstage/Makefile.mk b/src/soc/amd/glinda/psp_verstage/Makefile.mk index f8ad736..a11f053 100644 --- a/src/soc/amd/glinda/psp_verstage/Makefile.mk +++ b/src/soc/amd/glinda/psp_verstage/Makefile.mk @@ -4,8 +4,6 @@ subdirs-y += ../../common/psp_verstage -verstage-generic-ccopts += -I$(src)/soc/amd/glinda/psp_verstage/include -verstage-generic-ccopts += -I$(src)/soc/amd/common/psp_verstage/include verstage-generic-ccopts += -Isrc/vendorcode/amd/psp_verstage/glinda/include verstage-generic-ccopts += -Isrc/vendorcode/amd/psp_verstage/common/include diff --git a/src/soc/amd/mendocino/psp_verstage/Makefile.mk b/src/soc/amd/mendocino/psp_verstage/Makefile.mk index 347f26a..cc19709 100644 --- a/src/soc/amd/mendocino/psp_verstage/Makefile.mk +++ b/src/soc/amd/mendocino/psp_verstage/Makefile.mk @@ -2,8 +2,6 @@ verstage-generic-ccopts += -I$(src)/vendorcode/amd/psp_verstage/mendocino/include -verstage-generic-ccopts += -I$(src)/soc/amd/common/psp_verstage/include - subdirs-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += ../../common/psp_verstage verstage-y += svc.c diff --git a/src/soc/amd/phoenix/psp_verstage/Makefile.mk b/src/soc/amd/phoenix/psp_verstage/Makefile.mk index fc9f413..7571b1d 100644 --- a/src/soc/amd/phoenix/psp_verstage/Makefile.mk +++ b/src/soc/amd/phoenix/psp_verstage/Makefile.mk @@ -2,7 +2,6 @@ subdirs-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += ../../common/psp_verstage -verstage-generic-ccopts += -I$(src)/soc/amd/common/psp_verstage/include verstage-generic-ccopts += -Isrc/vendorcode/amd/psp_verstage/phoenix/include verstage-generic-ccopts += -Isrc/vendorcode/amd/psp_verstage/common/include -- To view, visit https://review.coreboot.org/c/coreboot/+/86864?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic64f5187e50b903af5461bfa4d57bb4951d3b501 Gerrit-Change-Number: 86864 Gerrit-PatchSet: 6 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Ana Carolina Cabral <ana.cpmelo95(a)gmail.com> Gerrit-Reviewer: Andy Ebrahiem <ahmet.ebrahiem(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XL] Change in coreboot[main]: mb/novacustom/mtl-h: Add discrete graphics variant
by Matt DeVillier (Code Review) 05 Apr '25

05 Apr '25

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86790?usp=email ) Change subject: mb/novacustom/mtl-h: Add discrete graphics variant ...................................................................... mb/novacustom/mtl-h: Add discrete graphics variant Add NovaCustom V540TNx and V560TNx, which are variants of the mtl-h baseboard, but with discrete graphics, compared to the igpu variant. Other notable differences: - 16" models come with TAS5825 Smart Amp - Realtek RTL8111 network adapter - 14" models have only one SSD slot - The non-Thunderbolt USB-C port has DP Alt mode with displayport lanes sourced from the discrete graphics - HDMI port is wired to discrete graphics NVIDIA dGPU ASL code will be added in subsequent patches. TEST=Build V560TNx with UEFIPayload and boot to payload Change-Id: I2b8194c486de1ba3e04aa74ed63caa7a151fbb8b Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86790 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> --- M src/mainboard/novacustom/mtl-h/Kconfig M src/mainboard/novacustom/mtl-h/Kconfig.name M src/mainboard/novacustom/mtl-h/Makefile.mk M src/mainboard/novacustom/mtl-h/include/mainboard/gpio.h A src/mainboard/novacustom/mtl-h/include/mainboard/variants.h M src/mainboard/novacustom/mtl-h/ramstage.c A src/mainboard/novacustom/mtl-h/variants/dgpu/data.vbt A src/mainboard/novacustom/mtl-h/variants/dgpu/gpio.c A src/mainboard/novacustom/mtl-h/variants/dgpu/hda_verb.c A src/mainboard/novacustom/mtl-h/variants/dgpu/overridetree.cb A src/mainboard/novacustom/mtl-h/variants/dgpu/ramstage.c A src/mainboard/novacustom/mtl-h/variants/dgpu/tas5825m.c M src/mainboard/novacustom/mtl-h/variants/igpu/gpio.c A src/mainboard/novacustom/mtl-h/variants/igpu/ramstage.c 14 files changed, 2,952 insertions(+), 5 deletions(-) Approvals: build bot (Jenkins): Verified Michał Żygowski: Looks good to me, approved diff --git a/src/mainboard/novacustom/mtl-h/Kconfig b/src/mainboard/novacustom/mtl-h/Kconfig index 813a558..f08ce25 100644 --- a/src/mainboard/novacustom/mtl-h/Kconfig +++ b/src/mainboard/novacustom/mtl-h/Kconfig @@ -23,6 +23,20 @@ select SPD_READ_BY_WORD select SYSTEM_TYPE_LAPTOP +config BOARD_NOVACUSTOM_V5X0TNX_BASE + bool + select EC_DASHARO_EC_DGPU + select BOARD_NOVACUSTOM_MTLH_COMMON + select DRIVERS_I2C_TAS5825M + +config BOARD_NOVACUSTOM_V540TNX + bool + select BOARD_NOVACUSTOM_V5X0TNX_BASE + +config BOARD_NOVACUSTOM_V560TNX + bool + select BOARD_NOVACUSTOM_V5X0TNX_BASE + config BOARD_NOVACUSTOM_V5X0TU_BASE bool select BOARD_NOVACUSTOM_MTLH_COMMON @@ -43,15 +57,18 @@ config VARIANT_DIR default "igpu" if BOARD_NOVACUSTOM_V5X0TU_BASE + default "dgpu" if BOARD_NOVACUSTOM_V5X0TNX_BASE config OVERRIDE_DEVICETREE default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" config MAINBOARD_PART_NUMBER default "V54x_6x_TU" if BOARD_NOVACUSTOM_V5X0TU_BASE + default "V5xTNC_TND_TNE" if BOARD_NOVACUSTOM_V5X0TNX_BASE config MAINBOARD_SMBIOS_PRODUCT_NAME default "V54x_6x_TU" if BOARD_NOVACUSTOM_V5X0TU_BASE + default "V5xTNC_TND_TNE" if BOARD_NOVACUSTOM_V5X0TNX_BASE config MAINBOARD_SMBIOS_MANUFACTURER default "Notebook" @@ -59,6 +76,8 @@ config MAINBOARD_VERSION default "V540TU" if BOARD_NOVACUSTOM_V540TU default "V560TU" if BOARD_NOVACUSTOM_V560TU + default "V540TNx" if BOARD_NOVACUSTOM_V540TNX + default "V560TNx" if BOARD_NOVACUSTOM_V560TNX config MAINBOARD_FAMILY string diff --git a/src/mainboard/novacustom/mtl-h/Kconfig.name b/src/mainboard/novacustom/mtl-h/Kconfig.name index ff079a0..2ad7489 100644 --- a/src/mainboard/novacustom/mtl-h/Kconfig.name +++ b/src/mainboard/novacustom/mtl-h/Kconfig.name @@ -1,7 +1,13 @@ comment "Meteor Lake H" +config BOARD_NOVACUSTOM_V540TNX + bool "V540TNx (14\", discrete graphics)" + +config BOARD_NOVACUSTOM_V560TNX + bool "V560TNx (16\", discrete graphics)" + config BOARD_NOVACUSTOM_V540TU - bool "V540TU (14\")" + bool "V540TU (14\", integrated graphics)" config BOARD_NOVACUSTOM_V560TU - bool "V560TU (16\")" + bool "V560TU (16\", integrated graphics)" diff --git a/src/mainboard/novacustom/mtl-h/Makefile.mk b/src/mainboard/novacustom/mtl-h/Makefile.mk index e4841b2..2607864 100644 --- a/src/mainboard/novacustom/mtl-h/Makefile.mk +++ b/src/mainboard/novacustom/mtl-h/Makefile.mk @@ -11,5 +11,6 @@ ramstage-y += ramstage.c ramstage-y += variants/${VARIANT_DIR}/hda_verb.c ramstage-y += variants/$(VARIANT_DIR)/gpio.c +ramstage-y += variants/$(VARIANT_DIR)/ramstage.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c diff --git a/src/mainboard/novacustom/mtl-h/include/mainboard/gpio.h b/src/mainboard/novacustom/mtl-h/include/mainboard/gpio.h index 57924a6..eb69988 100644 --- a/src/mainboard/novacustom/mtl-h/include/mainboard/gpio.h +++ b/src/mainboard/novacustom/mtl-h/include/mainboard/gpio.h @@ -12,6 +12,6 @@ #endif void mainboard_configure_early_gpios(void); -void mainboard_configure_gpios(void); +void variant_configure_gpios(void); #endif diff --git a/src/mainboard/novacustom/mtl-h/include/mainboard/variants.h b/src/mainboard/novacustom/mtl-h/include/mainboard/variants.h new file mode 100644 index 0000000..09d2a5b --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/include/mainboard/variants.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef MAINBOARD_VARIANTS_H +#define MAINBOARD_VARIANTS_H + +void variant_devtree_update(void); + +#endif diff --git a/src/mainboard/novacustom/mtl-h/ramstage.c b/src/mainboard/novacustom/mtl-h/ramstage.c index 637257a..4d42fa9 100644 --- a/src/mainboard/novacustom/mtl-h/ramstage.c +++ b/src/mainboard/novacustom/mtl-h/ramstage.c @@ -2,6 +2,7 @@ #include <ec/dasharo/ec/acpi.h> #include <mainboard/gpio.h> +#include <mainboard/variants.h> #include <smbios.h> #include <soc/ramstage.h> @@ -20,9 +21,15 @@ return SMBIOS_WAKEUP_TYPE_POWER_SWITCH; } +void __weak variant_devtree_update(void) +{ + /* Override dev tree settings per board */ +} + static void mainboard_init(void *chip_info) { - mainboard_configure_gpios(); + variant_configure_gpios(); + variant_devtree_update(); } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/novacustom/mtl-h/variants/dgpu/data.vbt b/src/mainboard/novacustom/mtl-h/variants/dgpu/data.vbt new file mode 100644 index 0000000..add19e3 --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/variants/dgpu/data.vbt Binary files differ diff --git a/src/mainboard/novacustom/mtl-h/variants/dgpu/gpio.c b/src/mainboard/novacustom/mtl-h/variants/dgpu/gpio.c new file mode 100644 index 0000000..83829a4 --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/variants/dgpu/gpio.c @@ -0,0 +1,329 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <mainboard/gpio.h> +#include <soc/gpio.h> +#include <gpio.h> +#include <timer.h> +#include <delay.h> + +static const struct pad_config gpio_table[] = { + + /* ------- GPIO Community 0 ------- */ + + /* ------- GPIO Group CPU ------- */ + + /* ------- GPIO Group V ------- */ + PAD_CFG_NF(GPP_V00, UP_20K, DEEP, NF1), /* BATLOW# */ + PAD_CFG_NF(GPP_V01, NATIVE, DEEP, NF1), /* ACPRESENT */ + PAD_CFG_GPI_TRIG_OWN(GPP_V02, NATIVE, DEEP, OFF, ACPI), /* GPIO - CPU_LAN_WAKEUP# */ + PAD_CFG_NF(GPP_V03, UP_20K, DEEP, NF1), /* PWRBTN# */ + PAD_CFG_NF(GPP_V04, NONE, DEEP, NF1), /* SLP_S3# */ + PAD_CFG_NF(GPP_V05, NONE, DEEP, NF1), /* SLP_S4# */ + PAD_CFG_NF(GPP_V06, NONE, DEEP, NF1), /* SLP_A# */ + PAD_CFG_GPO(GPP_V07, 0, DEEP), /* GPIO */ + PAD_CFG_NF(GPP_V08, NONE, DEEP, NF1), /* SUSCLK */ + PAD_CFG_NF(GPP_V09, NONE, DEEP, NF1), /* SLP_WLAN# */ + PAD_CFG_NF(GPP_V10, NONE, DEEP, NF1), /* SLP_S5# */ + PAD_CFG_GPO(GPP_V11, 1, DEEP), /* GPIO - GPIO_LAN_EN */ + PAD_CFG_NF(GPP_V12, NONE, DEEP, NF1), /* SLP_LAN# */ + PAD_CFG_GPO(GPP_V13, 0, DEEP), /* GPIO */ + PAD_CFG_NF(GPP_V14, NONE, DEEP, NF1), /* WAKE# */ + PAD_CFG_GPO(GPP_V15, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_V16, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_V17, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_V18, 0, DEEP), /* GPIO */ + PAD_CFG_NF(GPP_V19, NONE, DEEP, NF1), /* n/a */ + PAD_CFG_NF(GPP_V20, NONE, DEEP, NF1), /* n/a */ + PAD_CFG_NF(GPP_V21, NONE, DEEP, NF1), /* n/a */ + PAD_CFG_GPO(GPP_V22, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_V23, 0, DEEP), /* GPIO */ + + /* ------- GPIO Group GPP_C ------- */ + PAD_CFG_NF(GPP_C00, UP_20K, DEEP, NF1), /* SMBCLK */ + PAD_CFG_NF(GPP_C01, UP_20K, DEEP, NF1), /* SMBDATA */ + PAD_CFG_GPI_TRIG_OWN(GPP_C02, NONE, DEEP, OFF, ACPI), /* GPIO */ + PAD_CFG_NF(GPP_C03, NONE, DEEP, NF1), /* SML0CLK */ + PAD_CFG_NF(GPP_C04, NONE, DEEP, NF1), /* SML0DATA */ + PAD_CFG_GPO(GPP_C05, 0, DEEP), /* GPIO */ + PAD_CFG_NF(GPP_C06, NONE, RSMRST, NF1), /* SML1CLK */ + PAD_CFG_NF(GPP_C07, NONE, RSMRST, NF1), /* SML1DATA */ + PAD_CFG_GPO(GPP_C08, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_C09, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_C10, 0, DEEP), /* GPIO */ + PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1), /* SRCCLKREQ2# */ + PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), /* SRCCLKREQ3# */ + PAD_CFG_GPO(GPP_C13, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_C14, 0, DEEP), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_C15, NONE, DEEP, OFF, ACPI), /* GPIO - CPU_DGPU_PWRGD */ + PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* TBT_LSX0_TXD */ + PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), /* TBT_LSX0_RXD */ + PAD_CFG_GPO(GPP_C18, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_C19, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_C20, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_C21, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_C22, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_C23, 0, DEEP), /* GPIO */ + + /* ------- GPIO Community 1 ------- */ + + /* ------- GPIO Group GPP_A ------- */ + PAD_CFG_NF(GPP_A00, UP_20K, DEEP, NF1), /* ESPI_IO0 */ + PAD_CFG_NF(GPP_A01, UP_20K, DEEP, NF1), /* ESPI_IO1 */ + PAD_CFG_NF(GPP_A02, UP_20K, DEEP, NF1), /* ESPI_IO2 */ + PAD_CFG_NF(GPP_A03, UP_20K, DEEP, NF1), /* ESPI_IO3 */ + PAD_CFG_NF(GPP_A04, UP_20K, DEEP, NF1), /* ESPI_CS0# */ + PAD_CFG_NF(GPP_A05, UP_20K, DEEP, NF1), /* ESPI_CLK */ + PAD_CFG_NF(GPP_A06, NONE, DEEP, NF1), /* ESPI_RESET# */ + PAD_CFG_GPO(GPP_A07, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_A08, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_A09, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_A10, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_A11, 0, DEEP), /* GPIO - ADDS_CODE */ + PAD_CFG_GPI_TRIG_OWN(GPP_A12, NONE, DEEP, OFF, ACPI), /* GPIO - WLAN_WAKEUP# */ + PAD_CFG_TERM_GPO(GPP_A13, 1, UP_20K, PLTRST), /* GPIO - M2_SSD2_RST# */ + PAD_CFG_GPI_TRIG_OWN(GPP_A14, UP_20K, DEEP, OFF, ACPI), /* GPIO - NVVDD_ALERT# */ + PAD_CFG_GPO(GPP_A15, 0, DEEP), /* GPIO - CPU_SWI# */ + PAD_CFG_NF(GPP_A16, UP_20K, DEEP, NF1), /* RSVD - ESPI_ALERT0# */ + PAD_CFG_GPI_INT(GPP_A17, NONE, PLTRST, LEVEL), /* GPIO - TP_ATTN# */ + PAD_CFG_GPO(GPP_A18, 0, DEEP), /* GPIO - TEST_R (ANX7411) */ + PAD_CFG_GPI_APIC(GPP_A19, NONE, DEEP, LEVEL, NONE), /* GPIO - INTP_OUT (ANX7411) */ + PAD_CFG_GPO(GPP_A20, 1, DEEP), /* GPIO - LAN_PLT_RST# */ + PAD_CFG_NF(GPP_A21, NATIVE, DEEP, NF1), /* PMCALERT# */ + PAD_NC(GPP_A22, NATIVE), /* GPIO */ + PAD_NC(GPP_A23, NATIVE), /* GPIO */ + + /* ------- GPIO Group GPP_E ------- */ + PAD_CFG_GPI_TRIG_OWN(GPP_E00, NONE, DEEP, OFF, ACPI), /* GPIO - BOARD_ID7 */ + PAD_CFG_GPI_APIC(GPP_E01, UP_20K, DEEP, LEVEL, NONE), /* GPIO - TPM_PIRQ# */ + PAD_CFG_GPI_TRIG_OWN(GPP_E02, NONE, DEEP, OFF, ACPI), /* GPIO - BOARD_ID4 */ + PAD_CFG_GPI_TRIG_OWN(GPP_E03, NONE, DEEP, OFF, ACPI), /* GPIO - CPU_CNVI_WAKE# */ + PAD_CFG_GPO(GPP_E04, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_E05, 0, DEEP), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_E06, NONE, DEEP, OFF, ACPI), /* GPIO */ + PAD_CFG_GPO(GPP_E07, 0, DEEP), /* GPIO - CPU_SMI# */ + PAD_CFG_GPO(GPP_E08, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_E09, 1, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_E10, 0, DEEP), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_E11, NONE, DEEP, OFF, ACPI), /* GPIO - BOARD_ID6 */ + PAD_CFG_NF(GPP_E12, NONE, DEEP, NF8), /* I2C4_SDA - ANX7411 */ + PAD_CFG_NF(GPP_E13, NONE, DEEP, NF8), /* I2C4_SCL - ANX7411 */ + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* DDSP_HPDA */ + PAD_CFG_GPO(GPP_E15, 0, DEEP), /* GPIO - CPU_SCI# */ + PAD_CFG_NF(GPP_E16, NONE, DEEP, NF2), /* VRALERT# */ + PAD_CFG_GPI_TRIG_OWN(GPP_E17, NONE, DEEP, OFF, ACPI), /* GPIO - BOARD_ID5 */ + PAD_CFG_GPO(GPP_E18, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_E19, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_E20, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_E21, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_E22, 0, DEEP), /* GPIO */ + PAD_NC(GPP_E23, NONE), /* GPIO */ + PAD_NC(GPP_THC0_GSPI_CLK_LPBK, NONE), /* GPIO */ + + /* ------- GPIO Community 3 ------- */ + + /* ------- GPIO Group GPP_H ------- */ + PAD_CFG_GPO(GPP_H00, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_H01, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_H02, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_H03, 0, DEEP), /* GPIO */ + PAD_CFG_NF(GPP_H04, NONE, DEEP, NF2), /* CNV_MFUART2_RXD */ + PAD_CFG_NF(GPP_H05, NONE, DEEP, NF2), /* CNV_MFUART2_TXD */ + PAD_CFG_NF(GPP_H06, NONE, DEEP, NF1), /* I2C3_SDA */ + PAD_CFG_NF(GPP_H07, NONE, DEEP, NF1), /* I2C3_SCL */ + PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1), /* UART0_RXD */ + PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1), /* UART0_TXD */ + PAD_CFG_GPO(GPP_H10, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_H11, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_H12, 0, DEEP), /* GPIO */ + PAD_CFG_NF(GPP_H13, NONE, DEEP, NF1), /* PROC_C10_GATE# */ + PAD_CFG_GPO(GPP_H14, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_H15, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_H16, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_H17, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_H18, 0, DEEP), /* GPIO */ + PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1), /* I2C0_SDA */ + PAD_CFG_NF(GPP_H20, NONE, DEEP, NF1), /* I2C0_SCL */ + PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1), /* I2C1_SDA */ + PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1), /* I2C1_SCL */ + PAD_NC(GPP_H23, NONE), /* GPIO */ + PAD_NC(GPP_LPI3C1_CLK_LPBK, NATIVE), /* GPIO */ + PAD_CFG_NF(GPP_LPI3C0_CLK_LPBK, NATIVE, DEEP, NF2), /* n/a */ + + /* ------- GPIO Group GPP_F ------- */ + PAD_CFG_NF(GPP_F00, NONE, DEEP, NF1), /* CNV_BRI_DT */ + PAD_CFG_NF(GPP_F01, UP_20K, DEEP, NF1), /* CNV_BRI_RSP */ + PAD_CFG_NF(GPP_F02, NONE, DEEP, NF1), /* CNV_RGI_DT */ + PAD_CFG_NF(GPP_F03, UP_20K, DEEP, NF1), /* CNV_RGI_RSP */ + PAD_CFG_NF(GPP_F04, NONE, DEEP, NF1), /* CNV_RF_RESET# */ + PAD_CFG_NF(GPP_F05, NONE, DEEP, NF3), /* MODEM_CLKREQ */ + PAD_CFG_NF(GPP_F06, NONE, DEEP, NF1), /* CNVI_GNSS_PA_BLANKING */ + PAD_CFG_GPO(GPP_F07, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_F08, 0, DEEP), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_F09, NONE, DEEP, OFF, ACPI), /* GPIO - TPM_DET */ + PAD_CFG_GPO(GPP_F10, 0, DEEP), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_F11, NONE, DEEP, OFF, ACPI), /* GPIO - BOARD_ID3 */ + PAD_CFG_NF(GPP_F12, NONE, DEEP, NF8), /* I2C5_SCL - Smart AMP */ + PAD_CFG_NF(GPP_F13, NONE, DEEP, NF8), /* I2C5_SDA - Smart AMP */ + PAD_CFG_GPI_TRIG_OWN(GPP_F14, NONE, DEEP, OFF, ACPI), /* GPIO - BOARD_ID1 */ + PAD_CFG_GPI_TRIG_OWN(GPP_F15, NONE, DEEP, OFF, ACPI), /* GPIO - BOARD_ID2 */ + PAD_CFG_GPI_TRIG_OWN(GPP_F16, NONE, DEEP, OFF, ACPI), /* GPIO - GPIO4_GC6_NVVDD_EN */ + PAD_CFG_GPI_TRIG_OWN(GPP_F17, NONE, PLTRST, OFF, ACPI), /* GPIO - CPU_GC6_FB_EN */ + PAD_CFG_GPO(GPP_F18, 0, DEEP), /* GPIO -CCD_WP# */ + PAD_CFG_GPO(GPP_F19, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_F20, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_F21, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_F22, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_F23, 0, DEEP), /* GPIO */ + PAD_NC(GPP_THC1_GSPI1_CLK_LPBK, NONE), /* GPIO */ + PAD_NC(GPP_GSPI0A_CLK_LOOPBK, NONE), /* GPIO */ + + /* ------- GPIO Group SPI ------- */ + + /* ------- GPIO Group VGPIO3 ------- */ + PAD_CFG_NF(GPP_VGPIO3_USB0, NONE, DEEP, NF1), /* GPP_VGPIO3_USB0 */ + PAD_CFG_NF(GPP_VGPIO3_USB1, NONE, DEEP, NF1), /* GPP_VGPIO3_USB1 */ + PAD_CFG_NF(GPP_VGPIO3_USB2, NONE, DEEP, NF1), /* GPP_VGPIO3_USB2 */ + PAD_CFG_NF(GPP_VGPIO3_USB3, NONE, DEEP, NF1), /* GPP_VGPIO3_USB3 */ + PAD_CFG_NF(GPP_VGPIO3_USB4, NONE, DEEP, NF1), /* GPP_VGPIO3_USB4 */ + PAD_CFG_NF(GPP_VGPIO3_USB5, NONE, DEEP, NF1), /* GPP_VGPIO3_USB5 */ + PAD_CFG_NF(GPP_VGPIO3_USB6, NONE, DEEP, NF1), /* GPP_VGPIO3_USB6 */ + PAD_CFG_NF(GPP_VGPIO3_USB7, NONE, DEEP, NF1), /* GPP_VGPIO3_USB7 */ + PAD_CFG_GPI_TRIG_OWN(GPP_VGPIO3_TS0, NONE, DEEP, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_VGPIO3_TS1, NONE, DEEP, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_VGPIO3_THC0, NONE, DEEP, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_VGPIO3_THC1, NONE, DEEP, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_VGPIO3_THC2, NONE, DEEP, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_VGPIO3_THC3, NONE, DEEP, OFF, ACPI), /* GPIO */ + + /* ------- GPIO Community 4 ------- */ + + /* ------- GPIO Group GPP_S ------- */ + PAD_CFG_GPO(GPP_S00, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_S01, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_S02, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_S03, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_S04, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_S05, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_S06, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_S07, 0, DEEP), /* GPIO */ + + /* ------- GPIO Group JTAG ------- */ + + /* ------- GPIO Community 5 ------- */ + + /* ------- GPIO Group GPP_B ------- */ + PAD_CFG_GPO(GPP_B00, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_B01, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_B02, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_B03, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_B04, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_B05, 0, DEEP), /* GPIO - CPU_KBCRST# */ + PAD_CFG_GPO(GPP_B06, 0, DEEP), /* GPIO - ROM_I2C_EN */ + PAD_CFG_GPO(GPP_B07, 0, DEEP), /* GPIO - PANTONE_WP# */ + PAD_CFG_GPO(GPP_B08, 0, DEEP), /* GPIO - PS8461_SW (DDS for eDP) */ + PAD_CFG_GPO(GPP_B09, 0, DEEP), /* GPIO - DGPU_RST#_PCH */ + PAD_CFG_GPI_SCI(GPP_B10, NONE, PLTRST, EDGE_BOTH, INVERT), /* GPIO - NV Type-C DP HPD */ + PAD_CFG_GPI_SCI(GPP_B11, NONE, PLTRST, EDGE_BOTH, INVERT), /* GPIO - NV HDMI HPD */ + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* SLP_S0# */ + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* PLTRST# */ + PAD_CFG_GPO(GPP_B14, 0, DEEP), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_B15, NONE, DEEP, OFF, ACPI), /* GPIO */ + PAD_CFG_GPO(GPP_B16, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_B17, 1, DEEP), /* GPIO - CPU_GPIO_LANRTD3 */ + PAD_CFG_GPO(GPP_B18, 1, DEEP), /* GPIO - PCH_BT_EN */ + PAD_CFG_GPO(GPP_B19, 1, DEEP), /* GPIO - WIFI_RF_EN */ + PAD_CFG_GPO(GPP_B20, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_B21, 0, PLTRST), /* GPIO - TBT_FORCE_PWR */ + PAD_CFG_GPO(GPP_B22, 0, DEEP), /* GPIO */ + PAD_CFG_TERM_GPO(GPP_B23, 0, DN_20K, DEEP), /* GPIO */ + PAD_CFG_NF(GPP_ACI3C0_CLK_LPBK, NATIVE, DEEP, NF4), /* n/a */ + + /* ------- GPIO Group GPP_D ------- */ + PAD_CFG_GPO(GPP_D00, 1, DEEP), /* GPIO - SB_BLON */ + PAD_CFG_GPO(GPP_D01, 1, DEEP), /* GPIO - SSD2_PWR_EN */ + PAD_CFG_GPO(GPP_D02, 1, DEEP), /* GPIO - M2_SSD1_RST# */ + PAD_CFG_GPO(GPP_D03, 0, DEEP), /* GPIO - CPU_DGPU_PWR_EN */ + PAD_CFG_GPO(GPP_D04, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_D05, 1, DEEP), /* GPIO - SSD1_PWR_EN */ + PAD_CFG_GPO(GPP_D06, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_D07, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_D08, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_D09, 0, DEEP), /* GPIO */ + PAD_CFG_NF(GPP_D10, NONE, DEEP, NF1), /* HDA_BCLK */ + PAD_CFG_NF(GPP_D11, NATIVE, DEEP, NF1), /* HDA_SYNC */ + PAD_CFG_NF(GPP_D12, NATIVE, DEEP, NF1), /* HDA_SDO */ + PAD_CFG_NF(GPP_D13, NATIVE, DEEP, NF1), /* HDA_SDI0 */ + PAD_CFG_GPO(GPP_D14, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_D15, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_D16, 0, DEEP), /* GPIO - GPIO_SPK_MUTE */ + PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), /* HDA_RST# */ + PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), /* SRCCLKREQ6# */ + PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), /* SRCCLKREQ7# */ + PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), /* SRCCLKREQ8# */ + PAD_CFG_NF(GPP_D21, NONE, DEEP, NF2), /* SRCCLKREQ5# */ + PAD_CFG_NF(GPP_D22, NATIVE, DEEP, NF1), /* n/a */ + PAD_CFG_NF(GPP_D23, NATIVE, DEEP, NF1), /* n/a */ + PAD_CFG_NF(GPP_BOOTHALT_B, UP_20K, DEEP, NF1), /* GPP_BOOTHALT_B */ + + /* ------- GPIO Group VGPIO ------- */ + PAD_CFG_GPO(GPP_VGPIO00, 1, DEEP), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_VGPIO04, NONE, DEEP, OFF, ACPI), /* GPIO */ + PAD_CFG_GPO(GPP_VGPIO05, 1, DEEP), /* GPIO */ + PAD_CFG_GPIO_BIDIRECT(GPP_VGPIO06, 0, NONE, DEEP, LEVEL, ACPI), /* GPIO */ + PAD_CFG_GPIO_BIDIRECT(GPP_VGPIO07, 0, NONE, DEEP, LEVEL, ACPI), /* GPIO */ + PAD_CFG_GPIO_BIDIRECT(GPP_VGPIO08, 0, NONE, DEEP, LEVEL, ACPI), /* GPIO */ + PAD_CFG_GPIO_BIDIRECT(GPP_VGPIO09, 0, NONE, DEEP, LEVEL, ACPI), /* GPIO */ + PAD_CFG_NF(GPP_VGPIO10, NONE, DEEP, NF1), /* GPP_VGPIO10 */ + PAD_CFG_NF(GPP_VGPIO11, NONE, DEEP, NF1), /* GPP_VGPIO11 */ + PAD_CFG_NF(GPP_VGPIO12, NONE, DEEP, NF1), /* GPP_VGPIO12 */ + PAD_CFG_NF(GPP_VGPIO13, NONE, DEEP, NF1), /* GPP_VGPIO13 */ + PAD_CFG_GPIO_BIDIRECT(GPP_VGPIO18, 0, NONE, DEEP, LEVEL, ACPI), /* GPIO */ + PAD_CFG_GPIO_BIDIRECT(GPP_VGPIO19, 0, NONE, DEEP, LEVEL, ACPI), /* GPIO */ + PAD_CFG_GPIO_BIDIRECT(GPP_VGPIO20, 0, NONE, DEEP, LEVEL, ACPI), /* GPIO */ + PAD_CFG_GPIO_BIDIRECT(GPP_VGPIO21, 0, NONE, DEEP, LEVEL, ACPI), /* GPIO */ + PAD_CFG_NF(GPP_VGPIO22, NONE, DEEP, NF1), /* GPP_VGPIO22 */ + PAD_CFG_NF(GPP_VGPIO23, NONE, DEEP, NF1), /* GPP_VGPIO23 */ + PAD_CFG_NF(GPP_VGPIO24, NONE, DEEP, NF1), /* GPP_VGPIO24 */ + PAD_CFG_NF(GPP_VGPIO25, NONE, DEEP, NF1), /* GPP_VGPIO25 */ + PAD_CFG_NF(GPP_VGPIO30, NONE, DEEP, NF3), /* RESERVED */ + PAD_CFG_NF(GPP_VGPIO31, NONE, DEEP, NF3), /* RESERVED */ + PAD_CFG_NF(GPP_VGPIO32, NONE, DEEP, NF3), /* RESERVED */ + PAD_CFG_NF(GPP_VGPIO33, NONE, DEEP, NF3), /* RESERVED */ + PAD_CFG_NF(GPP_VGPIO34, NONE, DEEP, NF1), /* GPP_VGPIO34 */ + PAD_CFG_NF(GPP_VGPIO35, NONE, DEEP, NF1), /* GPP_VGPIO35 */ + PAD_CFG_NF(GPP_VGPIO36, NONE, DEEP, NF1), /* GPP_VGPIO36 */ + PAD_CFG_NF(GPP_VGPIO37, NONE, DEEP, NF1), /* GPP_VGPIO37 */ + PAD_CFG_NF(GPP_VGPIO40, NONE, DEEP, NF2), /* RESERVED */ + PAD_CFG_NF(GPP_VGPIO41, NONE, DEEP, NF2), /* RESERVED */ + PAD_CFG_NF(GPP_VGPIO42, NONE, DEEP, NF2), /* RESERVED */ + PAD_CFG_NF(GPP_VGPIO43, NONE, DEEP, NF2), /* RESERVED */ + PAD_CFG_NF(GPP_VGPIO44, NONE, DEEP, NF1), /* GPP_VGPIO44 */ + PAD_CFG_NF(GPP_VGPIO45, NONE, DEEP, NF1), /* GPP_VGPIO45 */ + PAD_CFG_NF(GPP_VGPIO46, NONE, DEEP, NF1), /* GPP_VGPIO46 */ + PAD_CFG_NF(GPP_VGPIO47, NONE, DEEP, NF1), /* GPP_VGPIO47 */ +}; + +#define DGPU_RST_N GPP_B09 +#define DGPU_PWR_EN GPP_D03 +#define DGPU_PWRGD GPP_C15 + +/* Pad configuration was generated automatically using intelp2m utility */ +void variant_configure_gpios(void) +{ + bool result; + + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); + + /* dGPU power on sequence */ + mdelay(4); + gpio_set(DGPU_PWR_EN, 1); + result = wait_ms(200, gpio_get(DGPU_PWRGD) == 1); + if (result) { + printk(BIOS_INFO, "dGPU powered on\n"); + gpio_set(DGPU_RST_N, 1); + } else { + printk(BIOS_ERR, "dGPU failed to power on, turning off\n"); + gpio_set(DGPU_PWR_EN, 0); + } + mdelay(50); +} diff --git a/src/mainboard/novacustom/mtl-h/variants/dgpu/hda_verb.c b/src/mainboard/novacustom/mtl-h/variants/dgpu/hda_verb.c new file mode 100644 index 0000000..376ed9d --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/variants/dgpu/hda_verb.c @@ -0,0 +1,87 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <device/azalia_device.h> +#include <gpio.h> + +const u32 cim_verb_data[] = { + /* Realtek, ALC245 */ + 0x10ec0245, /* Vendor ID */ + 0x1558a741, /* Subsystem ID */ + 30, /* Number of entries */ + AZALIA_SUBVENDOR(0, 0x1558a741), + AZALIA_RESET(1), + + 0x1271C30, 0x1271D01, 0x1271EA6, 0x1271F90, + 0x1371C00, 0x1371D00, 0x1371E00, 0x1371F40, + 0x1871CF0, 0x1871D11, 0x1871E11, 0x1871F41, + 0x1971CF0, 0x1971D11, 0x1971E11, 0x1971F41, + 0x1A71CF0, 0x1A71D11, 0x1A71E11, 0x1A71F41, + 0x1B71CF0, 0x1B71D11, 0x1B71E11, 0x1B71F41, + 0x1D71C2D, 0x1D71D9B, 0x1D71E68, 0x1D71F40, + 0x1E71CF0, 0x1E71D11, 0x1E71E11, 0x1E71F41, + 0x2171C20, 0x2171D10, 0x2171E21, 0x2171F04, + 0x5B50006, 0x5B40011, 0x205001A, 0x204810B, + 0x205004A, 0x2042010, 0x2050038, 0x2044909, + 0x5C50000, 0x5C43D82, 0x5C50000, 0x5C43D82, + 0x5350000, 0x534201A, 0x5350000, 0x534201A, + 0x535001D, 0x5340800, 0x535001E, 0x5340800, + 0x5350003, 0x5341EC4, 0x5350004, 0x5340000, + 0x5450000, 0x5442000, 0x545001D, 0x5440800, + 0x545001E, 0x5440800, 0x5450003, 0x5441EC4, + 0x5450004, 0x5440000, 0x5350000, 0x534A01A, + 0x205003C, 0x204F175, 0x205003C, 0x204F135, + 0x2050040, 0x2048800, 0x5A50001, 0x5A4001F, + 0x2050010, 0x2040020, 0x2050010, 0x2040020, + 0x170500, 0x170500, 0x5A50004, 0x5A40113, + 0x2050008, 0x2046A8C, 0x2050076, 0x204F000, + 0x205000E, 0x20465C0, 0x2050033, 0x2048580, + 0x2050069, 0x204FDA8, 0x2050068, 0x2040000, + 0x2050003, 0x2040002, 0x2050069, 0x2040000, + 0x2050068, 0x2040001, 0x205002E, 0x204290E, + 0x2050010, 0x2040020, 0x2050010, 0x2040020, + + /* Intel Meteor Lake HDMI */ + 0x8086281d, /* Vendor ID */ + 0x80860101, /* Subsystem ID */ + 10, /* Number of entries */ + AZALIA_SUBVENDOR(2, 0x80860101), + AZALIA_PIN_CFG(2, 0x04, 0x18560010), + AZALIA_PIN_CFG(2, 0x06, 0x18560010), + AZALIA_PIN_CFG(2, 0x08, 0x18560010), + AZALIA_PIN_CFG(2, 0x0a, 0x18560010), + AZALIA_PIN_CFG(2, 0x0b, 0x18560010), + AZALIA_PIN_CFG(2, 0x0c, 0x18560010), + AZALIA_PIN_CFG(2, 0x0d, 0x18560010), + AZALIA_PIN_CFG(2, 0x0e, 0x18560010), + AZALIA_PIN_CFG(2, 0x0f, 0x18560010), +}; + +const u32 pc_beep_verbs[] = {}; + +AZALIA_ARRAY_SIZES; + +static const u32 smartamp_verbs[] = { + 0x1471CF0, 0x1471D11, 0x1471E11, 0x1471F41, + 0x1771C10, 0x1771D01, 0x1771E17, 0x1771F90, +}; + +static const u32 no_smartamp_verbs[] = { + 0x1471C10, 0x1471D01, 0x1471E17, 0x1471F90, + 0x1771C11, 0x1771D01, 0x1771E17, 0x1771F90, + 0x205006B, 0x204A390, 0x205006B, 0x204A390, + 0x205006C, 0x2040C9E, 0x205006D, 0x2040C00, +}; + +void mainboard_azalia_program_runtime_verbs(u8 *base, u32 viddid) +{ + if (gpio_get(GPP_E00)) { + printk(BIOS_INFO, "Normal amp detected\n"); + azalia_program_verb_table(base, no_smartamp_verbs, + ARRAY_SIZE(no_smartamp_verbs)); + } else { + printk(BIOS_INFO, "Smart amp detected\n"); + azalia_program_verb_table(base, smartamp_verbs, + ARRAY_SIZE(smartamp_verbs)); + } +} diff --git a/src/mainboard/novacustom/mtl-h/variants/dgpu/overridetree.cb b/src/mainboard/novacustom/mtl-h/variants/dgpu/overridetree.cb new file mode 100644 index 0000000..3c60a20 --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/variants/dgpu/overridetree.cb @@ -0,0 +1,75 @@ +chip soc/intel/meteorlake + # Power limits, + # PsysPL2, PsysPL3, PL4 are configured by EC at runtime + register "power_limits_config[MTL_P_682_482_CORE]" = "{ + .tdp_pl1_override = 35, + .tdp_pl2_override = 64, + .tdp_pl4 = 120, + .psys_pmax = 180, + }" + + # MTL SOC has additional setting for PsysPmax + register "psys_pmax_watts" = "180" + + device domain 0 on + subsystemid 0x1558 0xa741 inherit + device ref pcie_rp12 on # PEG + register "pcie_rp[PCH_RP(12)]" = "{ + .clk_src = 6, + .clk_req = 6, + .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_DETECT, + }" + device pci 00.0 on + subsystemid 0x1558 0xa761 + end + end + device ref igpu on + register "ddi_port_A_config" = "1" + register "ddi_ports_config" = "{ + [DDI_PORT_A] = DDI_ENABLE_HPD, /* eDP */ + }" + end + device ref i2c0 on # Touchpad + register "serial_io_i2c_mode[PchSerialIoIndexI2C0]" = "PchSerialIoPci" + chip drivers/i2c/hid + register "generic.hid" = ""ELAN0412"" + register "generic.desc" = ""ELAN Touchpad"" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A17)" + register "generic.detect" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 15 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""FTCS1000"" + register "generic.desc" = ""FocalTech Touchpad"" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A17)" + register "generic.detect" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 38 on end + end + end + device ref i2c4 on # ANX7443 USB-C Retimer + register "serial_io_i2c_mode[PchSerialIoIndexI2C4]" = "PchSerialIoPci" + end + device ref i2c5 on # TAS5825M SmartAmp + register "serial_io_i2c_mode[PchSerialIoIndexI2C5]" = "PchSerialIoPci" + chip drivers/i2c/tas5825m + register "id" = "0" + device i2c 4e on end + end + end + device ref pcie_rp5 on # GLAN + register "pcie_rp[PCH_RP(5)]" = "{ + .clk_src = 2, + .clk_req = 2, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_V11)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A20)" + register "srcclk_pin" = "2" + device generic 0 on end + end + end + end +end diff --git a/src/mainboard/novacustom/mtl-h/variants/dgpu/ramstage.c b/src/mainboard/novacustom/mtl-h/variants/dgpu/ramstage.c new file mode 100644 index 0000000..adff672 --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/variants/dgpu/ramstage.c @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <mainboard/variants.h> +#include <gpio.h> + +void variant_devtree_update(void) +{ + struct device *i2c_amp_dev = pcidev_on_root(0x19, 1); + if (i2c_amp_dev) + i2c_amp_dev->enabled = !gpio_get(GPP_E00); +} diff --git a/src/mainboard/novacustom/mtl-h/variants/dgpu/tas5825m.c b/src/mainboard/novacustom/mtl-h/variants/dgpu/tas5825m.c new file mode 100644 index 0000000..5e95c4b --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/variants/dgpu/tas5825m.c @@ -0,0 +1,2396 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <delay.h> +#include <drivers/i2c/tas5825m/tas5825m.h> + +/* + * This code was auto-generated using extract.rs from + * https://github.com/system76/smart-amp + */ + +int tas5825m_setup(struct device *dev, int id) +{ + int res; + + res = tas5825m_set_book(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x03, 0x02); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x01, 0x11); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_book(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x03, 0x02); + if (res < 0) + return res; + + mdelay(5); + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_book(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x03, 0x12); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_book(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x48, 0x0C); + if (res < 0) + return res; + + res = tas5825m_set_book(dev, 0x64); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x01); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0xFE, 0x00, 0x40, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x50, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0x82, 0x00, 0x93, 0x00, 0xFC, 0x00, 0x00, + 0x8F, 0x00, 0xFF, 0xEF, 0x84, 0x49, 0x03, 0x27, + 0x84, 0x02, 0x04, 0x06, 0x02, 0x60, 0x00, 0x01, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x02); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x02, 0x70, 0x00, 0x06, 0x02, 0x78, 0x00, 0x05, + 0x02, 0x68, 0x00, 0x02, 0x02, 0x28, 0x03, 0x4D, + 0x84, 0x2A, 0x04, 0x00, 0xE2, 0x57, 0x91, 0x9F, + 0x84, 0x82, 0x20, 0xE0, 0x84, 0x82, 0x04, 0x01, + 0xF0, 0x1C, 0x31, 0xA0, 0xF0, 0x1C, 0x31, 0xA1, + 0xF0, 0x1C, 0x31, 0xA2, 0xF0, 0x1F, 0x31, 0xA3, + 0xE4, 0x00, 0x11, 0xA6, 0x80, 0x27, 0x80, 0xE1, + 0xF4, 0x00, 0x11, 0xA4, 0xF4, 0x1D, 0x31, 0xA5, + 0xF4, 0x1C, 0x31, 0xA7, 0xF4, 0x1F, 0x31, 0xA8, + 0x02, 0x78, 0x00, 0x03, 0xE2, 0x68, 0xF1, 0xC3, + 0x80, 0x67, 0x80, 0xE9, 0x84, 0x4B, 0x03, 0x27, + 0x02, 0x70, 0x00, 0x04, 0x84, 0x41, 0x03, 0x37, + 0x80, 0x07, 0x00, 0x80, 0xE0, 0x00, 0x11, 0xA9, + 0x84, 0x82, 0x00, 0xE0, 0x8E, 0xFC, 0x04, 0x10, + 0xF0, 0x1C, 0x11, 0xAA, 0xF0, 0x1C, 0x11, 0xAB, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x03); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0xF0, 0x1C, 0x11, 0xAC, 0xF0, 0x1F, 0x11, 0xAD, + 0x86, 0xA1, 0x01, 0xC2, 0x80, 0x27, 0x80, 0xE8, + 0x60, 0x00, 0x00, 0x00, 0x84, 0x43, 0x03, 0x37, + 0x80, 0x00, 0x00, 0x81, 0x0D, 0x00, 0x10, 0x20, + 0x84, 0x51, 0x03, 0x3E, 0x08, 0x44, 0x26, 0x30, + 0x84, 0xC3, 0x03, 0x47, 0x84, 0xC2, 0x40, 0xE0, + 0x8C, 0xFF, 0x03, 0x23, 0xE0, 0x10, 0x11, 0xB3, + 0xF0, 0x1C, 0x51, 0xB4, 0xF0, 0x1C, 0x51, 0xB5, + 0xF0, 0x1C, 0x51, 0xB6, 0xF0, 0x1F, 0x51, 0xB7, + 0x86, 0xA1, 0x01, 0xC6, 0x80, 0x27, 0x80, 0xEA, + 0x84, 0x53, 0x03, 0x3E, 0x84, 0x82, 0x04, 0x05, + 0x84, 0x51, 0x03, 0x75, 0xE2, 0x6B, 0xC0, 0x00, + 0x80, 0x07, 0x00, 0x80, 0xE0, 0x80, 0x31, 0xB8, + 0x84, 0x82, 0x40, 0xE0, 0xF0, 0x1C, 0x51, 0xB9, + 0xF0, 0x1C, 0x51, 0xBA, 0xF0, 0x1C, 0x51, 0xBB, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x04); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0xF0, 0x1F, 0x51, 0xBC, 0x86, 0xA1, 0x01, 0xC5, + 0x80, 0x27, 0x80, 0xEA, 0x60, 0x00, 0x00, 0x00, + 0x80, 0x00, 0x00, 0x81, 0x84, 0xA1, 0x03, 0x4F, + 0xE0, 0x80, 0xA0, 0x00, 0x01, 0x07, 0x11, 0x20, + 0x08, 0x44, 0x26, 0x30, 0x08, 0x00, 0x98, 0x4A, + 0x84, 0x53, 0x03, 0x75, 0x08, 0x00, 0x30, 0x48, + 0x02, 0xCA, 0x00, 0x01, 0x08, 0x60, 0x26, 0x32, + 0x84, 0x51, 0x03, 0x45, 0xE4, 0x10, 0x40, 0x00, + 0x80, 0x40, 0xC0, 0x82, 0x84, 0xC2, 0x40, 0xE0, + 0x84, 0xC3, 0x03, 0x5E, 0x08, 0x00, 0x50, 0x48, + 0xE0, 0x10, 0x11, 0xBD, 0x02, 0xC2, 0x00, 0x02, + 0x08, 0x60, 0x06, 0x12, 0x84, 0xD3, 0x03, 0x4F, + 0xF0, 0x1C, 0x51, 0xBE, 0xF0, 0x1C, 0x51, 0xBF, + 0xF0, 0x1C, 0x51, 0xC0, 0xF0, 0x1F, 0x51, 0xC1, + 0x84, 0xA1, 0x03, 0x65, 0x80, 0x27, 0x80, 0xEA, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x05); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0xE0, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x83, + 0x08, 0x00, 0x98, 0x6B, 0x08, 0x00, 0x30, 0x68, + 0x84, 0x53, 0x03, 0x45, 0x08, 0x60, 0x26, 0x33, + 0x84, 0x51, 0x03, 0x25, 0xE4, 0x10, 0x60, 0x00, + 0x80, 0x40, 0xC0, 0x81, 0x02, 0x70, 0x00, 0x7F, + 0x08, 0x00, 0x50, 0x28, 0x08, 0x60, 0x06, 0x11, + 0x84, 0xCB, 0x03, 0x65, 0xE0, 0x10, 0x51, 0xC4, + 0x84, 0x80, 0x41, 0x00, 0x02, 0xA3, 0x00, 0x10, + 0xE4, 0x00, 0x00, 0x00, 0x84, 0xD0, 0x04, 0x01, + 0x84, 0xA2, 0x04, 0x03, 0x84, 0xD2, 0x50, 0x01, + 0x84, 0x53, 0x03, 0x25, 0x80, 0x00, 0xC4, 0x04, + 0x8F, 0x30, 0x00, 0x00, 0x88, 0x67, 0x03, 0x00, + 0xE4, 0x00, 0x11, 0x9B, 0xEE, 0x64, 0x60, 0x00, + 0x02, 0xD3, 0x00, 0x10, 0x88, 0x47, 0x00, 0x80, + 0x10, 0x00, 0x18, 0x02, 0x86, 0xC1, 0x01, 0x9D, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x06); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0xE0, 0x10, 0x31, 0xC7, 0x86, 0xC9, 0x01, 0x9E, + 0x80, 0x00, 0xC4, 0x02, 0x02, 0x50, 0x01, 0x9C, + 0x00, 0xFF, 0x21, 0x65, 0x00, 0xFC, 0x00, 0x00, + 0x02, 0x60, 0x00, 0x01, 0x02, 0x70, 0x00, 0x04, + 0x84, 0xC8, 0x04, 0x10, 0x84, 0x41, 0x03, 0x67, + 0x84, 0x51, 0x03, 0x6D, 0x84, 0xC0, 0x04, 0x02, + 0x04, 0x80, 0x91, 0x20, 0x08, 0x60, 0x26, 0x30, + 0x02, 0x78, 0x00, 0x03, 0x02, 0x68, 0x00, 0x02, + 0x0D, 0x00, 0x10, 0x10, 0x08, 0x60, 0x06, 0x12, + 0x84, 0x49, 0x03, 0x2F, 0xE0, 0x80, 0x71, 0xA9, + 0x02, 0x28, 0x03, 0x55, 0x84, 0x82, 0x00, 0xE0, + 0x84, 0x2A, 0x04, 0x00, 0xF0, 0x1C, 0x11, 0xAA, + 0xF0, 0x1C, 0x11, 0xAB, 0xF0, 0x1C, 0x11, 0xAC, + 0xF0, 0x1F, 0x11, 0xAD, 0x86, 0xA1, 0x01, 0xAE, + 0x80, 0x27, 0x80, 0xE8, 0x84, 0x82, 0x04, 0x07, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x07); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0xE0, 0x80, 0x60, 0x00, 0x84, 0x82, 0x40, 0xE0, + 0x84, 0x43, 0x03, 0x67, 0xF0, 0x1C, 0x51, 0xAF, + 0xF0, 0x1C, 0x51, 0xB0, 0xF0, 0x1C, 0x51, 0xB1, + 0xF0, 0x1F, 0x51, 0xB2, 0x02, 0x78, 0x00, 0x05, + 0x80, 0x27, 0x80, 0xEA, 0x84, 0x82, 0x04, 0x08, + 0x02, 0x70, 0x00, 0x06, 0x84, 0x53, 0x03, 0x6D, + 0x84, 0x80, 0x04, 0x07, 0xE0, 0x00, 0x00, 0x82, + 0xF0, 0x81, 0x00, 0x80, 0x80, 0x07, 0x12, 0xBC, + 0x86, 0xA1, 0x01, 0x9F, 0xE2, 0x57, 0xA0, 0x00, + 0x84, 0x82, 0x04, 0x09, 0x84, 0x82, 0x20, 0xE0, + 0xF0, 0x1C, 0x31, 0xA0, 0xF0, 0x1C, 0x31, 0xA1, + 0xF0, 0x1C, 0x31, 0xA2, 0xF0, 0x1F, 0x31, 0xA3, + 0xE4, 0x00, 0x11, 0xA6, 0x80, 0x27, 0x80, 0xE1, + 0xF4, 0x00, 0x11, 0xA4, 0xF4, 0x1D, 0x31, 0xA5, + 0xF4, 0x1C, 0x31, 0xA7, 0xF4, 0x1F, 0x31, 0xA8, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x08); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x02, 0x78, 0x00, 0x03, 0xE2, 0x6A, 0xF1, 0xC3, + 0x80, 0x67, 0x80, 0xE9, 0x84, 0x4B, 0x03, 0x2F, + 0x02, 0x70, 0x00, 0x04, 0x84, 0x59, 0x03, 0x3D, + 0x80, 0x07, 0x00, 0x80, 0xE0, 0x00, 0x11, 0xA9, + 0x84, 0x82, 0x60, 0xE0, 0x8E, 0xFC, 0x04, 0x10, + 0xF0, 0x1C, 0x71, 0xAA, 0xF0, 0x1C, 0x71, 0xAB, + 0xF0, 0x1C, 0x71, 0xAC, 0xF0, 0x1F, 0x71, 0xAD, + 0x86, 0xA1, 0x01, 0xC2, 0x80, 0x27, 0x80, 0xEB, + 0x60, 0x00, 0x00, 0x00, 0x84, 0x5B, 0x03, 0x3D, + 0x80, 0x00, 0x00, 0x81, 0x0D, 0x00, 0x10, 0x20, + 0x84, 0x59, 0x03, 0x3F, 0x08, 0x44, 0x26, 0x30, + 0x84, 0xC3, 0x03, 0x57, 0x84, 0xC2, 0x60, 0xE0, + 0xE0, 0x10, 0x11, 0xB3, 0xF0, 0x1C, 0x71, 0xB4, + 0xF0, 0x1C, 0x71, 0xB5, 0xF0, 0x1C, 0x71, 0xB6, + 0xF0, 0x1F, 0x71, 0xB7, 0x86, 0xA1, 0x01, 0xC6, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x09); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x80, 0x27, 0x80, 0xEB, 0x84, 0x5B, 0x03, 0x3F, + 0x84, 0x82, 0x04, 0x0D, 0x84, 0x41, 0x03, 0x76, + 0xE2, 0x6B, 0xE0, 0x00, 0x80, 0x07, 0x00, 0x80, + 0xE0, 0x81, 0x31, 0xB8, 0x84, 0x82, 0x00, 0xE0, + 0xF0, 0x1C, 0x11, 0xB9, 0xF0, 0x1C, 0x11, 0xBA, + 0xF0, 0x1C, 0x11, 0xBB, 0xF0, 0x1F, 0x11, 0xBC, + 0x86, 0xA1, 0x01, 0xC5, 0x80, 0x27, 0x80, 0xE8, + 0x60, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x81, + 0x84, 0xA1, 0x03, 0x5D, 0xE0, 0x81, 0xA0, 0x00, + 0x01, 0x07, 0x11, 0x20, 0x08, 0x44, 0x26, 0x30, + 0x08, 0x00, 0x98, 0x4A, 0x84, 0x43, 0x03, 0x76, + 0x08, 0x00, 0x30, 0x48, 0x02, 0xCA, 0x00, 0x01, + 0x08, 0x60, 0x26, 0x32, 0x84, 0x41, 0x03, 0x46, + 0xE4, 0x10, 0x40, 0x00, 0x80, 0x40, 0xC0, 0x82, + 0x84, 0xC2, 0x00, 0xE0, 0x84, 0xC3, 0x03, 0x5F, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0A); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x08, 0x00, 0x50, 0x48, 0xE0, 0x10, 0x11, 0xBD, + 0x02, 0xC2, 0x00, 0x02, 0x08, 0x60, 0x06, 0x12, + 0x84, 0xD3, 0x03, 0x5D, 0xF0, 0x1C, 0x11, 0xBE, + 0xF0, 0x1C, 0x11, 0xBF, 0xF0, 0x1C, 0x11, 0xC0, + 0xF0, 0x1F, 0x11, 0xC1, 0x84, 0xA1, 0x03, 0x66, + 0x80, 0x27, 0x80, 0xE8, 0xE0, 0x00, 0x00, 0x00, + 0x80, 0x07, 0x00, 0x83, 0x08, 0x00, 0x98, 0x6B, + 0x08, 0x00, 0x30, 0x68, 0x84, 0x43, 0x03, 0x46, + 0x08, 0x60, 0x26, 0x33, 0x84, 0x51, 0x03, 0x26, + 0xE4, 0x10, 0x60, 0x00, 0x80, 0x40, 0xC0, 0x81, + 0x02, 0x70, 0x00, 0x7F, 0x08, 0x00, 0x50, 0x28, + 0x08, 0x60, 0x06, 0x11, 0x8C, 0xFF, 0x03, 0x24, + 0x84, 0xCB, 0x03, 0x66, 0xE0, 0x10, 0x51, 0xC4, + 0x84, 0x80, 0x41, 0x00, 0x02, 0xA3, 0x00, 0x10, + 0xE4, 0x00, 0x00, 0x00, 0x84, 0xD0, 0x04, 0x09, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0B); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x84, 0xA2, 0x04, 0x0B, 0x84, 0xD2, 0x50, 0x01, + 0x84, 0x53, 0x03, 0x26, 0x80, 0x00, 0xC4, 0x0C, + 0x8F, 0x30, 0x00, 0x00, 0x88, 0x67, 0x03, 0x00, + 0xE4, 0x00, 0x11, 0x9B, 0xEE, 0x64, 0x80, 0x00, + 0x02, 0xD3, 0x00, 0x10, 0x88, 0x47, 0x00, 0x80, + 0x10, 0x00, 0x18, 0x02, 0x86, 0xC1, 0x01, 0x9D, + 0xE0, 0x10, 0x31, 0xC7, 0x86, 0xC9, 0x01, 0x9E, + 0x80, 0x00, 0xC4, 0x0A, 0x02, 0x50, 0x01, 0x9C, + 0x00, 0xFF, 0x21, 0x65, 0x00, 0xFC, 0x00, 0x00, + 0x02, 0x70, 0x00, 0x04, 0x02, 0x68, 0x00, 0x01, + 0x02, 0x60, 0x00, 0x03, 0x02, 0x78, 0x00, 0x02, + 0x84, 0x49, 0x03, 0x6E, 0x84, 0x41, 0x03, 0x6F, + 0x84, 0xC8, 0x04, 0x10, 0x84, 0xC0, 0x04, 0x0A, + 0x04, 0x81, 0x91, 0x20, 0x08, 0x60, 0x26, 0x30, + 0x0D, 0x00, 0x10, 0x10, 0x08, 0x60, 0x06, 0x12, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0C); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x84, 0x00, 0x04, 0x06, 0xE0, 0x81, 0x71, 0xA9, + 0x84, 0x82, 0x20, 0xE8, 0xF0, 0x1D, 0x31, 0xAA, + 0xF0, 0x1D, 0x31, 0xAB, 0xF0, 0x1D, 0x31, 0xAC, + 0xF0, 0x1C, 0x31, 0xAD, 0x86, 0xA1, 0x01, 0xAE, + 0x80, 0x27, 0x80, 0xF9, 0x84, 0x82, 0x04, 0x0E, + 0xE0, 0x81, 0x60, 0x00, 0x84, 0x82, 0x00, 0xE8, + 0x84, 0x4B, 0x03, 0x6E, 0xF0, 0x1D, 0x11, 0xAF, + 0xF0, 0x1D, 0x11, 0xB0, 0xF0, 0x1D, 0x11, 0xB1, + 0xF0, 0x1C, 0x11, 0xB2, 0x02, 0xA3, 0x00, 0x1A, + 0x80, 0x27, 0x80, 0xF8, 0x84, 0x82, 0x04, 0x0F, + 0xE0, 0x81, 0xC0, 0x00, 0xF0, 0x81, 0xE0, 0x80, + 0x84, 0x43, 0x03, 0x6F, 0x80, 0x07, 0x12, 0xBD, + 0x02, 0xC0, 0x00, 0x00, 0x00, 0xFC, 0x50, 0x00, + 0x8F, 0x00, 0x00, 0x11, 0x8F, 0x00, 0xFF, 0xFF, + 0x84, 0x58, 0x04, 0x01, 0x84, 0xC2, 0x04, 0x00, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0D); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x02, 0xC2, 0x60, 0x00, 0x84, 0xA0, 0x61, 0x00, + 0xE0, 0x20, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x40, 0x40, 0xA0, 0x00, 0x80, 0x00, 0xC0, 0x82, + 0x08, 0xFC, 0x48, 0x3A, 0x08, 0xFC, 0x18, 0x50, + 0x00, 0xFC, 0x00, 0x00, 0xE0, 0x10, 0x00, 0x00, + 0x86, 0xA0, 0x41, 0x00, 0x40, 0x47, 0x20, 0x00, + 0x80, 0x00, 0xC0, 0x83, 0x04, 0xE0, 0x3D, 0x1E, + 0x04, 0x80, 0x11, 0xE0, 0x08, 0x44, 0x26, 0x33, + 0x02, 0xCB, 0x00, 0x10, 0xE0, 0x10, 0x40, 0x83, + 0x08, 0x00, 0x28, 0x21, 0x84, 0xCA, 0x61, 0x00, + 0x80, 0x07, 0x00, 0x81, 0x0C, 0xE0, 0x2C, 0x09, + 0x84, 0xCA, 0x21, 0x00, 0x00, 0xFC, 0x50, 0x00, + 0x8F, 0x00, 0x00, 0x01, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x78); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x18); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x30, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x78); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x1B); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x03, 0x80, 0x00, 0x00, 0x04, 0x00, + 0x00, 0x00, 0x03, 0x28, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x6C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x1C); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x78); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x1C); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x03, 0x30, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x1C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x78); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x1C); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x03, 0x38, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x3C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x78); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x1C); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x03, 0x40, 0x00, 0x00, 0x03, 0x48, + 0x00, 0x00, 0x03, 0x50, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x54, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x78); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x1C); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x03, 0x58, 0x00, 0x00, 0x03, 0x60, + 0x00, 0x00, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x74, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x1D); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x78); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x1D); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x1C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x78); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x1D); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x3C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x1E); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x78); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x1E); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x03, 0x68, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x0C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x78); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x1E); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x03, 0x70, 0x00, 0x00, 0x03, 0x78, + 0x00, 0x00, 0x04, 0x80, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x24, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x78); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x1E); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x04, 0x88, 0x00, 0x00, 0x04, 0x90, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x44, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x8C); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x0E); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0xA7, 0x26, 0x4A, 0x7F, 0xFF, 0xFF, 0xFF, + 0x00, 0x20, 0xC4, 0x9C, 0x00, 0x20, 0xC4, 0x9C, + 0x00, 0x00, 0x68, 0xDB, 0x00, 0x00, 0xD1, 0xB7, + 0x00, 0x00, 0x68, 0xDB, 0x0F, 0xA4, 0xA8, 0xC1, + 0xF8, 0x59, 0x7F, 0x63, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x5C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0F); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x07, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x2F, 0xB7, 0xE9, + 0x00, 0x5F, 0x6F, 0xD2, 0x00, 0x2F, 0xB7, 0xE9, + 0x0B, 0x1E, 0x4F, 0x76, 0xFC, 0x23, 0x05, 0x54, + 0xFA, 0x41, 0x20, 0x5C, 0x0B, 0x7D, 0xBF, 0x48, + 0xFA, 0x41, 0x20, 0x5C, 0x0B, 0x1E, 0x4F, 0x76, + 0xFC, 0x23, 0x05, 0x54, 0x00, 0x04, 0x81, 0x6F, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x0F, 0x3F, 0xE5, 0xC9, 0xF8, 0xBB, 0x98, 0xC8, + 0x07, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x81, 0x6F, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x0F, 0x3F, 0xE5, 0xC9, 0xF8, 0xBB, 0x98, 0xC8, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x10); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x89, 0xA0, 0x27, 0x7F, 0xEC, 0x56, 0xD5, + 0x7F, 0xFC, 0xB9, 0x23, 0x00, 0x89, 0xA0, 0x27, + 0x7F, 0xEC, 0x56, 0xD5, 0x7F, 0xFC, 0xB9, 0x23, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x40, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_book(dev, 0x00); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x11, 0xFF, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x7D, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x01); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x51, 0x05); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x02); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x19, 0xDF); + if (res < 0) + return res; + + res = tas5825m_set_book(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x46, 0x11); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x02, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x53, 0x01); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x54, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_book(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x03, 0x02); + if (res < 0) + return res; + + res = tas5825m_set_book(dev, 0x8C); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x01); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x71, 0x94, 0x9A, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x2C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0A); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, + 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x64, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0B); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x80, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, + 0x00, 0x80, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x80, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + { + const uint8_t values[] = { + 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x57, 0x62, 0x00, 0x00, 0x00, 0x00, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x28, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0E); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x03, 0x69, 0xC5, 0x00, 0xFE, 0x16, 0xD5, + 0x00, 0x22, 0x1D, 0x95, 0x00, 0x03, 0x69, 0xC5, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x5C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0F); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x7F, 0xF9, 0x2C, 0x60, 0x04, 0x90, 0xB5, 0x11, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x5C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x07); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x80, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x64, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + { + const uint8_t values[] = { + 0x40, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x6C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0xAA); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x01); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x07, 0xF6, 0x71, 0xFB, 0xF0, 0x5E, 0x48, 0xD6, + 0x07, 0xAC, 0xA4, 0x5B, 0x0F, 0xA1, 0xB7, 0x2A, + 0xF8, 0x5C, 0xE9, 0xAA, 0x08, 0x00, 0x00, 0x00, + 0xF0, 0xBC, 0xDB, 0x13, 0x07, 0x4B, 0x87, 0x16, + 0x0F, 0x43, 0x24, 0xED, 0xF8, 0xB4, 0x78, 0xEA, + 0x08, 0x00, 0x00, 0x00, 0xF1, 0x2E, 0x37, 0x44, + 0x06, 0xE6, 0xAE, 0x6C, 0x0E, 0xD1, 0xC8, 0xBC, + 0xF9, 0x19, 0x51, 0x94, 0x08, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x30, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x02); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x07, 0xE3, 0xB6, 0x0E, + 0xF0, 0x38, 0x93, 0xE5, 0x07, 0xE3, 0xB6, 0x0E, + 0x0F, 0xC7, 0x37, 0xC3, 0xF8, 0x38, 0x5F, 0x8D, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x03); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x07, 0xE7, 0xF3, 0x30, 0xF0, 0x30, 0x19, 0xA1, + 0x07, 0xE7, 0xF3, 0x30, 0x0F, 0xCF, 0xB1, 0xEB, + 0xF8, 0x2F, 0xE5, 0x2D, 0x07, 0xEF, 0xD5, 0xCD, + 0xF0, 0x20, 0x54, 0x66, 0x07, 0xEF, 0xD5, 0xCD, + 0x0F, 0xDF, 0x76, 0xF1, 0xF8, 0x20, 0x1F, 0xBE, + 0x07, 0xF8, 0xC3, 0x5E, 0xF0, 0x17, 0xB1, 0xEA, + 0x07, 0xEF, 0xAD, 0x9B, 0x0F, 0xE8, 0x4E, 0x16, + 0xF8, 0x17, 0x8F, 0x07, 0x08, 0x06, 0x13, 0x6A, + 0xF0, 0x0B, 0x9D, 0x15, 0x07, 0xEE, 0x72, 0x7F, + 0x0F, 0xF4, 0x3F, 0x7D, 0xF8, 0x0B, 0x56, 0xA9, + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x04); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x05); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x07, 0xE3, 0xB6, 0x0E, 0xF0, 0x38, 0x93, 0xE5, + 0x07, 0xE3, 0xB6, 0x0E, 0x0F, 0xC7, 0x37, 0xC3, + 0xF8, 0x38, 0x5F, 0x8D, 0x07, 0xE7, 0xF3, 0x30, + 0xF0, 0x30, 0x19, 0xA1, 0x07, 0xE7, 0xF3, 0x30, + 0x0F, 0xCF, 0xB1, 0xEB, 0xF8, 0x2F, 0xE5, 0x2D, + 0x07, 0xEF, 0xD5, 0xCD, 0xF0, 0x20, 0x54, 0x66, + 0x07, 0xEF, 0xD5, 0xCD, 0x0F, 0xDF, 0x76, 0xF1, + 0xF8, 0x20, 0x1F, 0xBE, 0x07, 0xF8, 0xC3, 0x5E, + 0xF0, 0x17, 0xB1, 0xEA, 0x07, 0xEF, 0xAD, 0x9B, + 0x0F, 0xE8, 0x4E, 0x16, 0xF8, 0x17, 0x8F, 0x07, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x06); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x08, 0x06, 0x13, 0x6A, 0xF0, 0x0B, 0x9D, 0x15, + 0x07, 0xEE, 0x72, 0x7F, 0x0F, 0xF4, 0x3F, 0x7D, + 0xF8, 0x0B, 0x56, 0xA9, 0x08, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0E); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x82, 0xB3, 0xD2, 0xFF, 0x00, 0xA4, 0x7A, + 0x00, 0x7C, 0xCA, 0xB8, 0x0F, 0xF6, 0xBE, 0xFB, + 0xF8, 0x09, 0x1E, 0x02, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x6C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0F); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0xFF, 0xF4, 0x49, 0x81, + 0xFF, 0xE8, 0x93, 0x02, 0xFF, 0xF4, 0x49, 0x81, + 0x0D, 0x94, 0x7A, 0x64, 0xFA, 0x3C, 0xAB, 0xA1, + 0x06, 0xD5, 0xF3, 0xB1, 0xF2, 0x54, 0x18, 0x9F, + 0x06, 0xD5, 0xF3, 0xB1, 0x0D, 0x94, 0x7A, 0x64, + 0xFA, 0x3C, 0xAB, 0xA1, 0x00, 0x00, 0x38, 0xE4, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x0F, 0xD5, 0x55, 0x55, 0xF8, 0x2A, 0x71, 0xC7, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x30, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x60, 0x02); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x62, 0x09); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x4C, 0x40); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x03, 0x03); + if (res < 0) + return res; + + res = tas5825m_set_book(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x78, 0x80); + if (res < 0) + return res; + + res = tas5825m_set_book(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x03, 0x02); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x01, 0x11); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_book(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x03, 0x02); + if (res < 0) + return res; + + mdelay(5); + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_book(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x03, 0x12); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_book(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x48, 0x0C); + if (res < 0) + return res; + + res = tas5825m_set_book(dev, 0x64); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x01); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0xFE, 0x00, 0x40, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x50, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0x82, 0x00, 0x93, 0x00, 0xFC, 0x00, 0x00, + 0x8F, 0x00, 0xFF, 0xEF, 0x84, 0x49, 0x03, 0x27, + 0x84, 0x02, 0x04, 0x06, 0x02, 0x60, 0x00, 0x01, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x02); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x02, 0x70, 0x00, 0x06, 0x02, 0x78, 0x00, 0x05, + 0x02, 0x68, 0x00, 0x02, 0x02, 0x28, 0x03, 0x4D, + 0x84, 0x2A, 0x04, 0x00, 0xE2, 0x57, 0x91, 0x9F, + 0x84, 0x82, 0x20, 0xE0, 0x84, 0x82, 0x04, 0x01, + 0xF0, 0x1C, 0x31, 0xA0, 0xF0, 0x1C, 0x31, 0xA1, + 0xF0, 0x1C, 0x31, 0xA2, 0xF0, 0x1F, 0x31, 0xA3, + 0xE4, 0x00, 0x11, 0xA6, 0x80, 0x27, 0x80, 0xE1, + 0xF4, 0x00, 0x11, 0xA4, 0xF4, 0x1D, 0x31, 0xA5, + 0xF4, 0x1C, 0x31, 0xA7, 0xF4, 0x1F, 0x31, 0xA8, + 0x02, 0x78, 0x00, 0x03, 0xE2, 0x68, 0xF1, 0xC3, + 0x80, 0x67, 0x80, 0xE9, 0x84, 0x4B, 0x03, 0x27, + 0x02, 0x70, 0x00, 0x04, 0x84, 0x41, 0x03, 0x37, + 0x80, 0x07, 0x00, 0x80, 0xE0, 0x00, 0x11, 0xA9, + 0x84, 0x82, 0x00, 0xE0, 0x8E, 0xFC, 0x04, 0x10, + 0xF0, 0x1C, 0x11, 0xAA, 0xF0, 0x1C, 0x11, 0xAB, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x03); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0xF0, 0x1C, 0x11, 0xAC, 0xF0, 0x1F, 0x11, 0xAD, + 0x86, 0xA1, 0x01, 0xC2, 0x80, 0x27, 0x80, 0xE8, + 0x60, 0x00, 0x00, 0x00, 0x84, 0x43, 0x03, 0x37, + 0x80, 0x00, 0x00, 0x81, 0x0D, 0x00, 0x10, 0x20, + 0x84, 0x51, 0x03, 0x3E, 0x08, 0x44, 0x26, 0x30, + 0x84, 0xC3, 0x03, 0x47, 0x84, 0xC2, 0x40, 0xE0, + 0x8C, 0xFF, 0x03, 0x23, 0xE0, 0x10, 0x11, 0xB3, + 0xF0, 0x1C, 0x51, 0xB4, 0xF0, 0x1C, 0x51, 0xB5, + 0xF0, 0x1C, 0x51, 0xB6, 0xF0, 0x1F, 0x51, 0xB7, + 0x86, 0xA1, 0x01, 0xC6, 0x80, 0x27, 0x80, 0xEA, + 0x84, 0x53, 0x03, 0x3E, 0x84, 0x82, 0x04, 0x05, + 0x84, 0x51, 0x03, 0x75, 0xE2, 0x6B, 0xC0, 0x00, + 0x80, 0x07, 0x00, 0x80, 0xE0, 0x80, 0x31, 0xB8, + 0x84, 0x82, 0x40, 0xE0, 0xF0, 0x1C, 0x51, 0xB9, + 0xF0, 0x1C, 0x51, 0xBA, 0xF0, 0x1C, 0x51, 0xBB, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x04); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0xF0, 0x1F, 0x51, 0xBC, 0x86, 0xA1, 0x01, 0xC5, + 0x80, 0x27, 0x80, 0xEA, 0x60, 0x00, 0x00, 0x00, + 0x80, 0x00, 0x00, 0x81, 0x84, 0xA1, 0x03, 0x4F, + 0xE0, 0x80, 0xA0, 0x00, 0x01, 0x07, 0x11, 0x20, + 0x08, 0x44, 0x26, 0x30, 0x08, 0x00, 0x98, 0x4A, + 0x84, 0x53, 0x03, 0x75, 0x08, 0x00, 0x30, 0x48, + 0x02, 0xCA, 0x00, 0x01, 0x08, 0x60, 0x26, 0x32, + 0x84, 0x51, 0x03, 0x45, 0xE4, 0x10, 0x40, 0x00, + 0x80, 0x40, 0xC0, 0x82, 0x84, 0xC2, 0x40, 0xE0, + 0x84, 0xC3, 0x03, 0x5E, 0x08, 0x00, 0x50, 0x48, + 0xE0, 0x10, 0x11, 0xBD, 0x02, 0xC2, 0x00, 0x02, + 0x08, 0x60, 0x06, 0x12, 0x84, 0xD3, 0x03, 0x4F, + 0xF0, 0x1C, 0x51, 0xBE, 0xF0, 0x1C, 0x51, 0xBF, + 0xF0, 0x1C, 0x51, 0xC0, 0xF0, 0x1F, 0x51, 0xC1, + 0x84, 0xA1, 0x03, 0x65, 0x80, 0x27, 0x80, 0xEA, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x05); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0xE0, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x83, + 0x08, 0x00, 0x98, 0x6B, 0x08, 0x00, 0x30, 0x68, + 0x84, 0x53, 0x03, 0x45, 0x08, 0x60, 0x26, 0x33, + 0x84, 0x51, 0x03, 0x25, 0xE4, 0x10, 0x60, 0x00, + 0x80, 0x40, 0xC0, 0x81, 0x02, 0x70, 0x00, 0x7F, + 0x08, 0x00, 0x50, 0x28, 0x08, 0x60, 0x06, 0x11, + 0x84, 0xCB, 0x03, 0x65, 0xE0, 0x10, 0x51, 0xC4, + 0x84, 0x80, 0x41, 0x00, 0x02, 0xA3, 0x00, 0x10, + 0xE4, 0x00, 0x00, 0x00, 0x84, 0xD0, 0x04, 0x01, + 0x84, 0xA2, 0x04, 0x03, 0x84, 0xD2, 0x50, 0x01, + 0x84, 0x53, 0x03, 0x25, 0x80, 0x00, 0xC4, 0x04, + 0x8F, 0x30, 0x00, 0x00, 0x88, 0x67, 0x03, 0x00, + 0xE4, 0x00, 0x11, 0x9B, 0xEE, 0x64, 0x60, 0x00, + 0x02, 0xD3, 0x00, 0x10, 0x88, 0x47, 0x00, 0x80, + 0x10, 0x00, 0x18, 0x02, 0x86, 0xC1, 0x01, 0x9D, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x06); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0xE0, 0x10, 0x31, 0xC7, 0x86, 0xC9, 0x01, 0x9E, + 0x80, 0x00, 0xC4, 0x02, 0x02, 0x50, 0x01, 0x9C, + 0x00, 0xFF, 0x21, 0x65, 0x00, 0xFC, 0x00, 0x00, + 0x02, 0x60, 0x00, 0x01, 0x02, 0x70, 0x00, 0x04, + 0x84, 0xC8, 0x04, 0x10, 0x84, 0x41, 0x03, 0x67, + 0x84, 0x51, 0x03, 0x6D, 0x84, 0xC0, 0x04, 0x02, + 0x04, 0x80, 0x91, 0x20, 0x08, 0x60, 0x26, 0x30, + 0x02, 0x78, 0x00, 0x03, 0x02, 0x68, 0x00, 0x02, + 0x0D, 0x00, 0x10, 0x10, 0x08, 0x60, 0x06, 0x12, + 0x84, 0x49, 0x03, 0x2F, 0xE0, 0x80, 0x71, 0xA9, + 0x02, 0x28, 0x03, 0x55, 0x84, 0x82, 0x00, 0xE0, + 0x84, 0x2A, 0x04, 0x00, 0xF0, 0x1C, 0x11, 0xAA, + 0xF0, 0x1C, 0x11, 0xAB, 0xF0, 0x1C, 0x11, 0xAC, + 0xF0, 0x1F, 0x11, 0xAD, 0x86, 0xA1, 0x01, 0xAE, + 0x80, 0x27, 0x80, 0xE8, 0x84, 0x82, 0x04, 0x07, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x07); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0xE0, 0x80, 0x60, 0x00, 0x84, 0x82, 0x40, 0xE0, + 0x84, 0x43, 0x03, 0x67, 0xF0, 0x1C, 0x51, 0xAF, + 0xF0, 0x1C, 0x51, 0xB0, 0xF0, 0x1C, 0x51, 0xB1, + 0xF0, 0x1F, 0x51, 0xB2, 0x02, 0x78, 0x00, 0x05, + 0x80, 0x27, 0x80, 0xEA, 0x84, 0x82, 0x04, 0x08, + 0x02, 0x70, 0x00, 0x06, 0x84, 0x53, 0x03, 0x6D, + 0x84, 0x80, 0x04, 0x07, 0xE0, 0x00, 0x00, 0x82, + 0xF0, 0x81, 0x00, 0x80, 0x80, 0x07, 0x12, 0xBC, + 0x86, 0xA1, 0x01, 0x9F, 0xE2, 0x57, 0xA0, 0x00, + 0x84, 0x82, 0x04, 0x09, 0x84, 0x82, 0x20, 0xE0, + 0xF0, 0x1C, 0x31, 0xA0, 0xF0, 0x1C, 0x31, 0xA1, + 0xF0, 0x1C, 0x31, 0xA2, 0xF0, 0x1F, 0x31, 0xA3, + 0xE4, 0x00, 0x11, 0xA6, 0x80, 0x27, 0x80, 0xE1, + 0xF4, 0x00, 0x11, 0xA4, 0xF4, 0x1D, 0x31, 0xA5, + 0xF4, 0x1C, 0x31, 0xA7, 0xF4, 0x1F, 0x31, 0xA8, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x08); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x02, 0x78, 0x00, 0x03, 0xE2, 0x6A, 0xF1, 0xC3, + 0x80, 0x67, 0x80, 0xE9, 0x84, 0x4B, 0x03, 0x2F, + 0x02, 0x70, 0x00, 0x04, 0x84, 0x59, 0x03, 0x3D, + 0x80, 0x07, 0x00, 0x80, 0xE0, 0x00, 0x11, 0xA9, + 0x84, 0x82, 0x60, 0xE0, 0x8E, 0xFC, 0x04, 0x10, + 0xF0, 0x1C, 0x71, 0xAA, 0xF0, 0x1C, 0x71, 0xAB, + 0xF0, 0x1C, 0x71, 0xAC, 0xF0, 0x1F, 0x71, 0xAD, + 0x86, 0xA1, 0x01, 0xC2, 0x80, 0x27, 0x80, 0xEB, + 0x60, 0x00, 0x00, 0x00, 0x84, 0x5B, 0x03, 0x3D, + 0x80, 0x00, 0x00, 0x81, 0x0D, 0x00, 0x10, 0x20, + 0x84, 0x59, 0x03, 0x3F, 0x08, 0x44, 0x26, 0x30, + 0x84, 0xC3, 0x03, 0x57, 0x84, 0xC2, 0x60, 0xE0, + 0xE0, 0x10, 0x11, 0xB3, 0xF0, 0x1C, 0x71, 0xB4, + 0xF0, 0x1C, 0x71, 0xB5, 0xF0, 0x1C, 0x71, 0xB6, + 0xF0, 0x1F, 0x71, 0xB7, 0x86, 0xA1, 0x01, 0xC6, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x09); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x80, 0x27, 0x80, 0xEB, 0x84, 0x5B, 0x03, 0x3F, + 0x84, 0x82, 0x04, 0x0D, 0x84, 0x41, 0x03, 0x76, + 0xE2, 0x6B, 0xE0, 0x00, 0x80, 0x07, 0x00, 0x80, + 0xE0, 0x81, 0x31, 0xB8, 0x84, 0x82, 0x00, 0xE0, + 0xF0, 0x1C, 0x11, 0xB9, 0xF0, 0x1C, 0x11, 0xBA, + 0xF0, 0x1C, 0x11, 0xBB, 0xF0, 0x1F, 0x11, 0xBC, + 0x86, 0xA1, 0x01, 0xC5, 0x80, 0x27, 0x80, 0xE8, + 0x60, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x81, + 0x84, 0xA1, 0x03, 0x5D, 0xE0, 0x81, 0xA0, 0x00, + 0x01, 0x07, 0x11, 0x20, 0x08, 0x44, 0x26, 0x30, + 0x08, 0x00, 0x98, 0x4A, 0x84, 0x43, 0x03, 0x76, + 0x08, 0x00, 0x30, 0x48, 0x02, 0xCA, 0x00, 0x01, + 0x08, 0x60, 0x26, 0x32, 0x84, 0x41, 0x03, 0x46, + 0xE4, 0x10, 0x40, 0x00, 0x80, 0x40, 0xC0, 0x82, + 0x84, 0xC2, 0x00, 0xE0, 0x84, 0xC3, 0x03, 0x5F, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0A); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x08, 0x00, 0x50, 0x48, 0xE0, 0x10, 0x11, 0xBD, + 0x02, 0xC2, 0x00, 0x02, 0x08, 0x60, 0x06, 0x12, + 0x84, 0xD3, 0x03, 0x5D, 0xF0, 0x1C, 0x11, 0xBE, + 0xF0, 0x1C, 0x11, 0xBF, 0xF0, 0x1C, 0x11, 0xC0, + 0xF0, 0x1F, 0x11, 0xC1, 0x84, 0xA1, 0x03, 0x66, + 0x80, 0x27, 0x80, 0xE8, 0xE0, 0x00, 0x00, 0x00, + 0x80, 0x07, 0x00, 0x83, 0x08, 0x00, 0x98, 0x6B, + 0x08, 0x00, 0x30, 0x68, 0x84, 0x43, 0x03, 0x46, + 0x08, 0x60, 0x26, 0x33, 0x84, 0x51, 0x03, 0x26, + 0xE4, 0x10, 0x60, 0x00, 0x80, 0x40, 0xC0, 0x81, + 0x02, 0x70, 0x00, 0x7F, 0x08, 0x00, 0x50, 0x28, + 0x08, 0x60, 0x06, 0x11, 0x8C, 0xFF, 0x03, 0x24, + 0x84, 0xCB, 0x03, 0x66, 0xE0, 0x10, 0x51, 0xC4, + 0x84, 0x80, 0x41, 0x00, 0x02, 0xA3, 0x00, 0x10, + 0xE4, 0x00, 0x00, 0x00, 0x84, 0xD0, 0x04, 0x09, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0B); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x84, 0xA2, 0x04, 0x0B, 0x84, 0xD2, 0x50, 0x01, + 0x84, 0x53, 0x03, 0x26, 0x80, 0x00, 0xC4, 0x0C, + 0x8F, 0x30, 0x00, 0x00, 0x88, 0x67, 0x03, 0x00, + 0xE4, 0x00, 0x11, 0x9B, 0xEE, 0x64, 0x80, 0x00, + 0x02, 0xD3, 0x00, 0x10, 0x88, 0x47, 0x00, 0x80, + 0x10, 0x00, 0x18, 0x02, 0x86, 0xC1, 0x01, 0x9D, + 0xE0, 0x10, 0x31, 0xC7, 0x86, 0xC9, 0x01, 0x9E, + 0x80, 0x00, 0xC4, 0x0A, 0x02, 0x50, 0x01, 0x9C, + 0x00, 0xFF, 0x21, 0x65, 0x00, 0xFC, 0x00, 0x00, + 0x02, 0x70, 0x00, 0x04, 0x02, 0x68, 0x00, 0x01, + 0x02, 0x60, 0x00, 0x03, 0x02, 0x78, 0x00, 0x02, + 0x84, 0x49, 0x03, 0x6E, 0x84, 0x41, 0x03, 0x6F, + 0x84, 0xC8, 0x04, 0x10, 0x84, 0xC0, 0x04, 0x0A, + 0x04, 0x81, 0x91, 0x20, 0x08, 0x60, 0x26, 0x30, + 0x0D, 0x00, 0x10, 0x10, 0x08, 0x60, 0x06, 0x12, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0C); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x84, 0x00, 0x04, 0x06, 0xE0, 0x81, 0x71, 0xA9, + 0x84, 0x82, 0x20, 0xE8, 0xF0, 0x1D, 0x31, 0xAA, + 0xF0, 0x1D, 0x31, 0xAB, 0xF0, 0x1D, 0x31, 0xAC, + 0xF0, 0x1C, 0x31, 0xAD, 0x86, 0xA1, 0x01, 0xAE, + 0x80, 0x27, 0x80, 0xF9, 0x84, 0x82, 0x04, 0x0E, + 0xE0, 0x81, 0x60, 0x00, 0x84, 0x82, 0x00, 0xE8, + 0x84, 0x4B, 0x03, 0x6E, 0xF0, 0x1D, 0x11, 0xAF, + 0xF0, 0x1D, 0x11, 0xB0, 0xF0, 0x1D, 0x11, 0xB1, + 0xF0, 0x1C, 0x11, 0xB2, 0x02, 0xA3, 0x00, 0x1A, + 0x80, 0x27, 0x80, 0xF8, 0x84, 0x82, 0x04, 0x0F, + 0xE0, 0x81, 0xC0, 0x00, 0xF0, 0x81, 0xE0, 0x80, + 0x84, 0x43, 0x03, 0x6F, 0x80, 0x07, 0x12, 0xBD, + 0x02, 0xC0, 0x00, 0x00, 0x00, 0xFC, 0x50, 0x00, + 0x8F, 0x00, 0x00, 0x11, 0x8F, 0x00, 0xFF, 0xFF, + 0x84, 0x58, 0x04, 0x01, 0x84, 0xC2, 0x04, 0x00, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0D); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x02, 0xC2, 0x60, 0x00, 0x84, 0xA0, 0x61, 0x00, + 0xE0, 0x20, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x40, 0x40, 0xA0, 0x00, 0x80, 0x00, 0xC0, 0x82, + 0x08, 0xFC, 0x48, 0x3A, 0x08, 0xFC, 0x18, 0x50, + 0x00, 0xFC, 0x00, 0x00, 0xE0, 0x10, 0x00, 0x00, + 0x86, 0xA0, 0x41, 0x00, 0x40, 0x47, 0x20, 0x00, + 0x80, 0x00, 0xC0, 0x83, 0x04, 0xE0, 0x3D, 0x1E, + 0x04, 0x80, 0x11, 0xE0, 0x08, 0x44, 0x26, 0x33, + 0x02, 0xCB, 0x00, 0x10, 0xE0, 0x10, 0x40, 0x83, + 0x08, 0x00, 0x28, 0x21, 0x84, 0xCA, 0x61, 0x00, + 0x80, 0x07, 0x00, 0x81, 0x0C, 0xE0, 0x2C, 0x09, + 0x84, 0xCA, 0x21, 0x00, 0x00, 0xFC, 0x50, 0x00, + 0x8F, 0x00, 0x00, 0x01, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x78); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x18); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x30, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x78); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x1B); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x03, 0x80, 0x00, 0x00, 0x04, 0x00, + 0x00, 0x00, 0x03, 0x28, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x6C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x1C); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x78); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x1C); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x03, 0x30, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x1C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x78); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x1C); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x03, 0x38, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x3C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x78); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x1C); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x03, 0x40, 0x00, 0x00, 0x03, 0x48, + 0x00, 0x00, 0x03, 0x50, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x54, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x78); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x1C); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x03, 0x58, 0x00, 0x00, 0x03, 0x60, + 0x00, 0x00, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x74, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x1D); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x78); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x1D); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x1C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x78); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x1D); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x3C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x1E); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x78); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x1E); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x03, 0x68, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x0C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x78); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x1E); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x03, 0x70, 0x00, 0x00, 0x03, 0x78, + 0x00, 0x00, 0x04, 0x80, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x24, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x78); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x1E); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x04, 0x88, 0x00, 0x00, 0x04, 0x90, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x44, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x8C); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x0E); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0xA7, 0x26, 0x4A, 0x7F, 0xFF, 0xFF, 0xFF, + 0x00, 0x20, 0xC4, 0x9C, 0x00, 0x20, 0xC4, 0x9C, + 0x00, 0x00, 0x68, 0xDB, 0x00, 0x00, 0xD1, 0xB7, + 0x00, 0x00, 0x68, 0xDB, 0x0F, 0xA4, 0xA8, 0xC1, + 0xF8, 0x59, 0x7F, 0x63, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x5C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0F); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x07, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x2F, 0xB7, 0xE9, + 0x00, 0x5F, 0x6F, 0xD2, 0x00, 0x2F, 0xB7, 0xE9, + 0x0B, 0x1E, 0x4F, 0x76, 0xFC, 0x23, 0x05, 0x54, + 0xFA, 0x41, 0x20, 0x5C, 0x0B, 0x7D, 0xBF, 0x48, + 0xFA, 0x41, 0x20, 0x5C, 0x0B, 0x1E, 0x4F, 0x76, + 0xFC, 0x23, 0x05, 0x54, 0x00, 0x04, 0x81, 0x6F, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x0F, 0x3F, 0xE5, 0xC9, 0xF8, 0xBB, 0x98, 0xC8, + 0x07, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x81, 0x6F, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x0F, 0x3F, 0xE5, 0xC9, 0xF8, 0xBB, 0x98, 0xC8, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x10); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x89, 0xA0, 0x27, 0x7F, 0xEC, 0x56, 0xD5, + 0x7F, 0xFC, 0xB9, 0x23, 0x00, 0x89, 0xA0, 0x27, + 0x7F, 0xEC, 0x56, 0xD5, 0x7F, 0xFC, 0xB9, 0x23, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x40, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_book(dev, 0x00); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x11, 0xFF, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x7D, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x01); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x51, 0x05); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x02); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x19, 0xDF); + if (res < 0) + return res; + + res = tas5825m_set_book(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x46, 0x11); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x02, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x53, 0x01); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x54, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_book(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x03, 0x02); + if (res < 0) + return res; + + res = tas5825m_set_book(dev, 0x8C); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x01); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x71, 0x94, 0x9A, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x2C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0A); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, + 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x64, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0B); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x80, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, + 0x00, 0x80, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x80, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + { + const uint8_t values[] = { + 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x57, 0x62, 0x00, 0x00, 0x00, 0x00, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x28, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0E); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x03, 0x69, 0xC5, 0x00, 0xFE, 0x16, 0xD5, + 0x00, 0x22, 0x1D, 0x95, 0x00, 0x03, 0x69, 0xC5, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x5C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0F); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x7F, 0xF9, 0x2C, 0x60, 0x04, 0x90, 0xB5, 0x11, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x5C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x07); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x80, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x64, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + { + const uint8_t values[] = { + 0x40, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x6C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0xAA); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x01); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x07, 0xF6, 0x71, 0xFB, 0xF0, 0x5E, 0x48, 0xD6, + 0x07, 0xAC, 0xA4, 0x5B, 0x0F, 0xA1, 0xB7, 0x2A, + 0xF8, 0x5C, 0xE9, 0xAA, 0x08, 0x00, 0x00, 0x00, + 0xF0, 0xBC, 0xDB, 0x13, 0x07, 0x4B, 0x87, 0x16, + 0x0F, 0x43, 0x24, 0xED, 0xF8, 0xB4, 0x78, 0xEA, + 0x08, 0x00, 0x00, 0x00, 0xF1, 0x2E, 0x37, 0x44, + 0x06, 0xE6, 0xAE, 0x6C, 0x0E, 0xD1, 0xC8, 0xBC, + 0xF9, 0x19, 0x51, 0x94, 0x08, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x30, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x02); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x07, 0xE3, 0xB6, 0x0E, + 0xF0, 0x38, 0x93, 0xE5, 0x07, 0xE3, 0xB6, 0x0E, + 0x0F, 0xC7, 0x37, 0xC3, 0xF8, 0x38, 0x5F, 0x8D, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x03); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x07, 0xE7, 0xF3, 0x30, 0xF0, 0x30, 0x19, 0xA1, + 0x07, 0xE7, 0xF3, 0x30, 0x0F, 0xCF, 0xB1, 0xEB, + 0xF8, 0x2F, 0xE5, 0x2D, 0x07, 0xEF, 0xD5, 0xCD, + 0xF0, 0x20, 0x54, 0x66, 0x07, 0xEF, 0xD5, 0xCD, + 0x0F, 0xDF, 0x76, 0xF1, 0xF8, 0x20, 0x1F, 0xBE, + 0x07, 0xF8, 0xC3, 0x5E, 0xF0, 0x17, 0xB1, 0xEA, + 0x07, 0xEF, 0xAD, 0x9B, 0x0F, 0xE8, 0x4E, 0x16, + 0xF8, 0x17, 0x8F, 0x07, 0x08, 0x06, 0x13, 0x6A, + 0xF0, 0x0B, 0x9D, 0x15, 0x07, 0xEE, 0x72, 0x7F, + 0x0F, 0xF4, 0x3F, 0x7D, 0xF8, 0x0B, 0x56, 0xA9, + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x04); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x05); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x07, 0xE3, 0xB6, 0x0E, 0xF0, 0x38, 0x93, 0xE5, + 0x07, 0xE3, 0xB6, 0x0E, 0x0F, 0xC7, 0x37, 0xC3, + 0xF8, 0x38, 0x5F, 0x8D, 0x07, 0xE7, 0xF3, 0x30, + 0xF0, 0x30, 0x19, 0xA1, 0x07, 0xE7, 0xF3, 0x30, + 0x0F, 0xCF, 0xB1, 0xEB, 0xF8, 0x2F, 0xE5, 0x2D, + 0x07, 0xEF, 0xD5, 0xCD, 0xF0, 0x20, 0x54, 0x66, + 0x07, 0xEF, 0xD5, 0xCD, 0x0F, 0xDF, 0x76, 0xF1, + 0xF8, 0x20, 0x1F, 0xBE, 0x07, 0xF8, 0xC3, 0x5E, + 0xF0, 0x17, 0xB1, 0xEA, 0x07, 0xEF, 0xAD, 0x9B, + 0x0F, 0xE8, 0x4E, 0x16, 0xF8, 0x17, 0x8F, 0x07, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x06); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x08, 0x06, 0x13, 0x6A, 0xF0, 0x0B, 0x9D, 0x15, + 0x07, 0xEE, 0x72, 0x7F, 0x0F, 0xF4, 0x3F, 0x7D, + 0xF8, 0x0B, 0x56, 0xA9, 0x08, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0E); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x82, 0xB3, 0xD2, 0xFF, 0x00, 0xA4, 0x7A, + 0x00, 0x7C, 0xCA, 0xB8, 0x0F, 0xF6, 0xBE, 0xFB, + 0xF8, 0x09, 0x1E, 0x02, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x6C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0F); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0xFF, 0xF4, 0x49, 0x81, + 0xFF, 0xE8, 0x93, 0x02, 0xFF, 0xF4, 0x49, 0x81, + 0x0D, 0x94, 0x7A, 0x64, 0xFA, 0x3C, 0xAB, 0xA1, + 0x06, 0xD5, 0xF3, 0xB1, 0xF2, 0x54, 0x18, 0x9F, + 0x06, 0xD5, 0xF3, 0xB1, 0x0D, 0x94, 0x7A, 0x64, + 0xFA, 0x3C, 0xAB, 0xA1, 0x00, 0x00, 0x38, 0xE4, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x0F, 0xD5, 0x55, 0x55, 0xF8, 0x2A, 0x71, 0xC7, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x30, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x60, 0x02); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x62, 0x09); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x4C, 0x40); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x03, 0x03); + if (res < 0) + return res; + + res = tas5825m_set_book(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x78, 0x80); + if (res < 0) + return res; + + return 0; +} diff --git a/src/mainboard/novacustom/mtl-h/variants/igpu/gpio.c b/src/mainboard/novacustom/mtl-h/variants/igpu/gpio.c index f52b044..29a0ccc 100644 --- a/src/mainboard/novacustom/mtl-h/variants/igpu/gpio.c +++ b/src/mainboard/novacustom/mtl-h/variants/igpu/gpio.c @@ -568,7 +568,7 @@ PAD_CFG_NF(GPP_VGPIO47, NONE, DEEP, NF1), }; -void mainboard_configure_gpios(void) +void variant_configure_gpios(void) { gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); } diff --git a/src/mainboard/novacustom/mtl-h/variants/igpu/ramstage.c b/src/mainboard/novacustom/mtl-h/variants/igpu/ramstage.c new file mode 100644 index 0000000..4d559de --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/variants/igpu/ramstage.c @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: CC-PDDC */ + +/* Please update the license if adding licensable material. */ + +/* + * This is a placeholder, if there ever is something variant specific to + * add to ramstage, do it here. + */ -- To view, visit https://review.coreboot.org/c/coreboot/+/86790?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2b8194c486de1ba3e04aa74ed63caa7a151fbb8b Gerrit-Change-Number: 86790 Gerrit-PatchSet: 10 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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