coreboot-gerrit April 2025

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[M] Change in coreboot[main]: Documentation: Write down coreboot's git commit message rules
by Martin L Roth (Code Review) 05 Apr '25

05 Apr '25

Attention is currently required from: Jan Samek, Nicholas Chin, Paul Menzel. Martin L Roth has posted comments on this change by Martin L Roth. ( https://review.coreboot.org/c/coreboot/+/75495?usp=email ) Change subject: Documentation: Write down coreboot's git commit message rules ...................................................................... Patch Set 4: (5 comments) File Documentation/contributing/git_commit_messages.md: https://review.coreboot.org/c/coreboot/+/75495/comment/94fde3a5_3c785add?us… : PS1, Line 15: - If reflowing prose to 75 characters can reduce the length of the : commit message by 2 or more lines, please reflow it. > I understand how you feel about this, but in my opinion, it's not worth worrying about to save a sin […] Acknowledged https://review.coreboot.org/c/coreboot/+/75495/comment/6852f955_dcf18e85?us… : PS1, Line 40: CB:XXXXX or a 10 character hash > I understand what you're saying, but the CB:XXXXX is very convenient because jenkins turns it into a […] Acknowledged https://review.coreboot.org/c/coreboot/+/75495/comment/38457d91_3c4daa41?us… : PS1, Line 46: - All but the most trivial of patches should generally have a body. > Why? My opinion is that it saves people from asking why a patch was done. […] Acknowledged File Documentation/contributing/git_commit_messages.md: https://review.coreboot.org/c/coreboot/+/75495/comment/0aee489e_0615f9d0?us… : PS3, Line 53: TEST > Could we also have a description for the `BUG=` tag? Done File Documentation/contributing/index.md: PS3: > Needs a rebase to match MyST Parser's toctree format Done -- To view, visit https://review.coreboot.org/c/coreboot/+/75495?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic2ba681193e302318934cc2f7f30659eac73d099 Gerrit-Change-Number: 75495 Gerrit-PatchSet: 4 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Jan Samek <samekh(a)email.cz> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Himanshu Sahdev <himanshu.sahdev(a)intel.com> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Attention: Jan Samek <samekh(a)email.cz> Gerrit-Comment-Date: Sat, 05 Apr 2025 19:53:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin L Roth <gaumless(a)gmail.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Nicholas Chin <nic.c3.14(a)gmail.com> Comment-In-Reply-To: Jan Samek <samekh(a)email.cz>

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[M] Change in coreboot[main]: Update Maintainers file
by Matt DeVillier (Code Review) 05 Apr '25

05 Apr '25

Attention is currently required from: Felix Held, Felix Singer, Fred Reitberger, Martin L Roth, Martin Roth, Paul Menzel. Matt DeVillier has posted comments on this change by Martin L Roth. ( https://review.coreboot.org/c/coreboot/+/85883?usp=email ) Change subject: Update Maintainers file ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85883?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2feac94595081fcea9becd9d8067ddd99a50123c Gerrit-Change-Number: 85883 Gerrit-PatchSet: 5 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Sat, 05 Apr 2025 19:51:59 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: Update Maintainers file
by Martin L Roth (Code Review) 05 Apr '25

05 Apr '25

Attention is currently required from: Felix Held, Felix Singer, Fred Reitberger, Martin Roth, Matt DeVillier, Paul Menzel. Martin L Roth has posted comments on this change by Martin L Roth. ( https://review.coreboot.org/c/coreboot/+/85883?usp=email ) Change subject: Update Maintainers file ...................................................................... Patch Set 5: (1 comment) File MAINTAINERS: https://review.coreboot.org/c/coreboot/+/85883/comment/0cf6571f_712f2a72?us… : PS4, Line 389: MrChromebox(a)gmail.com> > ```suggestion […] Fix applied. -- To view, visit https://review.coreboot.org/c/coreboot/+/85883?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2feac94595081fcea9becd9d8067ddd99a50123c Gerrit-Change-Number: 85883 Gerrit-PatchSet: 5 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Sat, 05 Apr 2025 19:51:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com>

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[M] Change in coreboot[main]: Update Maintainers file
by Martin L Roth (Code Review) 05 Apr '25

05 Apr '25

Attention is currently required from: Felix Held, Fred Reitberger, Martin Roth, Paul Menzel. Martin L Roth has posted comments on this change by Martin L Roth. ( https://review.coreboot.org/c/coreboot/+/85883?usp=email ) Change subject: Update Maintainers file ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/85883/comment/9f4adbb7_9973e333?us… : PS4, Line 9: - Update AMD maintainers lists to reflect current situation : - Remove Ron Minnich as maintainer (at his request) : - Update the Infrastructure owners to reflect the current situation. > One commit per item would be great. That's not happening. It's not code. There isn't going to be anything rolled back. There's no reason for splitting it. Is it better to ask for something to be split and prevent it from being merged, or let it go in even if it's not perfect? If you insist on things being split up I can just abandon the changes now and let the file rot. -- To view, visit https://review.coreboot.org/c/coreboot/+/85883?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2feac94595081fcea9becd9d8067ddd99a50123c Gerrit-Change-Number: 85883 Gerrit-PatchSet: 4 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Sat, 05 Apr 2025 19:50:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>

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[L] Change in coreboot[main]: Documentation: Add information about the site-local directory
by Martin L Roth (Code Review) 05 Apr '25

05 Apr '25

Martin L Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/87185?usp=email ) Change subject: Documentation: Add information about the site-local directory ...................................................................... Documentation: Add information about the site-local directory This adds a document about coreboot's site-local directory along with how and when to use it. Change-Id: Ida176aa460be7673bad219f958f741dd68a8aa62 Signed-off-by: Martin Roth <gaumless(a)gmail.com> --- M Documentation/getting_started/index.md A Documentation/getting_started/site-local.md 2 files changed, 463 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/87185/1 diff --git a/Documentation/getting_started/index.md b/Documentation/getting_started/index.md index 7180c96..91bd714 100644 --- a/Documentation/getting_started/index.md +++ b/Documentation/getting_started/index.md @@ -10,5 +10,6 @@ Writing Documentation <writing_documentation.md> Setting up GPIOs <gpio.md> Adding devices to a device tree <devicetree.md> +Using the site-local directory <site-local.md> Frequently Asked Questions <faq.md> ``` diff --git a/Documentation/getting_started/site-local.md b/Documentation/getting_started/site-local.md new file mode 100644 index 0000000..497939e --- /dev/null +++ b/Documentation/getting_started/site-local.md @@ -0,0 +1,462 @@ +# Using the site-local Directory in coreboot + +## Overview + +The `site-local` directory is a powerful mechanism in coreboot that +allows developers to maintain local modifications, configurations, and +binary blobs separate from the main coreboot repository. This +separation ensures that your local changes never conflict with upstream +updates and can be versioned independently. + +## Purpose and Benefits + +- **Local Customization**: Store board-specific configurations and + modifications +- **Binary Blobs**: Keep non-redistributable files (like firmware + blobs) outside the main repository +- **Independent Versioning**: Version your local additions separately + from coreboot +- **Clean Separation**: Avoid conflicts with upstream changes +- **Build Integration**: Seamlessly integrate local additions into the + build process +- **Override default values**: Set custom Kconfig or Makefile values, + overriding the general coreboot codebase + +## Getting Started + +### Directory Structure + +Create a `site-local` directory at the top level of your coreboot +repository: + +``` +coreboot/ +├── src/ +├── util/ +├── ... +└── site-local/ <-- Your local additions go here +``` + +### Key Files + +The following files in your `site-local` directory are recognized by +coreboot's build system and parsed very early in the process to allow +default values to be set, overriding values that might be set +elsewhere in the coreboot tree. + +1. **`site-local/Kconfig`**: Integrated early in the configuration + process, allowing you to set custom defaults +2. **`site-local/Makefile.mk`**: Integrated into the build system for + custom build rules + +## Integration Methods + +### 1. Using Symbolic Links + +The most common approach for integrating local additions is using +symbolic links. This allows you to maintain a parallel directory +structure in `site-local` that mirrors coreboot's structure. + +#### Steps: + +1. Create your directory structure within `site-local` that mirrors + coreboot's structure +2. Add a `symlink.txt` file at the root of each directory you want to + link +3. In each `symlink.txt`, specify the path (relative to coreboot root) + where it should be linked +4. Run `make symlink` to create the symbolic links + +#### Example: + +``` +coreboot/ +├── src/ +│ └── soc/ +│ └── test-soc-from-site-local -> ../../site-local/src/soc/test-soc-from-site-local/ +└── site-local/ + ├── Kconfig + ├── Makefile.mk + └── src/ + └── soc/ + └── test-soc-from-site-local/ + ├── chip.h + ├── soc.c + └── symlink.txt <-- Contains "src/soc/test-soc-from-site-local" +``` + +To keep symlinks updated automatically, add this to your +`site-local/Makefile.mk`: + +``` +site-local-target:: symlink +``` + +### 2. Direct Integration via Kconfig + +Your `site-local/Kconfig` file is included early in coreboot's +configuration process, allowing you to: + +- Set custom default configurations +- Override upstream defaults +- Define new configuration options + +### 3. Build System Integration + +The `site-local/Makefile.mk` file is included in the build system, +allowing you to: + +- Add files to CBFS +- Define custom build targets +- Modify build behavior for specific boards + +## Common Use Cases + +### 1. Adding Binary Blobs to CBFS + +For non-redistributable files like firmware blobs or option ROMs: + +```makefile +# In site-local/Makefile.mk +cbfs-files-$(CONFIG_BOARD_VENDOR_BOARDNAME) += firmware.bin +firmware.bin-file := path/to/firmware.bin +firmware.bin-type := raw +``` + +### 2. Board-Specific Binary Files + +Store board-specific binary files in your `site-local` directory: + +```makefile +# Example from real configs +CONFIG_IFD_BIN_PATH="site-local/descriptor.bin" +CONFIG_ME_BIN_PATH="site-local/me.bin" +CONFIG_GBE_BIN_PATH="site-local/gbe.bin" +``` + +### 3. Custom Payloads + +Specify custom payloads for your builds: + +```makefile +CONFIG_PAYLOAD_FILE="site-local/custom/linuxboot_payload" +``` + +### 4. FSP Binaries + +Store and reference Intel FSP binaries: + +```makefile +CONFIG_FSP_T_FILE="site-local/board/Server_T.fd" +CONFIG_FSP_M_FILE="site-local/board/Server_M.fd" +CONFIG_FSP_S_FILE="site-local/board/Server_S.fd" +``` + +### 5. CPU Microcode Updates + +Include CPU microcode updates: + +```makefile +CONFIG_CPU_UCODE_BINARIES="site-local/board/microcode.bin" +``` + +## Example: Developing a New SoC Out-of-Tree + +One of the most powerful use cases for `site-local` is developing a new +SoC implementation out-of-tree before it's ready to be made public. +This allows you to: + +- Keep proprietary or under-NDA code separate until it can be properly + open-sourced +- Develop and test in the context of the full coreboot tree +- Collaborate with a team on the SoC without affecting the public + codebase +- Gradually transition from private to public as code is cleared for + release + +### Directory Structure for a New SoC + +Here's a comprehensive example of how to structure your `site-local` +directory for developing a new SoC (in this example, a fictional +"newvendor/newtarget" SoC): + +``` +coreboot/ +└── site-local/ + ├── Kconfig # Global Kconfig overrides + ├── Makefile.mk # Global Makefile overrides + └── src/ + ├── soc/ + │ └── newvendor/ # New vendor directory + │ ├── common/ # Common code for vendor SoCs + │ │ ├── include/ + │ │ │ └── soc/ + │ │ │ └── common_definitions.h + │ │ ├── Kconfig + │ │ ├── Makefile.mk + │ │ ├── common_init.c + │ │ └── symlink.txt # Contains "src/soc/newvendor/common" + │ │ + │ └── newtarget/ # Specific SoC implementation + │ ├── include/ + │ │ └── soc/ + │ │ ├── addressmap.h + │ │ ├── gpio.h + │ │ └── soc_api.h + │ ├── chip.h + │ ├── Kconfig + │ ├── Makefile.mk + │ ├── romstage.c + │ ├── ramstage.c + │ ├── gpio.c + │ ├── soc.c + │ ├── memory.c + │ ├── uart.c + │ └── symlink.txt # Contains "src/soc/newvendor/newtarget" + │ + └── mainboard/ + └── newvendor/ # Reference mainboard for the new SoC + └── devboard/ # Development board for the SoC + ├── devicetree.cb + ├── Kconfig + ├── Makefile.mk + ├── board.c + ├── romstage.c + ├── gpio.c + └── symlink.txt # Contains "src/mainboard/newvendor/devboard" +``` + +### Key Files for SoC Implementation + +Let's look at the content of some key files in this structure: + +#### 1. SOC Kconfig (`site-local/src/soc/newvendor/newtarget/Kconfig`) + +```kconfig +config SOC_NEWVENDOR_NEWTARGET + bool + help + NewVendor NewTarget SoC support + +if SOC_NEWVENDOR_NEWTARGET + +config SOC_SPECIFIC_OPTIONS + def_bool y + select ARCH_BOOTBLOCK_ARM64 + select ARCH_RAMSTAGE_ARM64 + select ARCH_ROMSTAGE_ARM64 + select ARCH_VERSTAGE_ARM64 + select ARM64_USE_ARM_TRUSTED_FIRMWARE + select HAVE_UART_SPECIAL + select COMMON_CBFS_SPI_WRAPPER + select SOC_NEWVENDOR_COMMON # For common vendor code + +config VBOOT + bool + default y if VBOOT_SLOTS_RW_AB + +config UART_FOR_CONSOLE + int + default 0 + +endif # SOC_NEWVENDOR_NEWTARGET +``` + +#### 2. SOC Makefile (`site-local/src/soc/newvendor/newtarget/Makefile.mk`) + +```makefile +bootblock-y += bootblock.c +bootblock-y += uart.c +bootblock-y += gpio.c + +romstage-y += romstage.c +romstage-y += memory.c +romstage-y += uart.c +romstage-y += gpio.c + +ramstage-y += soc.c +ramstage-y += uart.c +ramstage-y += gpio.c + +CPPFLAGS_common += -Isrc/soc/newvendor/newtarget/include +CPPFLAGS_common += -Isrc/soc/newvendor/common/include + +# Include any vendor-specific binary blobs that can't be open-sourced yet +BL31_MAKEARGS += PLAT=newtarget + +# Include private bootloader files for this SoC +cbfs-files-y += scp.bin +scp.bin-file := site-local/blobs/newvendor/newtarget/scp.bin +scp.bin-type := raw +scp.bin-position := 0x20000 +``` + +#### 3. Global site-local Kconfig (`site-local/Kconfig`) + +```kconfig +# Include our custom SoC in the mainboard selection process +source "src/soc/newvendor/*/Kconfig" + +# Override build options for development +config COMPILER_GCC + default y + +config ALLOW_MANUAL_FIRMWARE_BLOB_SELECTION + default y + +# Add custom firmware verification options +config CUSTOM_FIRMWARE_VERIFICATION + bool "Use custom firmware verification" + default n + help + Enable custom firmware verification process for NDA-covered + components +``` + +#### 4. Global site-local Makefile (`site-local/Makefile.mk`) + +```makefile +# Always run the symlink target to keep links updated +site-local-target:: symlink + +# Add a custom build step for the new SoC +prebuild-y += $(if $(CONFIG_SOC_NEWVENDOR_NEWTARGET), site-local-newtarget-prepare) + +# Define custom build step +site-local-newtarget-prepare: + @echo "Preparing NewTarget build environment..." + $(MAKE) -C site-local/tools/newtarget +``` + +#### 5. Mainboard Kconfig (`site-local/src/mainboard/newvendor/devboard/Kconfig`) + +```kconfig +if BOARD_NEWVENDOR_DEVBOARD + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select SOC_NEWVENDOR_NEWTARGET + select BOARD_ROMSIZE_KB_16384 + select MAINBOARD_HAS_CHROMEOS + select COMMON_CBFS_SPI_WRAPPER + select DRIVERS_I2C_GENERIC + select DRIVERS_USB_ACPI + +config MAINBOARD_DIR + string + default "newvendor/devboard" + +config MAINBOARD_PART_NUMBER + string + default "NewVendor Development Board" + +config MAINBOARD_VENDOR + string + default "NewVendor" + +config MAX_CPUS + int + default 8 + +endif # BOARD_NEWVENDOR_DEVBOARD +``` + +### Integration with coreboot + +1. First, set up the symlinks: + +```bash +cd coreboot +make symlink +``` + +This will create symbolic links from your `site-local` SoC +implementation into the main coreboot directory structure. + +2. Configure coreboot to use your new board: + +```bash +make menuconfig +``` + +Select: +- Mainboard → Mainboard vendor → NewVendor +- Mainboard → Mainboard model → NewVendor Development Board + +3. Build coreboot with your new SoC: + +```bash +make +``` + +### Transition to Upstream + +When your SoC implementation is ready to be made public: + +1. Move the code from `site-local` to the appropriate locations in the + main coreboot tree +2. Remove the symlinks +3. Test to ensure everything still works +4. Commit the code to the main coreboot repository + +This approach allows for a seamless transition from private to public +development. + +## Useful Commands + +- `make symlink`: Create symbolic links from `site-local` into the + coreboot tree +- `make clean-symlink`: Remove symbolic links created by `make symlink` +- `make cleanall-symlink`: Remove all symbolic links in the coreboot + tree + +## Best Practices + +1. **Version Control**: Consider keeping your `site-local` directory in + a separate git repository +2. **Git Submodules**: You can add your `site-local` repo as a git + submodule to your coreboot checkout +3. **Documentation**: Document your local additions within your + `site-local` directory +4. **Organization**: Mirror coreboot's directory structure for clarity +5. **Minimal Changes**: Keep local modifications minimal to ease future + updates + +## Important Notes + +- The `site-local` directory is intentionally excluded from coreboot's + `.gitignore` +- coreboot's lint checks will fail if you try to commit the + `site-local` directory to the main repository +- It's recommended to keep `site-local` in a separate repository and + pull it in as needed + +## Example: Complete `site-local` Setup + +Here's a complete example of a `site-local` setup for a custom board: + +``` +coreboot/ +└── site-local/ + ├── Kconfig # Custom Kconfig options + ├── Makefile.mk # Build system integration + ├── blobs/ # Binary blobs directory + │ ├── board1/ + │ │ ├── descriptor.bin + │ │ └── me.bin + │ └── board2/ + │ └── microcode.bin + └── src/ # Custom source code + └── mainboard/ + └── vendor/ + └── custom_board/ + ├── devicetree.cb + ├── Kconfig + ├── Makefile.mk + └── symlink.txt # Contains "src/mainboard/vendor/custom_board" +``` + +By leveraging the `site-local` mechanism effectively, you can maintain a +clean separation between upstream coreboot and your local +customizations, making it easier to update to new coreboot versions +while preserving your specific modifications. \ No newline at end of file -- To view, visit https://review.coreboot.org/c/coreboot/+/87185?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ida176aa460be7673bad219f958f741dd68a8aa62 Gerrit-Change-Number: 87185 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com>

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[XL] Change in coreboot[main]: Documentation: Update acronyms list
by Martin L Roth (Code Review) 05 Apr '25

05 Apr '25

Martin L Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/87184?usp=email ) Change subject: Documentation: Update acronyms list ...................................................................... Documentation: Update acronyms list - Wrap long lines. - Add periods. - Fix alphabetical ordering for a few acronyms. - Replace any en-dashes with a hyphen. - Add a few new acronyms. - Add a number of definitions (mostly U to Z) Change-Id: I0d5c76f6cf6118635c0fae217d5d37d39c8403a9 Signed-off-by: Martin Roth <gaumless(a)gmail.com> --- M Documentation/acronyms.md 1 file changed, 714 insertions(+), 524 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/87184/1 diff --git a/Documentation/acronyms.md b/Documentation/acronyms.md index 199a7da..f5c284d 100644 --- a/Documentation/acronyms.md +++ b/Documentation/acronyms.md @@ -4,23 +4,23 @@ ## _0-9 * _XXX - An underscore followed by 3 uppercase letters will typically be -an ACPI specified method. Look in the [ACPI -Spec](https://uefi.org/specifications) for details, or run the tool -`acpihelp _XXX` + an ACPI specified method. Look in the [ACPI + Spec](https://uefi.org/specifications) for details, or run the tool + `acpihelp _XXX` * 2FA - [**Two-factor Authentication**](https://en.wikipedia.org/wiki/Multi-factor_authentication) -* 4G - In coreboot, this typically refers to the 4 gibibyte boundary of 32-bit addressable memory space. - Better abbreviated as 4GiB +* 4G - In coreboot, this typically refers to the 4 gibibyte boundary + of 32-bit addressable memory space. Better abbreviated as 4GiB. * 5G - Telecommunication: [**Fifth-Generation Cellular Network**](https://en.wikipedia.org/wiki/5G) ## A * ABI - [**Application Binary Interface**](https://en.wikipedia.org/wiki/Application_binary_interface) -* ABL - AMD: AGESA BootLoader (or AMD BootLoader) - The portion of the AMD processor - initialization that happens from the PSP. Significantly, Memory - Initialization. +* ABL - AMD: AGESA BootLoader (or AMD BootLoader) - The portion of the + AMD processor initialization that happens from the PSP. + Significantly, Memory Initialization. * AC - Electricity: [**Alternating Current**](https://en.wikipedia.org/wiki/Alternating_current) * ACE - AXI Coherency Extensions * Ack - Acknowledgment / Acknowledged -* ACM – [**Authenticated Code Module**](https://doc.coreboot.org/security/intel/acm.html) +* ACM - [**Authenticated Code Module**](https://doc.coreboot.org/security/intel/acm.html) * ACP - [**Average CPU power**](https://en.wikipedia.org/wiki/Thermal_design_power) * ACPI - The [**Advanced Configuration and Power Interface**](http://en.wikipedia.org/wiki/Advanced_Configuration_and_Power_… @@ -29,7 +29,13 @@ * [http://kernelslacker.livejournal.com/88243.html](http://kernelslacker.livej… * ADC - [**Analog-to-Digital Converter**](https://en.wikipedia.org/wiki/Analog-to-digital_converter) * ADL - Intel: [**Alder Lake**](https://en.wikichip.org/wiki/intel/microarchitectures/alder_lake) +* AER - **Advanced Error Reporting** - A PCI Express feature that + provides detailed error reporting and handling capabilities for PCIe + devices and links. * AES - [**Advanced Encryption Standard**](https://en.wikipedia.org/wiki/Advanced_Encryption_Standard) + - A widely-used symmetric encryption algorithm that is implemented + in hardware on modern x86 processors through the AES-NI instruction + set extension. * AESKL - Intel: AES Key Locker * AGESA - [**AMD Generic Encapsulated Software Architecture**](https://en.wikipedia.org/wiki/AGESA_) * AGP - The [**Accelerated Graphics @@ -41,6 +47,7 @@ is a standard register set for communicating with a SATA controller. * [http://www.intel.com/technology/serialata/ahci.htm](http://www.intel.com/te… * [http://download.intel.com/technology/serialata/pdf/rev1_3.pdf](http://downl… +* AHB - Advanced High-performance Bus (part of the AMBA bus specification) * AIC - Add-in Card * AIO - Computer formfactor: [**All In One**](https://en.wikipedia.org/wiki/Desktop_computer#All-in-one) * ALIB - AMD: ACPI-ASL Library @@ -49,22 +56,25 @@ * AMBA - ARM: [**Advanced Microcontroller Bus Architecture**](https://en.wikipedia.org/wiki/Advanced_Microcontroller_Bus_…: An open standard to connect and manage functional blocks in an SoC - (System on a Chip) + (System on a Chip). * AMD64 - Another name for [**x86-64**](https://en.wikipedia.org/wiki/X86-64) -* AMD-Vi AMD: The AMD name for their IOMMU implementation -* AMPL - AMD: [**Advanced Platform Management Link**](https://web.archive.org/web/20220509053546/https://developer.amd.co… - Also referred to as - SBI: Sideband Interface +* AMD-Vi - AMD: The AMD name for their IOMMU implementation. +* AML - **ACPI Machine Language** - The low-level programming language + used to define ACPI tables and methods that control power management + and hardware configuration. +* AMPL - AMD: [**Advanced Platform Management Link**](https://web.archive.org/web/20220509053546/https://developer.amd.co… + - Also referred to as SBI: Sideband Interface. * AMT - Intel: [**Active Management Technology**](https://en.wikipedia.org/wiki/Intel_Active_Management_Technol… * ANSI - [**American National Standards Institute**](https://en.wikipedia.org/wiki/American_National_Standards_Inst… * AOAC - AMD: Always On, Always Connected -* AON - Always ON: Sometimes used for power domains that are always on (e.g. RTC, GPIOs, Wake on LAN ...) +* AON - Always ON: Sometimes used for power domains that are always on + (e.g. RTC, GPIOs, Wake on LAN ...). * AP - Application processor - The main processor on the board (as opposed to the embedded controller or other processors that may be on - the system), any cores in the processor chip that aren't the BSP (Boot - Strap Processor). -* APB - Advanced Peripheral Bus (part of the AMBA bus specification) + the system), any cores in the processor chip that aren't the BSP + (Boot Strap Processor). +* APB - Advanced Peripheral Bus (part of the AMBA bus specification). * APCB - AMD: AMD PSP Customization Block -* AHB - Advanced High-performance Bus (part of the AMBA bus specification) * API - [**Application Programming Interface**](https://en.wikipedia.org/wiki/API) * APIC - [**Advanced Programmable Interrupt Controller**](https://en.wikipedia.org/wiki/Advanced_Programmable_Interrupt… @@ -73,19 +83,20 @@ Local APICs (LAPIC) are CPU-bound, IO-APICs are bridge-bound. * [http://osdev.berlios.de/pic.html](http://osdev.berlios.de/pic.html) * APL - Intel: [**Apollo Lake**](https://en.wikichip.org/wiki/intel/cores/apollo_lake) -* APM - [**Advanced Power Management**](https://en.wikipedia.org/wiki/Advanced_Power_Management) - The standard for power management - before ACPI (Yes, they’re both advanced). APM was managed entirely by - the firmware and the operating system had no control or even awareness - of the power management. +* APM - [**Advanced Power Management**](https://en.wikipedia.org/wiki/Advanced_Power_Management) + - The standard for power management before ACPI (Yes, they're both + advanced). APM was managed entirely by the firmware and the operating + system had no control or even awareness of the power management. * APOB - AMD: [**AGESA PSP Output Buffer**](https://doc.coreboot.org/soc/amd/family17h.html#additional-defini… * APU - AMD: [**Accelerated Processing Unit**](https://en.wikipedia.org/wiki/AMD_Accelerated_Processing_Unit) * ARC - HDMI: [**Audio Return Channel**](https://en.wikipedia.org/wiki/HDMI#ARC) -* ARM - [**Advanced RISC Machines**](https://en.wikipedia.org/wiki/Arm_%28company%29) - Originally Acorn RISC Machine. This - may refer to either the company or the instruction set. +* ARM - [**Advanced RISC Machines**](https://en.wikipedia.org/wiki/Arm_%28company%29) + - Originally Acorn RISC Machine. This may refer to either the company + or the instruction set. * ARP - Networking: [**Address Resolution Protocol**](https://en.wikipedia.org/wiki/Address_Resolution_Protocol) * ASCII - [**American Standard Code for Information Interchange**](https://en.wikipedia.org/wiki/ASCII) -* ASEG - The A_0000h-B_FFFFh memory segment - this area was typically - hidden by the Video BIOS +* ASEG - The 0xA0000-0xBFFFF memory segment - this area was typically + hidden by the Video BIOS. * ASF - [**Alert Standard Format**](https://en.wikipedia.org/wiki/Alert_Standard_Format) * ASL - [**ACPI Source Language**](https://uefi.org/htmlspecs/ACPI_Spec_6_4_html/19_ASL_Reference/… * ASLR - Address Space Layout Randomization @@ -94,24 +105,28 @@ * ASPM - PCI: [**Active State Power Management**](https://en.wikipedia.org/wiki/Active_State_Power_Management) * ATA - [**Advanced Technology Attachment**](https://en.wikipedia.org/wiki/Parallel_ATA) -* ATS - PCIe: Address Translation Services * ATAPI - [**ATA Packet Interface**](https://en.wikipedia.org/wiki/Parallel_ATA#ATAPI) +* ATS - PCIe: Address Translation Services * ATX - [**Advanced Technology eXtended**](https://en.wikipedia.org/wiki/ATX) * AVX - [**Advanced Vector Extensions**](https://en.wikipedia.org/wiki/Advanced_Vector_Extensions) -* AXI - [Advanced eXtensible Interface](https://en.wikipedia.org/wiki/Advanced_eXtensible_Interface) part of the AMBA bus specification +* AXI - [Advanced eXtensible Interface](https://en.wikipedia.org/wiki/Advanced_eXtensible_Interface) + part of the AMBA bus specification. ## B -* BAR - [**Base Address Register**](https://en.wikipedia.org/wiki/Base_Address_Register) This generally refers to one of the - base address registers in the PCI config space of a PCI device -* Baud - [**Baud**](https://en.wikipedia.org/wiki/Baud) - Not an acronym - Symbol rate unit of symbols per second, named - after Émile Baudot +* BAR - [**Base Address Register**](https://en.wikipedia.org/wiki/Base_Address_Register) + This generally refers to one of the base address registers in the PCI + config space of a PCI device. +* Baud - [**Baud**](https://en.wikipedia.org/wiki/Baud) - Not an acronym + - Symbol rate unit of symbols per second, named after Émile Baudot. * BBS - [**BIOS boot specification**](https://en.wikipedia.org/wiki/Option_ROM#BIOS_Boot_Specifi… * BCD - [**Binary-Coded Decimal**](https://en.wikipedia.org/wiki/Binary-coded_decimal) * BCT - Intel: [**Binary Configuration Tool**](https://github.com/intel/BCT) -* BDA - [**BIOS Data Area**](http://www.bioscentral.com/misc/bda.htm) This refers to the memory area of 0x40:0000 which is where the original PC-BIOS stored its data tables. -* BDF - [**BUS, Device, Function**](https://en.wikipedia.org/wiki/PCI_configuration_space#Technical… - A way of referencing a PCI Device - function address. +* BDA - [**BIOS Data Area**](http://www.bioscentral.com/misc/bda.htm) + This refers to the memory area of 0x40:0000 which is where the + original PC-BIOS stored its data tables. +* BDF - [**BUS, Device, Function**](https://en.wikipedia.org/wiki/PCI_configuration_space#Technical… + - A way of referencing a PCI Device function address. * BDS - UEFI: [**Boot-Device Select**](https://en.wikipedia.org/wiki/Unified_Extensible_Firmware_Interfa… * BDW - Intel: [**Broadwell**](https://en.wikichip.org/wiki/intel/microarchitectures/broadwell_%28client%29) * BERT - ACPI: [**Boot Error Record Table**](https://uefi.org/specs/ACPI/6.4/18_ACPI_Platform_Error_Interfaces/… @@ -122,17 +137,18 @@ or [**Unreal mode**](https://en.wikipedia.org/wiki/Unreal_mode). * BIOS - [**Basic Input/Output System**](https://en.wikipedia.org/wiki/BIOS) -* BIST - The [**Built-in Self Test**](https://en.wikipedia.org/wiki/Built-in_self-test) is a test run by the processor on - itself when it is first started. Usually, any nonzero value indicates - that the selftest failed. -* Bit-banging - [**Bit-banging**](https://en.wikipedia.org/wiki/Bit_banging) - A term for the method of emulating a more complex - protocol by using GPIOs. -* BKDG - AMD: [**Bios & Kernel Developers' guide**](https://en.wikichip.org/wiki/amd/List_of_AMD_publications) (Replaced by the PPR - - Processor Programming Reference) -* BLOB - [**Binary Large OBject**](https://en.wikipedia.org/wiki/Binary_large_object) - Originally a collection of binary files - stored as a single object, this was co-opted by the open source - communities to mean any proprietary binary file that is not available - as source code. +* BIST - The [**Built-in Self Test**](https://en.wikipedia.org/wiki/Built-in_self-test) + is a test run by the processor on itself when it is first started. + Usually, any nonzero value indicates that the selftest failed. +* Bit-banging - [**Bit-banging**](https://en.wikipedia.org/wiki/Bit_banging) + - A term for the method of emulating a more complex protocol by using + GPIOs. +* BKDG - AMD: [**Bios & Kernel Developers' guide**](https://en.wikichip.org/wiki/amd/List_of_AMD_publications) + (Replaced by the PPR - Processor Programming Reference). +* BLOB - [**Binary Large OBject**](https://en.wikipedia.org/wiki/Binary_large_object) + - Originally a collection of binary files stored as a single object, + this was co-opted by the open source communities to mean any + proprietary binary file that is not available as source code. * BM - [**Bus Master**](https://en.wikipedia.org/wiki/Bus_mastering) * BMC - [**Baseboard Management Controller**](https://en.wikipedia.org/wiki/Intelligent_Platform_Management… * BMP - [**Bitmap**](https://en.wikipedia.org/wiki/BMP_file_format) @@ -140,11 +156,11 @@ * BPDT - Boot Partition Description Table * bps - Bits Per Second * BS - coreboot: Boot State - coreboot's ramstage sequence are made up - of boot states. Each of these states can be hooked to run functions - before the stat, during the state, or after the state is complete. + of boot states. Each of these states can be hooked to run functions + before the state, during the state, or after the state is complete. * BSF - Intel: [**Boot Specification File**](https://www.intel.com/content/dam/develop/external/us/en/documents/… * BSP - BootStrap Processor - The initialization core of the main - system processor. This is the processor core that starts the boot + system processor. This is the processor core that starts the boot process. * BSS - [**Block Starting Symbol**](https://en.wikipedia.org/wiki/.bss) * BT - [**Bluetooth**](https://en.wikipedia.org/wiki/Bluetooth) @@ -159,93 +175,98 @@ [**C-States**](https://en.wikichip.org/wiki/acpi/c-states) C0-Cx: Each higher number saves more power, but takes longer to return to a fully running processor. -* C0 - ACPI Defined Processor Idle state: Active - CPU is running +* C0 - ACPI Defined Processor Idle state: Active - CPU is running. * C1 - ACPI Defined Processor Idle state: Halt - Nothing currently - running, but can start running again immediately -* C2 - ACPI Defined Processor Idle state: Stop-clock - core clocks off + running, but can start running again immediately. +* C2 - ACPI Defined Processor Idle state: Stop-clock - core clocks off. * C3 - ACPI Defined Processor Idle state: Sleep - L1 & L2 caches may be saved to Last Level Cache (LLC), core powered down. -* C4+ - Processor Specific idle states +* C4+ - Processor Specific idle states. * CAR - [**Cache As RAM**](https://web.archive.org/web/20140818050214/https://www.coreboot.org/… -* CBFS - coreboot filesystem -* CBMEM - coreboot Memory +* CBFS - coreboot filesystem. +* CBMEM - coreboot Memory. * CBI - Google: [**CrOS Board Information**](https://chromium.googlesource.com/chromiumos/docs/+/HEAD/des… * CDN - [**Content Delivery Network**](https://en.wikipedia.org/wiki/Content_delivery_network) -* CEM - PCIe: [**Card ElectroMechanical**](https://members.pcisig.com/wg/PCI-SIG/document/folder/… specification -* CFL - [**Coffee Lake**](https://en.wikichip.org/wiki/intel/microarchitectures/coffee_lake) -* CHI - Coherent Hub Interface +* CEM - PCIe: [**Card ElectroMechanical**](https://members.pcisig.com/wg/PCI-SIG/document/folder/… + specification. +* CFL - Intel: [**Coffee Lake**](https://en.wikichip.org/wiki/intel/microarchitectures/coffee_lake) +* CHI - Coherent Hub Interface. * CID - [**Coverity ID**](https://en.wikipedia.org/wiki/Coverity) * CIM - [**Common Information Model**](https://www.dmtf.org/standards/cim) * CISC - [**Complex Instruction Set Computer**](https://en.wikipedia.org/wiki/Complex_instruction_set_computer) -* CL - ChangeList - Another name for a patch or commit. This seems to be +* CL - ChangeList - Another name for a patch or commit. This seems to be Perforce notation. * CLK - Clock - Used when there isn't enough room for 2 additional characters - similar to RST, for people who hate vowels. * CML - Intel: [**Comet Lake**](https://en.wikichip.org/wiki/intel/microarchitectures/comet_lake) * CMOS - [**Complementary Metal Oxide Semiconductor**](https://en.wikipedia.org/wiki/Nonvolatile_BIOS_memory) - - This is a method of making ICs (Integrated Circuits). For BIOS, it’s + - This is a method of making ICs (Integrated Circuits). For BIOS, it's generally used to describe a section of NVRAM (Non-volatile RAM), in this case a section battery-backed memory in the RTC (Real Time Clock) - that is typically used to store BIOS settings. - *[https://en.wikipedia.org/wiki/Nonvolatile_BIOS_memory](https://en.wikipedia.org/wiki/Nonvolatile_BIOS_memory) -* CNL - Intel: [**Cannon Lake**](https://en.wikichip.org/wiki/intel/microarchitectures/cannon_lake) (formerly Skymont) + that is typically used to store BIOS settings. See also: + [https://en.wikipedia.org/wiki/Nonvolatile_BIOS_memory](https://en.wikipedia… +* CNL - Intel: [**Cannon Lake**](https://en.wikichip.org/wiki/intel/microarchitectures/cannon_lake) + (formerly Skymont). * CNVi - Intel: [**Connectivity Integration**](https://en.wikipedia.org/wiki/CNVi) -* CPL - x86: Current Privilege Level - Privilege levels range from 0-3; lower numbers are more privileged. +* CPL - x86: Current Privilege Level - Privilege levels range from 0-3; + lower numbers are more privileged. * CPLD - [**Complex Programmable Logic Device**](https://en.wikipedia.org/wiki/Complex_programmable_logic_device) -* CPPC - AMD: Collaborative Processor Performance Controls -* CPS - Characters Per Second +* CPPC - AMD: Collaborative Processor Performance Controls. +* CPS - Characters Per Second. * CPU - [**Central Processing Unit**](https://en.wikipedia.org/wiki/Central_processing_unit) -* CPUID - x86: [**CPU Identification**](https://en.wikipedia.org/wiki/CPUID) opcode +* CPUID - x86: [**CPU Identification**](https://en.wikipedia.org/wiki/CPUID) + opcode. * Cr50 - Google: The first generation Google Security Chip (GSC) used on ChromeOS devices. -* CRB - Customer Reference Board -* CRLF - Carriage Return, Line Feed - \\r\\n - The standard window EOL +* CRB - Customer Reference Board. +* CRLF - Carriage Return, Line Feed - `\\r\\n` - The standard window EOL (End-of-Line) marker. * crt0 - [**C Run Time 0**](https://en.wikipedia.org/wiki/Crt0) -* crt0s - crt0 Source code +* crt0s - crt0 Source code. * CRT - [**Cathode Ray Tube**](https://en.wikipedia.org/wiki/Cathode-ray_tube) -* CSE - Intel: Converged Security Engine +* CSE - Intel: Converged Security Engine. * CSI - MIPI: [**Camera Serial Interface**](https://en.wikipedia.org/wiki/Camera_Serial_Interface) -* CSME - Intel: Converged Security and Management Engine -* CTLE - Intel: Continuous Time Linear Equalization +* CSME - Intel: Converged Security and Management Engine. +* CTLE - Intel: Continuous Time Linear Equalization. * CVE - [**Common Vulnerabilities and Exposures**](https://en.wikipedia.org/wiki/Common_Vulnerabilities_and_Expos… -* CXMT - ChangXin Memory Technologies -* CZN - AMD: [**Cezanne**](https://en.wikichip.org/wiki/amd/cores/cezanne) - CPU Family 19h, Model 50h +* CXMT - ChangXin Memory Technologies. +* CZN - AMD: [**Cezanne**](https://en.wikichip.org/wiki/amd/cores/cezanne) + - CPU Family 19h, Model 50h. ## D -* D$ - Data Cache +* D$ - Data Cache. * D-States - [**ACPI Device power states**](https://en.wikipedia.org/wiki/Advanced_Configuration_and_Power_In… D0-D3 - These are device specific power states, with each higher number requiring less power, and typically taking a longer time to get back to D0, fully running. -* D0 - ACPI Device power state: Active - Device fully on and running -* D1 - ACPI Device power state: Lower power than D0 -* D2 - ACPI Device power state: Lower power than D1 +* D0 - ACPI Device power state: Active - Device fully on and running. +* D1 - ACPI Device power state: Lower power than D0. +* D2 - ACPI Device power state: Lower power than D1. * D3 Hot - ACPI Device power state: Device is in a low power state, but still has power. * D3 Cold - ACPI Device power state: Power is completely removed from the device. * DASH - [**Desktop and mobile Architecture for System Hardware**](https://en.wikipedia.org/wiki/Desktop_and_mobile_Architecture_f… -* DB - DaughterBoard -* DbC - USB: Debug Capability on the USB host controller -* DC - Electricity: Direct Current -* DCP - Digital Content Protection -* DCR - **Decode Control Register** This is a way of identifying the - hardware in question. This is generally paired with a Vendor ID (VID) +* DB - DaughterBoard. +* DbC - USB: Debug Capability on the USB host controller. +* DC - Electricity: Direct Current. +* DCP - Digital Content Protection. +* DCR - **Decode Control Register** - This is a way of identifying the + hardware in question. This is generally paired with a Vendor ID (VID). * DDC - [**Display Data Channel**](https://en.wikipedia.org/wiki/Display_Data_Channel) -* DDI - Intel: Digital Display Interface +* DDI - Intel: Digital Display Interface. * DDR - [**Double Data Rate**](https://en.wikipedia.org/wiki/Double_data_rate) -* DEVAPC - Mediatek: Device Access Permission Control -* DF - Data Fabric -* DFP - USB: Downstream Facing port +* DEVAPC - Mediatek: Device Access Permission Control. +* DF - Data Fabric. +* DFP - USB: Downstream Facing port. * DHCP - [**Dynamic Host Configuration Protocol**](https://en.wikipedia.org/wiki/Dynamic_Host_Configuration_Protoc… -* DID - Device Identifier +* DID - Device Identifier. * DIMM - [**Dual Inline Memory Module**](https://en.wikipedia.org/wiki/DIMM) * DIP - [**Dual inline package**](https://en.wikipedia.org/wiki/Dual_in-line_package) * DMA - [**Direct Memory @@ -256,30 +277,30 @@ Graphics Card, Sound Card. DMA is an essential feature of all modern computers, as it allows devices of different speeds to communicate without subjecting the CPU to a massive interrupt load. -* DMI - Direct Media Interface is a link/bus between CPU and PCH. +* DMI - Direct Media Interface - A link/bus between CPU and PCH. * DMI - [**Desktop Management Interface**](https://en.wikipedia.org/wiki/Desktop_Management_Interface) -* DMIC - Digital Microphone +* DMIC - Digital Microphone. * DMTF - [**Distributed Management Task Force**](https://en.wikipedia.org/wiki/Distributed_Management_Task_Force) -* DMZ - Demilitarized Zone +* DMZ - Demilitarized Zone. * DNS - [**Domain Name Service**](https://en.wikipedia.org/wiki/Domain_Name_System) * DNV - Intel: [**Denverton**](https://en.wikichip.org/wiki/intel/cores/denverton) -* DOS - Disk Operating System -* DP - DisplayPort -* DPM - Mediatek: DRAM Power Manager -* DPTC - AMD: Dynamic Power and Thermal Control -* DPTF - Intel: Dynamic Power and Thermal Framework +* DOS - Disk Operating System. +* DP - DisplayPort. +* DPM - Mediatek: DRAM Power Manager. +* DPTC - AMD: Dynamic Power and Thermal Control. +* DPTF - Intel: Dynamic Power and Thermal Framework. * DRAM - Memory: [**Dynamic Random Access Memory**](https://en.wikipedia.org/wiki/Dynamic_random-access_memory) -* DRTM - Dynamic Root of Trust for Measurement -* DQ - Memory: Data I/O signals. On a D-flipflop, used for SRAM, the +* DRTM - Dynamic Root of Trust for Measurement. +* DQ - Memory: Data I/O signals. On a D-flipflop, used for SRAM, the data-in pin is generally referred to as D, and the data-out pin is Q, thus the IO Data signal lines are referred to as DQ lines. * DQS - Memory: Data Q Strobe - Data valid signal for DDR memory. * DRM - [**Digital Rights Management**](https://en.wikipedia.org/wiki/Digital_rights_management) -* DRP - USB: Port than can be switched between either a Downstream facing (DFP) or - an Upstream Facing (UFP). -* DRQ - DMA Request -* DRTU - Intel: Diagnostics and Regulatory Testing Utility +* DRP - USB: Port that can be switched between either a Downstream + facing (DFP) or an Upstream Facing (UFP). +* DRQ - DMA Request. +* DRTU - Intel: Diagnostics and Regulatory Testing Utility. * DSDT - The [**Differentiated System Descriptor Table**](http://acpi.sourceforge.net/dsdt/index.php), is generated by BIOS and necessary for ACPI. Implementation of ACPI in coreboot needs @@ -288,79 +309,84 @@ * DSC - [**Digital Signal Controller**](https://en.wikipedia.org/wiki/Digital_signal_controller) * DSL - [**Digital subscriber line**](https://en.wikipedia.org/wiki/Digital_subscriber_line) * DSP - [**Digital Signal Processor**](https://en.wikipedia.org/wiki/Digital_signal_processor) -* DTB - U-Boot: Device Tree Binary +* DTB - U-Boot: Device Tree Binary. * dTPM - Discrete TPM (Trusted Platform Module) - A separate TPM chip, vs Integrated TPMs or fTPMs (Firmware TPMs). -* DTS - U-Boot: Device Tree Source -* DUT - Device Under Test -* DvC - USB: Debug Capability on the USB Device (Device Capability) -* DVFS - ARM: Dynamic Voltage and Frequency Scaling +* DTS - U-Boot: Device Tree Source. +* DUT - Device Under Test. +* DvC - USB: Debug Capability on the USB Device (Device Capability). +* DVFS - ARM: Dynamic Voltage and Frequency Scaling. * DVI - [**Digital Video Interface**](https://en.wikipedia.org/wiki/Digital_Visual_Interface) -* DVT - Production Timeline: Design Validation Test +* DVT - Production Timeline: Design Validation Test. * DW - DesignWare: A portfolio of silicon IP blocks for sale by the - Synopsys company. Includes blocks like USB, MIPI, PCIe, HDMI, SATA, - I2c, memory controllers and more. + Synopsys company. Includes blocks like USB, MIPI, PCIe, HDMI, SATA, + I2C, memory controllers and more. * DXE - UEFI: [**Driver Execution Environment**](https://en.wikipedia.org/wiki/Unified_Extensible_Firmware_In… -* DXIO - AMD: Distributed CrossBar I/O +* DXIO - AMD: Distributed CrossBar I/O. ## E * EAPD - Intel: [**External Amplifier Power Down**](https://web.archive.org/web/20210203194800/https://www.eeweb.com/hd… -* EBDA - Extended BIOS Data Area -* EBG - Intel: Emmitsburg PCH -* ECC - [**Error Correction Code**](https://en.wikipedia.org/wiki/Error_correction_code) - Typically used to refer to a type of - memory that can detect and correct memory errors. +* EBDA - Extended BIOS Data Area. +* EBG - Intel: Emmitsburg PCH. +* EC - **Embedded Controller** - A microcontroller on the mainboard, often + handling keyboard, power, battery, and thermal management. +* ECC - [**Error Correction Code**](https://en.wikipedia.org/wiki/Error_correction_code) + - Typically used to refer to a type of memory that can detect and + correct memory errors. * EDID - [**Extended Display Identification Data**](https://en.wikipedia.org/wiki/Extended_Display_Identification_Data) -* EDK2 - EFI Development Kit 2 +* EDK2 - EFI Development Kit 2. * EDO - Memory: [**Extended Data Out**](https://en.wikipedia.org/wiki/Dynamic_random-access_memory#Extended_… - A DRAM standard introduced in 1994 that improved upon, but was backwards compatible with FPM (Fast Page Mode) memory. * eDP - [**Embedded DisplayPort**](https://en.wikipedia.org/wiki/DisplayPort#eDP) -* EDS - Intel: External Design Specification -* EEPROM - [**Electrically Erasable Programmable ROM**](https://en.wikipedia.org/wiki/EEPROM) (common mistake: - electrical erasable programmable ROM). +* EDS - Intel: External Design Specification. +* EEPROM - [**Electrically Erasable Programmable ROM**](https://en.wikipedia.org/wiki/EEPROM) + (common mistake: electrical erasable programmable ROM). * EFI - [**Extensible Firmware Interface**](https://en.wikipedia.org/wiki/Unified_Extensible_Firmware_Inte… -* EFS - AMD: Embedded Firmware Structure: The data structure that AMD processors look for first in the boot ROM to start the boot process. -* EHCI - [**Enhanced Host Controller Interface**](https://en.wikipedia.org/wiki/Host_controller_interface_%28USB… - USB 2.0 +* EFS - AMD: Embedded Firmware Structure - The data structure that AMD + processors look for first in the boot ROM to start the boot process. +* EHCI - [**Enhanced Host Controller Interface**](https://en.wikipedia.org/wiki/Host_controller_interface_%28USB… + - USB 2.0. * EHL - Intel: [**Elkhart Lake**](https://en.wikichip.org/wiki/intel/cores/elkhart_lake) -* EIDE - Enhanced Integrated Drive Electronics +* EIDE - Enhanced Integrated Drive Electronics. * EMI - [**ElectroMagnetic Interference**](https://en.wikipedia.org/wiki/Electromagnetic_interference) * eMMC - [**embedded MultiMedia Card**](https://en.wikipedia.org/wiki/MultiMediaCard#eMMC) -* EOP - End of POST -* EOL - End of Life -* EPP - Intel: Energy-Performance Preference -* EPROM - Erasable Programmable Read-Only Memory +* EOP - End of POST. +* EOL - End of Life. +* EPP - Intel: Energy-Performance Preference. +* EPROM - Erasable Programmable Read-Only Memory. * EROFS - Linux: [**Enhanced Read-Only File System**](https://en.wikipedia.org/wiki/EROFS) -* ESD - Electrostatic discharge -* eSPI - Enhanced System Peripheral Interface -* EVT - Production Timeline: Engineering Validation Test +* ESD - Electrostatic discharge. +* eSPI - Enhanced System Peripheral Interface. +* EVT - Production Timeline: Engineering Validation Test. ## F -* FADT - ACPI Table: Fixed ACPI Description Table -* FAE - Field Application Engineer -* FAT - File Allocation Table -* FBVDDQ - Nvidia Power: Framebuffer Voltage -* FCH - AMD: Firmware Control Hub -* FCS - Production Timeline: First Customer Shipment -* FDD - Floppy Disk Drive -* FFS - UEFI: Firmware File System -* FIFO - First In, First Out -* FIT - Intel: Firmware Interface Table -* FIT - Flattened-Image Tree -* FIVR - Intel: Fully Integrated Voltage Regulators +* FADT - ACPI Table: Fixed ACPI Description Table. +* FAE - Field Application Engineer. +* FAT - File Allocation Table. +* FBVDDQ - Nvidia Power: Framebuffer Voltage. +* FCH - AMD: Firmware Control Hub. +* FCS - Production Timeline: First Customer Shipment. +* FDD - Floppy Disk Drive. +* FFS - UEFI: Firmware File System. +* FIFO - First In, First Out. +* FIT - Intel: Firmware Interface Table. +* FIT - Flattened-Image Tree. +* FIVR - Intel: Fully Integrated Voltage Regulators. * Flashing - Flashing means the writing of flash memory. The BIOS on modern mainboards is stored in a NOR flash EEPROM chip. * Flat mode - Real mode running in a way that allows it to access the - entire 4GiB of the 32-bit address space. Also known as Unreal mode or - Big Real mode + entire 4GiB of the 32-bit address space. Also known as Unreal mode or + Big Real mode. * FMAP - coreboot: [**Flash map**](https://doc.coreboot.org/lib/flashmap.html) -* FPDT - ACPI: Firmware Performance Data Table +* FPDT - ACPI: Firmware Performance Data Table. * FPGA - [**Field-Programmable Gate Array**](https://en.wikipedia.org/wiki/Field-programmable_gate_array) * Framebuffer - The [**framebuffer**](https://en.wikipedia.org/wiki/Framebuffer) is a part @@ -372,89 +398,100 @@ the visible screen. * On-screen, meaning that the framebuffer is directly coupled to the visible display. -* FPM - Memory: [**Fast Page Mode**](https://en.wikipedia.org/wiki/Dynamic_random-access_memory#Page_mod… - A DRAM standard introduced in 1990. +* FPM - Memory: [**Fast Page Mode**](https://en.wikipedia.org/wiki/Dynamic_random-access_memory#Page_mod… + - A DRAM standard introduced in 1990. * FPU - [**Floating-Point Unit**](https://en.wikipedia.org/wiki/Floating-point_unit) * FSB - [**Front-Side Bus**](https://en.wikipedia.org/wiki/Front-side_bus) -* FSM - Finite State Machine -* FSP - Intel: Firmware Support Package -* FSR - Intel: Firmware Status Register +* FSM - Finite State Machine. +* FSP - Intel: Firmware Support Package. +* FSPUPD - Intel FSP: **Firmware Support Package Update Data** - + Configuration data structure passed to Intel's FSP binary at runtime. +* FSR - Intel: Firmware Status Register. * FTP - Network Protocol: [**File Transfer Protocol**](https://en.wikipedia.org/wiki/File_Transfer_Protocol) -* fTPM - Firmware TPM (Trusted Platform Module). This is a TPM that is - based in firmware instead of actual hardware. It typically runs in +* fTPM - Firmware TPM (Trusted Platform Module). This is a TPM that is + based in firmware instead of actual hardware. It typically runs in some sort of TEE (Trusted Execution Environment). -* FWCM Intel: firmware Connection Manager -* FWID - Firmware Identifier +* FW - Firmware - Low-level software embedded within hardware components. +* FWCM - Intel: firmware Connection Manager. +* FWID - Firmware Identifier. ## G -* G0 - ACPI Global Power State: System is running -* G0-G3 - ACPI Global Power States -* G1 - ACPI Global Power State: System is suspended -* G2 - ACPI Global Power State: Soft power-off. The mainboard is off, +* G0 - ACPI Global Power State: System is running. +* G0-G3 - ACPI Global Power States. +* G1 - ACPI Global Power State: System is suspended. +* G2 - ACPI Global Power State: Soft power-off. The mainboard is off, but can be woken up electronically, by a button, wake-on-lan, a keypress, or some other method. * G3 - ACPI Global Power State: Mechanical Off. There is no power going to the system except for a small battery to keep the CMOS contents, Real Time Clock, and maybe a few other registers running. * GART - AMD: [**Graphics Address Remapping Table**](https://en.wikipedia.org/wiki/Graphics_address_remapping_table) -* GATT - Graphics Aperture Translation Table +* GATT - Graphics Aperture Translation Table. * GDT - [Global Descriptor Table](https://wiki.osdev.org/Global_Descriptor_Table) * GLK - Intel: [**Gemini Lake**](https://en.wikichip.org/wiki/intel/cores/gemini_lake) * GMA - Intel: [**Graphics Media Accelerator**](https://en.wikipedia.org/wiki/Intel_GMA) -* GNB - Graphics NorthBridge -* GND - Power: Ground -* GNVS - Global Non-Volatile Storage -* GPD - PCH GPIO in Deep Sleep well (D5 power) -* GPE - ACPI: General Purpose Event -* GPI - GPIOs: GPIO Input -* GPIO - [**General Purpose Input/Output**](https://en.wikipedia.org/wiki/General-purpose_input/output) (Pin) -* GPMR - Intel: General Purpose Memory Range -* GPO - GPIOs: GPIO Output -* GPP - AMD: General Purpose (PCI/PCIe) port -* GPP - Intel: PCH GPIO in Primary Well (S0 power only) -* GPS - Nvidia: GPU Performance Scale +* GNB - Graphics NorthBridge. +* GND - Power: Ground. +* GNVS - Global Non-Volatile Storage. +* GPD - PCH GPIO in Deep Sleep well (D5 power). +* GPE - ACPI: General Purpose Event. +* GPI - GPIOs: GPIO Input. +* GPIO - [**General Purpose Input/Output**](https://en.wikipedia.org/wiki/General-purpose_input/output) + (Pin). +* GPMR - Intel: General Purpose Memory Range. +* GPO - GPIOs: GPIO Output. +* GPP - AMD: General Purpose (PCI/PCIe) port. +* GPP - Intel: PCH GPIO in Primary Well (S0 power only). +* GPS - Nvidia: GPU Performance Scale. * GPT - UEFI: [**GUID Partition Table**](https://en.wikipedia.org/wiki/GUID_Partition_Table) * GPU - [**Graphics Processing Unit**](https://en.wikipedia.org/wiki/Graphics_processing_unit) * GSoC - [**Google Summer of Code**](https://en.wikipedia.org/wiki/Google_Summer_of_Code) -* GSC - Google Security Chip - Typically Cr50/Ti50, though could also refer to the titan chips +* GSC - Google Security Chip - Typically Cr50/Ti50, though could also + refer to the titan chips. * GSPI - Generic SPI - These are SPI controllers available for general use, not dedicated to flash, for example. -* GTDT - ACPI: Generic Timer Description Table +* GTDT - ACPI: Generic Timer Description Table. * GTT - [**Graphics Translation Table**](https://en.wikipedia.org/wiki/Graphics_address_remapping_table) * GUID - UEFI: [**Globally Unique IDentifier**](https://en.wikipedia.org/wiki/Universally_unique_identifier) ## H -* HBP - Graphics: [**Horizontal Back Porch**](https://en.wikipedia.org/wiki/Horizontal_blanking_interval) In the Horizontal blanking interval, this is the blank area past the end of the scanline +* HBP - Graphics: [**Horizontal Back Porch**](https://en.wikipedia.org/wiki/Horizontal_blanking_interval) + In the Horizontal blanking interval, this is the blank area past the + end of the scanline. * HDA - [**High Definition Audio**](https://en.wikipedia.org/wiki/Intel_High_Definition_Audio) * HDCP - [**High-bandwidth Digital Content Protection**](https://en.wikipedia.org/wiki/High-bandwidth_Digital_Content_… -* HDD - Hard Disk Drive +* HDD - Hard Disk Drive. * HDMI - [**High-Definition Multimedia Interface**](https://en.wikipedia.org/wiki/HDMI) * HDR - [**High Dynamic Range**](https://en.wikipedia.org/wiki/High_dynamic_range) -* HECI - Intel: [**Host Embedded Controller Interface**](https://en.wikipedia.org/wiki/Host_Embedded_Controller_Interfa… (Replaced by MEI) -* HFP - Graphics: [**Horizontal Front Porch**](https://en.wikipedia.org/wiki/Horizontal_blanking_interval) In the Horizontal blanking interval, this is the blank before the start of the next scanline. +* HECI - Intel: [**Host Embedded Controller Interface**](https://en.wikipedia.org/wiki/Host_Embedded_Controller_Interfa… + (Replaced by MEI). +* HFP - Graphics: [**Horizontal Front Porch**](https://en.wikipedia.org/wiki/Horizontal_blanking_interval) + In the Horizontal blanking interval, this is the blank before the + start of the next scanline. * HID - [**Human Interface Device**](https://en.wikipedia.org/wiki/Human_interface_device) -* HOB - UEFI: Hand-Off Block -* HPD - Hot-Plug Detect +* HOB - UEFI: Hand-Off Block. +* HPD - Hot-Plug Detect. * HPET - [**High Precision Event Timer**](https://en.wikipedia.org/wiki/High_Precision_Event_Timer) -* HSP - AMD: Hardware Security Processor -* HSPHY - USB: USB3 High-Speed PHY -* HSTI - Hardware Security Test Interface -* HSW - Intel: Haswell -* Hybrid S3 - System Power State: This is where the operating system +* HSP - AMD: Hardware Security Processor. +* HSPHY - USB: USB3 High-Speed PHY. +* HSTI - Hardware Security Test Interface. +* HSW - Intel: Haswell. +* Hybrid S3 - System Power State: This is where the operating system saves the contents of RAM out to the Hard drive, as if preparing to go - to S4, but then goes into suspend to RAM. This allows the system to + to S4, but then goes into suspend to RAM. This allows the system to resume quickly from S3 if the system stays powered, and resume from the disk if power is lost. * Hypertransport - AMD: The [**Hypertransport**](https://en.wikipedia.org/wiki/Hypertransport) bus is an older (2001-2017) high-speed electrical interconnection protocol specification between CPU, Memory, and (occasionally) peripheral - devices. This was originally called the Lightning Data Transport + devices. This was originally called the Lightning Data Transport (LDT), which could be seen reflected in various register names. Hypertransport was replaced by AMD's Infinity Fabric (IF) on AMD's Zen processors. @@ -462,26 +499,28 @@ ## I -* I$ - Instruction Cache +* I$ - Instruction Cache. * I2C - **Inter-Integrated Circuit** is a bidirectional 2-wire bus for communication generally between different ICs on a circuit board. * [https://www.esacademy.com/en/library/technical-articles-and-documents/misce… * I2S - [**Inter-IC Sound**](https://en.wikipedia.org/wiki/I%C2%B2S) * I3C - [**I3c**](https://en.wikipedia.org/wiki/I3C_%28bus%29) is not an - acronym - The follower to I2C (Inter-Integrated Circuit) - - Also known as SenseWire -* IA - Intel Architecture -* IA-64 - Intel Itanium 64-bit architecture -* IAFC - RISC-V: [**RISC-V Base Integer instruction set**](https://en.wikipedia.org/wiki/RISC-V), plus atomic instructions, single precision floating point instructions, and compressed instructions -* IBB – Initial Boot Block -* IBV - Independent BIOS Vendor -* IC - Integrated Circuit -* ICL - Intel: Ice Lake -* IDE - Software: Integrated Development Environment + acronym - The follower to I2C (Inter-Integrated Circuit). + Also known as SenseWire. +* IA - Intel Architecture. +* IA-64 - Intel Itanium 64-bit architecture. +* IAFC - RISC-V: [**RISC-V Base Integer instruction set**](https://en.wikipedia.org/wiki/RISC-V), + plus atomic instructions, single precision floating point instructions, + and compressed instructions. +* IBB – Initial Boot Block. +* IBV - Independent BIOS Vendor. +* IC - Integrated Circuit. +* ICL - Intel: Ice Lake. +* IDE - Software: Integrated Development Environment. * IDE - Integrated Drive Electronics - A type of hard drive - Used interchangeable with ATA, though IDE describes the drive, and ATA - describes the interface. Generally replaced by SATA (Though again, - SATA describes the interface, not actually the drive) + describes the interface. Generally replaced by SATA (Though again, + SATA describes the interface, not actually the drive). * IDSEL/AD - Initialization Device SELect/Address and Data. Each PCI slot has a signal called IDSEL. It is used to differentiate between the different slots. @@ -489,8 +528,10 @@ * IF - AMD: [**Infinity Fabric**](https://en.wikipedia.org/wiki/HyperTransport#Infinity_Fabric) is a superset of AMD's earlier Hypertransport interconnect. -* IFD - Intel: Intel Flash Descriptor -* IMAFC - RISC-V: [**RISC-V Base Integer instruction set**](https://en.wikipedia.org/wiki/RISC-V), plus integer multiply & divide, atomic instructions, single precision floating point instructions, and compressed instructions +* IFD - Intel: Intel Flash Descriptor. +* IMAFC - RISC-V: [**RISC-V Base Integer instruction set**](https://en.wikipedia.org/wiki/RISC-V), + plus integer multiply & divide, atomic instructions, single precision + floating point instructions, and compressed instructions. * IMC - AMD: Integrated micro-controller - An 8051 microcontroller built into some AMD FCHs (Fusion Controller Hubs) and Southbridge chips. This never worked well for anything beyond fan control and caused @@ -498,44 +539,44 @@ devices from communicating with the flash chip at runtime. * IMC - Integrated Memory Controller - This is a less usual use of the IMC acronym, but seems to be growing somewhat. -* IO or I/O - Input/Output -* IoC - Security: Indicator of Compromise -* IOC - Intel: I/O Cache -* IOE - Intel: I/O Expander -* IOHC - AMD: I/O Hub Controller -* IOM - Intel: I/O Manager +* IO or I/O - Input/Output. +* IoC - Security: Indicator of Compromise. +* IOC - Intel: I/O Cache. +* IOE - Intel: I/O Expander. +* IOHC - AMD: I/O Hub Controller. +* IOM - Intel: I/O Manager. * IOMMU - [**I/O Memory Management Unit**](https://en.wikipedia.org/wiki/Input%E2%80%93output_memory_managemen… * IOMUX - AMD: The I/O Mux block controls how each GPIO is configured. -* IOSF - Intel: Intel On-chip System Fabric -* IP - Intellectual Property -* IP - Internet Protocol -* IPC - Inter-Processor Communication/Inter-Process Communication -* IPI - Inter Processor Interrupt -* IPMI - Intelligent Platform Management Interface -* IRQ - Interrupt Request -* ISA - Instruction set architecture +* IOSF - Intel: Intel On-chip System Fabric. +* IP - Intellectual Property. +* IP - Internet Protocol. +* IPC - Inter-Processor Communication / Inter-Process Communication. +* IPI - Inter Processor Interrupt. +* IPMI - Intelligent Platform Management Interface. +* IRQ - Interrupt Request. +* ISA - Instruction set architecture. * ISA (bus) - Industry standard architecture - Replaced generally by PCI - (Peripheral Control Interface) -* ISDN - Integrated Services Digital Network -* ISH - AMD PSP: Image Slot Header + (Peripheral Control Interface). +* ISDN - Integrated Services Digital Network. +* ISH - AMD PSP: Image Slot Header. * ISH - Intel: Integrated Sensor Hub - A microcontroller built into the processor to help offload data processing from various sensors on a mainboard. -* ISP - Internet Service Provider -* ISP - Image-Signal-Process -* IVHD - ACPI: I/O Virtualization Hardware Definition -* IVMD - ACPI: I/O Virtualization Memory Definition -* IVRS - I/O Virtualization Reporting Structure -* IWYU - Include What you Use - A tool to help with include file use +* ISP - Internet Service Provider. +* ISP - Image-Signal-Processor. +* IVHD - ACPI: I/O Virtualization Hardware Definition. +* IVMD - ACPI: I/O Virtualization Memory Definition. +* IVRS - I/O Virtualization Reporting Structure. +* IWYU - Include What you Use - A tool to help with include file use. ## J -* JEDEC - Joint Electron Device Engineering Council -* JSL - Intel: Jasper Lake +* JEDEC - Joint Electron Device Engineering Council. +* JSL - Intel: Jasper Lake. * JTAG - The [**Joint Test Action Group**](https://en.wikipedia.org/wiki/JTAG) created a standard for - communicating between chips to verify and test ICs and PCB designs. + communicating between chips to verify and test ICs and PCB designs. The standard was named after the group, and has become a standard method of accessing special debug functions on a chip allowing for hardware-level debug of both the hardware and software. @@ -543,8 +584,11 @@ ## K -* KBL - Intel: Kaby Lake -* KVM - Keyboard Video Mouse +* KBL - Intel: Kaby Lake. +* Kconfig - **Kernel Configuration** - The configuration system originally + developed for the Linux kernel, used by coreboot (via Meitä) to manage + build-time options. +* KVM - Keyboard Video Mouse. ## L @@ -552,117 +596,121 @@ serial link. * L1-Cache - The fastest but smallest memory cache on a processor. Frequently split into Instruction and Data caches (I-Cache / D-Cache, - also occasionally abbreviated as i$ and d$) + also occasionally abbreviated as i$ and d$). * L1 - ASPM Power State: The L1 power state shuts the PCIe link off completely until triggered to resume by the CLKREQ# signal. * L2-Cache - The second level of memory cache on a processor, this is a - larger cache than L1, but takes longer to access. Typically checked + larger cache than L1, but takes longer to access. Typically checked only after data has not been found in the L1-cache. * L3-Cache - The Third, and typically final memory cache level on a - processor. The L3 cache is typically quite a bit larger than the L1 & + processor. The L3 cache is typically quite a bit larger than the L1 & L2 caches, but again takes longer to access, though it's still much - faster than reading memory. The L3 cache is frequently shared between + faster than reading memory. The L3 cache is frequently shared between multiple cores on a modern CPU. -* LAN - Local Area Network -* LAPIC - Local APIC -* LBA - Logical Block Address -* LCD - Liquid Crystal Display -* LCAP - PCIe: Link Capabilities -* LED - Light Emitting Diode -* LF - Line Feed - The standard Unix EOL (End-of-Line) marker. -* LGTM - Looks Good To Me -* LLC - Last Level Cache +* LAN - Local Area Network. +* LAPIC - Local APIC. +* LBA - Logical Block Address. +* LCD - Liquid Crystal Display. +* LCAP - PCIe: Link Capabilities. +* LED - Light Emitting Diode. +* LF - Line Feed - `\n` - The standard Unix EOL (End-of-Line) marker. +* LGTM - Looks Good To Me. +* LLC - Last Level Cache. * LLVM - Initially stood for Low Level Virtual Machine, but now is just the name of the project, as it has expanded past its original goal. -* LP5 - LPDDR5 +* LP5 - LPDDR5. * LPDDR5 - [**Low-Power DDR 5 SDRAM**](https://en.wikipedia.org/wiki/LPDDR) * LPC - The [**Low Pin count**](http://www.intel.com/design/chipsets/industry/lpc.htm) bus was a replacement for the ISA bus, created by serializing a number of parallel signals to get rid of those connections. -* LPM - USB: Link Power Management -* LPT - Line Print Terminal, Local Print Terminal, or Line Printer. - - The Parallel Port +* LPM - USB: Link Power Management. +* LPT - Line Print Terminal, Local Print Terminal, or Line Printer - + The Parallel Port. * LRU - Least Recently Used - a rule used in operating systems that utilises a paging system. LRU selects a page to be paged out if it has been used less recently than any other page. This may be applied to a cache system as well. -* LSB - Least Significant Bit +* LSB - Least Significant Bit. * LTE - Telecommunication: [**Long-Term Evolution**](https://en.wikipedia.org/wiki/LTE_%28telecommunication%29) -* LVDS - Low-Voltage Differential Signaling +* LVDS - Low-Voltage Differential Signaling. ## M * M.2 - An interface specification for small peripheral cards. -* MAC Address - Media Access Control Address +* MAC Address - Media Access Control Address. * MAFS - (eSPI) Master Attached Flash Sharing: Flash components are - attached to the controller device and may be accessed by by the + attached to the controller device and may be accessed by the peripheral devices through the eSPI flash access channel. -* MBP - Intel UEFI: ME-to-BIOS Payload -* MBR - Master Boot Record +* MBP - Intel UEFI: ME-to-BIOS Payload. +* MBR - Master Boot Record. * MCA - [**Machine Check Architecture**](https://en.wikipedia.org/wiki/Machine_Check_Architecture) -* MCR - Machine Check Registers +* MCR - Machine Check Registers. * MCTP - [**Management Component Transport Protocol**](https://en.wikipedia.org/wiki/Management_Component_Transport_Pr… -* MCU - Memory Control Unit +* MCU - Memory Control Unit. * MCU - [**MicroController Unit**](https://en.wikipedia.org/wiki/Microcontroller) -* MCUPM - Mediatek: MCUPM is a hardware module which is used for MCUSYS Power Management. MCUPM firmware (mcupm.bin) is loaded into MCUPM SRAM at system initialization. -* MDFIO - Intel: Multi-Die Fabric IO -* MDN - AMD: Mendocino -* mDP - Mini DisplayPort connector -* ME - Intel: Management Engine -* MEI - Intel: ME Interface (Previously known as HECI) +* MCUPM - Mediatek: MCUPM is a hardware module which is used for MCUSYS + Power Management. MCUPM firmware (mcupm.bin) is loaded into MCUPM + SRAM at system initialization. +* MDFIO - Intel: Multi-Die Fabric IO. +* MDN - AMD: Mendocino. +* mDP - Mini DisplayPort connector. +* ME - Intel: Management Engine. +* Meitä - **coreboot Configuration** - The name of coreboot's build + configuration system, derived from Kconfig. +* MEI - Intel: ME Interface (Previously known as HECI). * Memory training - the process of finding the best speeds, voltages, and delays for system memory. -* MHU: ARM: Message Handling Unit -* MIPI: The [**Mobile Industry Processor +* MHU - ARM: Message Handling Unit. +* MIPI - The [**Mobile Industry Processor Interface**](https://en.wikipedia.org/wiki/MIPI_Alliance) Alliance has developed a number of different specifications for mobile devices. The Camera Serial Interface (CSI) is a widely used interface that has made its way into laptops. -* MIPS - Millions of Instructions per Second +* MIPS - Millions of Instructions per Second. * MIPS (processor) - Microprocessor without Interlocked Pipelined Stages. -* MKBP - Matrix Keyboard Protocol +* MKBP - Matrix Keyboard Protocol. * MMC - [**MultiMedia Card**](https://en.wikipedia.org/wiki/MultiMediaCard) * MMIO - [**Memory Mapped I/O**](https://en.wikipedia.org/wiki/MMIO) allows peripherals' memory or registers to be accessed directly - through the memory bus. When the memory bus size was very small, this + through the memory bus. When the memory bus size was very small, this was initially done by hiding any memory at that address, effectively - wasting that memory. In modern systems, that memory is typically + wasting that memory. In modern systems, that memory is typically moved to the end of the physical memory space, freeing a 'hole' to map devices into. -* MMU - Memory Management Unit +* MMU - Memory Management Unit. * MMX - Officially, not an acronym, trademarked by Intel. Unofficially, Matrix Math eXtension. -* MODEM - Modulator-Demodulator -* Modern Standby - Microsoft's name for the S0iX states -* MOP - Macro-Operation -* MOS - Metal-Oxide-Silicon -* MP - Production Timeline: Mass Production -* MPU - Memory Protection Unit +* MODEM - Modulator-Demodulator. +* Modern Standby - Microsoft's name for the S0iX states. +* MOP - Macro-Operation. +* MOS - Metal-Oxide-Silicon. +* MP - Production Timeline: Mass Production. +* MPU - Memory Protection Unit. * MPTable - The Intel [**MultiProcessor specification**](https://en.wikipedia.org/wiki/MultiProcessor_Specification) is a hardware compatibility guide for machine hardware designers and OS software writers to produce SMP-capable machines and OSes in a vendor-independent manner. Version 1.1 of the spec was released in - 1994, and the 1.4 version was released in 1995. This has been + 1994, and the 1.4 version was released in 1995. This has been generally superseded by the ACPI tables. -* MRC - Intel: Memory Reference Code -* MSB - Most Significant Bit -* MSI - Message Signaled Interrupt -* MSR - Machine-Specific Register -* MTS or MT/s - MegaTransfers per second -* MTL - Intel: Meteor Lake -* MTL - ARM: MHU Transport Layer +* MRC - Intel: Memory Reference Code. +* MSB - Most Significant Bit. +* MSI - Message Signaled Interrupt. +* MSR - Machine-Specific Register. +* MTS or MT/s - MegaTransfers per second. +* MTL - Intel: Meteor Lake. +* MTL - ARM: MHU Transport Layer. * MTRR - [**Memory Type and Range Register**](https://en.wikipedia.org/wiki/MTRR) allows to set the cache behaviour on memory access in x86. Basically, - it tells the CPU how to cache certain ranges of memory - (e.g. write-through, write-combining, write-back...). Memory ranges - are specified over physical address ranges. In Linux, they are visible + it tells the CPU how to cache certain ranges of memory (e.g. + write-through, write-combining, write-back...). Memory ranges are + specified over physical address ranges. In Linux, they are visible over `/proc/mtrr` and they can be modified there. For further information, see the [**Linux documentation**](https://www.kernel.org/doc/html/v5.19/x86/pat.html). * MXM - PCIe: [**Mobile PCI Express Module**](https://en.wikipedia.org/wiki/Mobile_PCI_Express_Module) @@ -670,10 +718,10 @@ ## N -* Nack - Negative Acknowledgement -* NB - North Bridge -* NBCI - Nvidia: NoteBook Common Interface -* NC - GPIOs: No Connect +* Nack - Negative Acknowledgement. +* NB - North Bridge. +* NBCI - Nvidia: NoteBook Common Interface. +* NC - GPIOs: No Connect. * NDA - Non-Disclosure Agreement. * NF - GPIOs: Native Function - GPIOs frequently have multiple different functions, one of which is defined as the default, or Native function. @@ -681,76 +729,84 @@ Communication**](https://en.wikipedia.org/wiki/Near-field_communication) * NGFF - [**Next Generation Form Factor**](https://en.wikipedia.org/wiki/M.2) - The original name for - M.2 -* NHLT - ACPI Table - Non-HDA Link Table -* NIC - Network Interface Card -* NMI - Non-maskable interrupt + M.2. +* NHLT - ACPI Table - Non-HDA Link Table. +* NIC - Network Interface Card. +* NMI - Non-maskable interrupt. * Nonce - Cryptography: [**Number used once**](https://en.wikipedia.org/wiki/Cryptographic_nonce) -* NOP - No Operation -* NTFS - New Technology File System +* NOP - No Operation. +* NTFS - New Technology File System. * NVME - Non-Volatile Memory Express - An SSD interface that allows access to the flash memory through a PCIe bus. -* NVPCF - Nvidia Platform and Control Framework -* NVVDD - Nvidia Power: Core voltage -* NX - No Execute +* NVPCF - Nvidia Platform and Control Framework. +* NVRAM - **Non-Volatile Random Access Memory** - Memory that retains its + data when power is removed. Often used to store firmware settings. + (CMOS RAM is a specific type of NVRAM). +* NVVDD - Nvidia Power: Core voltage. +* NX - No Execute. ## O -* ODH - GPIOs: Open Drain High - High is driven to the reference voltage, low is a high-impedance state -* ODL - GPIOs: Open Drain Low - Low is driven to ground, High is a high-impedance state. +* ODH - GPIOs: Open Drain High - High is driven to the reference + voltage, low is a high-impedance state. +* ODL - GPIOs: Open Drain Low - Low is driven to ground, High is a + high-impedance state. * ODM - [**Original Design Manufacturer**](https://en.wikipedia.org/wiki/Original_design_manufacturer) * OEM - [**Original Equipment Manufacturer**](https://en.wikipedia.org/wiki/Original_equipment_manufactur… * OHCI - [**Open Host Controller Interface**](https://en.wikipedia.org/wiki/Host_Controller_Interface_%28USB… - non-proprietary USB Host controller for USB 1.1 (May also refer to the open host controller for IEEE 1394, but this is less common). -* OOBE - Out Of the Box Experience -* OPP - ARM: Operating Performance Points -* OS - Operating System -* OTA - Over the Air -* OTP - One Time Programmable +* OOBE - Out Of the Box Experience. +* OPP - ARM: Operating Performance Points. +* OS - Operating System. +* OTA - Over the Air. +* OTP - One Time Programmable. ## P -* PAE - physical address extension -* PAL - Programmable Array Logic +* P-state - **Processor Performance State** - ACPI-defined states (Px) + that allow the OS to control CPU frequency and voltage for performance + scaling. +* PAE - physical address extension. +* PAL - Programmable Array Logic. * PAM - Intel: Programmable Attribute Map - This is the legacy BIOS - region from 0xC_0000 to 0xF_FFFF + region from 0xC0000 to 0xFFFFF. * PAT - [**Page Attribute Table**](https://en.wikipedia.org/wiki/Page_attribute_table) This can be used independently or in combination with MTRR to setup memory type - access ranges. Allows more finely-grained control than MTRR. Compared to MTRR, - which sets memory types by physical address ranges, PAT sets them at Page - level. + access ranges. Allows more finely-grained control than MTRR. Compared + to MTRR, which sets memory types by physical address ranges, PAT sets + them at Page level. * PAT - Intel: [**Performance Acceleration Technology**](https://en.wikipedia.org/wiki/Performance_acceleration_techno… * PATA - Parallel Advanced Technology Attachment - A renaming of ATA after SATA became the standard. * PAVP - [**Intel: Protected Audio-Video Path**](https://en.wikipedia.org/wiki/Intel_GMA#Protected_Audio_Video_Path) -* PC - Personal Computer -* PC AT - Personal Computer Advanced Technology +* PC - Personal Computer. +* PC AT - Personal Computer Advanced Technology. * PC100 - An SDRAM specification for a 100MHz memory bus. -* PCB - Printed Circuit Board -* PCD - UEFI: Platform Configuration Database +* PCB - Printed Circuit Board. +* PCD - UEFI: Platform Configuration Database. * PCH - Intel: [**Platform Controller Hub**](https://en.wikipedia.org/wiki/Platform_Controller_Hub) * PCI - [**Peripheral Control Interconnect**](https://en.wikipedia.org/wiki/Peripheral_Component_Intercon… - - Replaced generally by PCIe (PCI Express) + - Replaced generally by PCIe (PCI Express). * PCI Configuration Space - The [**PCI Config space**](https://en.wikipedia.org/wiki/PCI_Configuration_Space) is an [address space](https://en.wikipedia.org/wiki/Address_space) for all - PCI devices. Originally, this address space was accessed through an + PCI devices. Originally, this address space was accessed through an index/data pair by writing the address that you wanted to read/write into the I/O address 0xCF8, then reading or writing I/O Address 0xCFC. This has been updated to an MMIO method which increases each PCI function's configuration space from 256 bytes to 4K. * PCIe - [**PCI Express**](https://en.wikipedia.org/wiki/Pci_express) -* PCMCIA: Personal Computer Memory Card International Association +* PCMCIA - Personal Computer Memory Card International Association. * PCO - AMD: [**Picasso**](https://en.wikichip.org/wiki/amd/cores/picasso) -* PCR: TPM: Platform Configuration Register +* PCR - TPM: Platform Configuration Register. * PD - GPIOs: Pull-Down - Drives the pin to ground through a resistor. The resistor allows the pin to be set to the reference voltage as needed. @@ -758,27 +814,27 @@ needs and availability between two devices, typically over USB type C. * PEG - PCIe Graphics - A (typically) x16 PCIe slot connected to the CPU for higher graphics bandwidth and lower latency. -* PEI - UEFI: Pre-EFI Initialization -* PEIM - UEFI: PEI Module -* PEP - Intel: Power Engine Plug-in -* PEXVDD - Nvidia Power: PCIExpress Voltage -* PHX - AMD: Phoenix SoC +* PEI - UEFI: Pre-EFI Initialization. +* PEIM - UEFI: PEI Module. +* PEP - Intel: Power Engine Plug-in. +* PEXVDD - Nvidia Power: PCIExpress Voltage. +* PHX - AMD: Phoenix SoC. * PHY - [**PHYsical layer**](https://en.wikipedia.org/wiki/PHY) - The hardware that implements the send/receive functionality of a communication protocol. -* PI - Platform Initialization +* PI - Platform Initialization. * PIC - [**Programmable Interrupt Controller**](https://en.wikipedia.org/wiki/Programmable_interrupt_controll… * PII - [**Personally Identifiable Information**](https://en.wikipedia.org/wiki/Personal_data) * PIO - [**Programmed I/O**](https://en.wikipedia.org/wiki/Programmed_input%E2%80%93output) -* PIR - PCI Interrupt Router +* PIR - PCI Interrupt Router. * PIR Table - The [**PCI Interrupt Routing Table**](https://web.archive.org/web/20080206072638/http://www.microsoft.co… was a Microsoft specification that allowed windows to determine how each PCI slot was wired to the interrupt router. -* PIRQ - PCI IRQ +* PIRQ - PCI IRQ. * PIT - Generally refers to the 8253/8254 [**Programmable Interval Timer**](https://en.wikipedia.org/wiki/Programmable_interval_timer). * PLCC - [**Plastic leaded chip @@ -786,15 +842,15 @@ * PLL - [**Phase-Locked Loop**](https://en.wikipedia.org/wiki/Phase-locked_loop) * PM - Platform Management -* PM - Power Management -* PMC Intel: Power Management Controller -* PMIC - Power Management IC (Pronounced "P-mick") -* PMIO - Port-Mapped I/O -* PMU - Power Management Unit -* PNP - Plug aNd Play -* PoP - Point-of-Presence -* POR - Plan of Record -* POR - Power On Reset +* PM - Power Management - Control of power usage in components/system. +* PMC - Intel: Power Management Controller. +* PMIC - Power Management IC (Pronounced "P-mick"). +* PMIO - Port-Mapped I/O. +* PMU - Power Management Unit. +* PNP - Plug aNd Play. +* PoP - Point-of-Presence. +* POR - Plan of Record. +* POR - Power On Reset. * Port80 - The [**I/O port 0x80**](https://en.wikipedia.org/wiki/Power-on_self-test#Progress_and_error… is the address for BIOS writes to update diagnostic information during @@ -803,107 +859,113 @@ Test**](https://en.wikipedia.org/wiki/Power-on_self-test) * POTS - [**Plain Old Telephone Service**](https://en.wikipedia.org/wiki/Plain_old_telephone_service) -* PPI - UEFI: PEIM-to-PEIM Interface -* PPR - Processor Programming Reference -* PPT - AMD: Package Power Tracking -* PROM - Programmable Read Only Memory +* PPI - UEFI: PEIM-to-PEIM Interface. +* PPR - Processor Programming Reference. +* PPT - AMD: Package Power Tracking. +* PROM - Programmable Read Only Memory. * Proto - Production Timeline: The first initial production to test key concepts. -* PSE - Page Size Extention -* PSF - Intel: Primary Sideband Fabric -* PSP - AMD: Platform Security Processor -* PSPP - AMD: PCIE Speed Power Policy -* PSR - Intel: Platform Service Record -* PSR - Graphics: Panel Self-Refresh - This is a power-savings feature specified in eDP +* PSE - Page Size Extention. +* PSF - Intel: Primary Sideband Fabric. +* PSP - AMD: Platform Security Processor. +* PSPP - AMD: PCIE Speed Power Policy. +* PSR - Intel: Platform Service Record. +* PSR - Graphics: Panel Self-Refresh - This is a power-savings feature + specified in eDP. * PTT - Intel: Platform Trust Technology - Intel's firmware based TPM. * PU - GPIOs: Pull-Up - Drives the pin to reference voltage through a resistor. The resistor allows the signal to still be set to ground when needed. -* PVT - Production Timeline: (Production Validation Test -* PWM - Pulse Width Modulation -* PXE - Pre-boot Execution Environment +* PVT - Production Timeline: Production Validation Test. +* PWM - Pulse Width Modulation. +* PXE - Pre-boot Execution Environment. ## Q -* QOS - Quality of Service +* QOS - Quality of Service. ## R * RAID - redundant array of inexpensive disks - as opposed to SLED - single large expensive disk. -* RAM - Random Access Memory +* RAM - Random Access Memory. * RAMID - Boards that have soldered-down memory (no DIMMs) can have various different sizes, speeds, and brands of memory chips attached. - Because there is no SPD, (for cost savings) the memory needs to be - identified in a different manner. The simplest of these is done using + Because there is no SPD (for cost savings), the memory needs to be + identified in a different manner. The simplest of these is done using a set of 3 or 4 GPIOs to allow 8 to 16 different memory chips to be used. -* RAPL - Running Average Power Limit -* RCB - PCIe: Read Completion Boundary - Sets the address alignment on which a read request may be serviced with multiple completions +* RAPL - Running Average Power Limit. +* RCB - PCIe: Read Completion Boundary - Sets the address alignment on + which a read request may be serviced with multiple completions. * RCS - [**Revision control system**](https://en.wikipedia.org/wiki/Revision_Control_System) * Real mode - The original 20-bit addressing mode of the 8086 & 8088 computers, allowing the system to access 1MiB of memory through a - Segment:Offset index pair. In 2022, this is still the mode that + Segment:Offset index pair. In 2022, this is still the mode that x86-64 processors are in at the reset vector! * RDMA - [**Remote Direct Memory Access**](https://en.wikipedia.org/wiki/Remote_Direct_Memory_Access) is a concept whereby two or more computers communicate via DMA directly from main memory of one system to the main memory of another. -* RFC - Request for Comment +* RFC - Request for Comment. * RFI - [**Radio-Frequency Interference**](https://en.wikipedia.org/wiki/Electromagnetic_interference) -* RGB - Red, Green, Blue -* RISC - Reduced Instruction Set Computer -* RMA - Return Merchandise Authorization -* RO - Read Only -* ROM - Read Only Memory -* RoT - Root of Trust +* RGB - Red, Green, Blue. +* RISC - Reduced Instruction Set Computer. +* RMA - Return Merchandise Authorization. +* RO - Read Only. +* ROM - Read Only Memory. +* RoT - Root of Trust. * RPL - Intel: [**Raptor Lake**](https://en.wikipedia.org/wiki/Raptor_Lake) -* RPP - Intel: Raptor Point PCH -* RRG - AMD (ATI): Register Reference Guide -* RSDP - Root System Description Pointer -* RTC - Real Time Clock -* RTD3 - Power State: Runtime D3 -* RTFM - Read the Fucking Manual -* RTOS - Real-Time Operating System -* RVP - Intel: Reference Validation Platform -* RW - Read / Write -* RX - Receive +* RPP - Intel: Raptor Point PCH. +* RRG - AMD (ATI): Register Reference Guide. +* RSDP - Root System Description Pointer. +* RTC - Real Time Clock. +* RTD3 - Power State: Runtime D3. +* RTFM - Read the Fucking (or 'Friendly' if you don't enjoy cursing) Manual. +* RTOS - Real-Time Operating System. +* RVP - Intel: Reference Validation Platform. +* RW - Read / Write. +* RX - Receive. ## S * S-states - ACPI System Power States: [**Sleep states**](https://uefi.org/specs/ACPI/6.4/16_Waking_and_Sleeping/sleeping-s… -* S0 - ACPI System Power State: Fully running +* S0 - ACPI System Power State: Fully running. * S0 - S5 - ACPI System power states level 0 - 5, with each higher numbered power state being (theoretically) lower power than the previous, and (again theoretically) taking longer to get back to a fully running system than the previous. -* S1 - ACPI System Power State: Standby - This isn’t use much anymore, +* S0iX - **S0 Low Power Idle** - Intel-specific low-power states + (e.g., S0i1, S0i3) entered while the system remains in the ACPI S0 + state, enabling faster resume times than S3. Often associated with + Microsoft's "Modern Standby". +* S1 - ACPI System Power State: Standby - This isn't use much anymore, but it used to put the Processor into a powered, but idle state, power down any drives, and turn off the display. This would wake up almost instantly because no processor context was lost in this state. * S2 - ACPI System Power State: Lower power than S1, Higher power than - S3, I don’t know that this state was ever well defined by any group. + S3. This state was never well defined or widely implemented. * S3 - ACPI System Power State: Suspend to RAM - A low-power state where the processor context is copied to the system Memory, then the - processor and all peripherals are powered off. On wake, or resume, + processor and all peripherals are powered off. On wake, or resume, the system starts to boot normally, then switches to restore the memory registers to the previous settings, restore the processor context from memory, and jump back to the operating system to pick up where it left off. -* S4 - ACPI System Power State: Suspend to Disk. The processor context +* S4 - ACPI System Power State: Suspend to Disk. The processor context and all the contents of memory are copied to the hard drive. This is typically fully handled by the operating system, so resume is a normal boot through all of the firmware, then the OS restore the original - contents of memory. Any critical processor state is restored. -* S5 - ACPI System Power State: System is “completely powered off”, but + contents of memory. Any critical processor state is restored. +* S5 - ACPI System Power State: System is "completely powered off", but still has power going to the board. * SAFS - (eSPI) Slave Attached Flash Sharing: Flash is attached to the - peripheral device. Only valid for server platforms. + peripheral device. Only valid for server platforms. * SAGV - Intel: System Agent Geyserville. The original internal name for the feature eventually released as Speedstep which controls the processor voltage and frequencies. @@ -914,75 +976,75 @@ coreboot as a table. * SAS - Serial Attached SCSI - A serialized version of SCSI used mostly for high performance hard drives and tape drives. -* SATA - Serial Advanced Technology Attachment -* SB - South Bridge -* SB-RMI - AMD: Sideband Remote Management Interface -* SB-TSI - SideBand Temperature Sensor Interface -* SBA - SideBand Addressing -* SBI - SideBand Interface -* SBOM - Software Bill of Materials -* SCI - System Control Interrupt -* SCP - ARM: System Control Processor -* SCP - Network Protocol: Secure Copy +* SATA - Serial Advanced Technology Attachment. +* SB - South Bridge. +* SB-RMI - AMD: Sideband Remote Management Interface. +* SB-TSI - SideBand Temperature Sensor Interface. +* SBA - SideBand Addressing. +* SBI - SideBand Interface. +* SBOM - Software Bill of Materials. +* SCI - System Control Interrupt. +* SCP - ARM: System Control Processor. +* SCP - Network Protocol: Secure Copy. * SCSI - Small Computer System Interface - A high-bandwidth - communication interface for peripherals. This is a very old interface + communication interface for peripherals. This is a very old interface that has seen numerous updates and is still used today, primarily in - SAS (Serial Attached SCSI). The initial version is now often referred + SAS (Serial Attached SCSI). The initial version is now often referred to as Parallel SCSI. -* SD - [**Secure Digital**](https://en.wikipedia.org/wiki/SD_card) card -* SDHCI - SD Host Controller Interface -* SDRAM - Synchronous DRAM -* SDLE: AMD: Stardust Dynamic Load Emulator +* SD - [**Secure Digital**](https://en.wikipedia.org/wiki/SD_card) card. +* SDHCI - SD Host Controller Interface. +* SDRAM - Synchronous DRAM. +* SDLE - AMD: Stardust Dynamic Load Emulator. * SEEP - Serial EEPROM (Electrically Erasable Programmable Read-Only - Memory) -* SEV - AMD: Secure Encrypted Virtualization -* SF - Snoop Filter + Memory). +* SEV - AMD: Secure Encrypted Virtualization. +* SF - Snoop Filter. * Shadow RAM - RAM which content is copied from ROM residing at the same address for speedup purposes. * Shim - A small piece of code whose only purpose is to act as an interface to load another piece of code. -* SIMD - Single Instruction, Multiple Data -* SIMM - Single Inline Memory Module -* SIPI - Startup Inter Processor Interrupt +* SIMD - Single Instruction, Multiple Data. +* SIMM - Single Inline Memory Module. +* SIPI - Startup Inter Processor Interrupt. * SIO - [**Super I/O**](https://en.wikipedia.org/wiki/Super_I/O) -* SKL - Intel: SkyLake -* SKU - Stock Keeping Unit -* SMART: [**Self-Monitoring Analysis And Reporting +* SKL - Intel: SkyLake. +* SKU - Stock Keeping Unit. +* SMART - [**Self-Monitoring Analysis And Reporting Technology**](https://en.wikipedia.org/wiki/S.M.A.R.T.) * SMBIOS - [**System Management BIOS**](https://en.wikipedia.org/wiki/System_Management_BIOS) * SMBus - [**System Management Bus**](https://en.wikipedia.org/wiki/System_Management_Bus) * [http://www.smbus.org/](http://www.smbus.org/) -* SME - AMD: Secure Memory Encryption -* SMI - System management interrupt +* SME - AMD: Secure Memory Encryption. +* SMI - System management interrupt. * SMM - [**System management mode**](https://en.wikipedia.org/wiki/System_Management_Mode) -* SMN - AMD: System Management Network -* SMRAM - System Management RAM -* SMT - Simultaneous Multithreading -* SMT - Surface Mount -* SMT - Symmetric Multithreading -* SNP - AMD: Secure Nested Paging -* SMU - AMD: System Management Unit -* SO-DIMM: Small Outline Dual In-Line Memory Module -* SoC - System on a Chip +* SMN - AMD: System Management Network. +* SMRAM - System Management RAM. +* SMT - Simultaneous Multithreading. +* SMT - Surface Mount. +* SMT - Symmetric Multithreading. +* SNP - AMD: Secure Nested Paging. +* SMU - AMD: System Management Unit. +* SO-DIMM - Small Outline Dual In-Line Memory Module. +* SoC - System on a Chip. * SOIC - [**Small-Outline Integrated Circuit**](https://en.wikipedia.org/wiki/Small-outline_integrated_circuit) * SPD - [**Serial Presence Detect**](https://en.wikipedia.org/wiki/Serial_presence_detect) * SPI - [**Serial Peripheral Interface**](https://en.wikipedia.org/wiki/Serial_Peripheral_Interface) -* SPL - AMD: Security Patch Level -* SPM - Mediatek: System Power Manager -* SPMI - MIPI: System Power Management Interface -* SPR - Sapphire Rapids -* SRAM - Static Random Access Memory -* SSD - Solid State Drive -* SSDT - Secondary System Descriptor Table - ACPI table -* SSE - Streaming SIMD Extensions -* SSH - Network Protocol: Secure Shell -* SSI - **Server System Infrastructure** +* SPL - AMD: Security Patch Level. +* SPM - Mediatek: System Power Manager. +* SPMI - MIPI: System Power Management Interface. +* SPR - Sapphire Rapids. +* SRAM - Static Random Access Memory. +* SSD - Solid State Drive. +* SSDT - Secondary System Descriptor Table - ACPI table. +* SSE - Streaming SIMD Extensions. +* SSH - Network Protocol: Secure Shell. +* SSI - **Server System Infrastructure**. * SSI-CEB - Physical board format: [**SSI Compact Electronics Bay**](https://en.wikipedia.org/wiki/SSI_CEB) * SSI-EEB - Physical board format: [**SSI Enterprise Electronics @@ -993,158 +1055,286 @@ * SSI-TEB - Physical board format: [**SSI Thin Electronics Bay**](https://en.wikipedia.org/wiki/SSI_CEB) * SSP - [**Speech Signal Processor**](https://en.wikipedia.org/wiki/Speech_processing) -* SSPHY - USB: USB3 Super-Speed PHY -* STAPM - AMD: Skin Temperature Aware Power Management -* STB - AMD: Smart Trace Buffer -* STG - System-Top-Group apparently a term for grouping subsystems in an SOC together? +* SSPHY - USB: USB3 Super-Speed PHY. +* STAPM - AMD: Skin Temperature Aware Power Management. +* STB - AMD: Smart Trace Buffer. +* STG - **System-Top-Group** - Used internally by some vendors (e.g., + Mediatek) to refer to a collection of subsystems within an SoC. * SuperIO - The [**Super I/O**](https://en.wikipedia.org/wiki/Super_I/O) (SIO) device provides a system with any of a number of different - peripherals. Most common are: A PS/2 Keyboard and mouse port, LPT + peripherals. Most common are: A PS/2 Keyboard and mouse port, LPT Ports, UARTS, Watchdog Timers, Floppy drive Controllers, GPIOs, or any of a number of various other devices. -* SVC - ARM: Supervisor Call -* SVI2/3 - Serial VID (Voltage Identification) Interface 2.0 / 3.0 -* SWCM - Intel: Software Connection Manager +* SVC - ARM: Supervisor Call. +* SVI2/3 - Serial VID (Voltage Identification) Interface 2.0 / 3.0. +* SWCM - Intel: Software Connection Manager. ## T -* TBT - Thunderbolt -* TBT - Intel: Turbo Boost Technology -* tBUF - I2C: The bus free time between a STOP and START condition -* TCC - Intel: Thermal Control Circuit -* TCP - Transmission Control Protocol -* TCPC - Type C Port Controller -* TCSS - Intel: Type C SubSystem -* TDMA - Time-Division Multiple Access +* TBT - Thunderbolt. +* TBT - Intel: Turbo Boost Technology. +* tBUF - I2C: The bus free time between a STOP and START condition. +* TCC - Intel: Thermal Control Circuit. +* TCG - **Trusted Computing Group** - The industry standards body + responsible for defining specifications for the TPM and related trust + technologies. +* TCP - Transmission Control Protocol. +* TCPC - Type C Port Controller. +* TCSS - Intel: Type C SubSystem. +* TDMA - Time-Division Multiple Access. * TDP - [**Thermal Design Power**](https://en.wikipedia.org/wiki/Thermal_design_power) * TEE - [**Trusted Execution Environment**](https://en.wikipedia.org/wiki/Trusted_execution_environment) -* TFTP - Network Protocol: Trivial File Transfer Protocol -* TGL - Intel: Tigerlake -* THC - Touch Host Controller +* TFTP - Network Protocol: Trivial File Transfer Protocol. +* TGL - Intel: Tigerlake. +* THC - Touch Host Controller. * Ti50 - Google: The next generation GSC (Google Security chip) on - ChromeOS devices after Cr50 -* TLA - Techtronics Logic Analyzer -* TLA - Three Letter Acronym + ChromeOS devices after Cr50. +* TLA - Techtronics Logic Analyzer. +* TLA - Three Letter Acronym. * TLB - [**Translation Lookside Buffer**](https://en.wikipedia.org/wiki/Translation_lookaside_buffer) -* TME - Intel: Total Memory Encryption -* TOCTOU - Time-Of-Check to Time-Of-Use -* TOLUM - Top of Low Usable Memory -* ToM - Top of Memory -* TPM - Trusted Platform Module -* TS - TimeStamp -* TSN - Time-Sensitive Networking +* TME - Intel: Total Memory Encryption. +* TOCTOU - Time-Of-Check to Time-Of-Use. +* TOLUM - Top of Low Usable Memory. +* ToM - Top of Memory. +* TPM - Trusted Platform Module. +* TS - TimeStamp. +* TSN - Time-Sensitive Networking. * TSC - [**Time Stamp Counter**](https://en.wikipedia.org/wiki/Time_Stamp_Counter) -* TSEG - TOM (Top of Memory) Segment -* TSR - Temperature Sensor +* TSEG - TOM (Top of Memory) Segment. +* TSR - Temperature Sensor. * TWAIN - Technology without an interesting name. -* TX - Transmit -* TXE - Intel: Trusted eXecution Engine +* TX - Transmit. +* TXE - Intel: Trusted eXecution Engine. ## U -* UART - Universal asynchronous receiver-transmitter -* UC - UnCacheable. Memory type setting in MTRR/PAT. -* uCode - [**Microcode**](https://en.wikipedia.org/wiki/Microcode) -* UDK - UEFI: UEFI Development Kit -* UDP - User Datagram Protocol -* UDMA - ATA: [**Ultra DMA**](https://en.wikipedia.org/wiki/UDMA) - The fastest transfer mode for ATA Hard Drives -* UEFI - Unified Extensible Firmware Interface -* UFC - User Facing Camera -* UFP - USB: Upstream Facing Port -* UFS - Universal Flash storage +* UART - **Universal asynchronous receiver-transmitter** - A hardware + device for asynchronous serial communication that converts parallel + data to serial data for transmission and vice versa. This is a + fundamental component in electronics that handles communication + between devices, commonly used for debugging, device-to-device + communication, and connecting to external peripherals. +* UC - **UnCacheable** - A memory type setting in MTRR/PAT that + indicates memory that should not be cached by the CPU, typically used + for memory-mapped I/O or other special memory regions where caching + would be inappropriate or could cause problems. +* uCode - [**Microcode**](https://en.wikipedia.org/wiki/Microcode) - + Low-level firmware that controls the operation of a processor's + internal circuitry, often used to fix bugs or add features to + processors after they are manufactured. +* UDK - UEFI: **UEFI Development Kit** - A development environment for + creating UEFI applications and drivers, providing tools, libraries, + and documentation for UEFI development. + +* UDP - User Datagram Protocol. + +* UDMA - ATA: [**Ultra DMA**](https://en.wikipedia.org/wiki/UDMA) - The + fastest transfer mode for ATA Hard Drives. +* UEFI - Unified Extensible Firmware Interface. +* UFC - User Facing Camera. +* UFP - USB: Upstream Facing Port. +* UFS - Universal Flash storage. * UHCI - USB: [**Universal Host Controller - Interface**](https://en.wikipedia.org/wiki/Host_controller_interface_%28USB… - - Intel proprietary USB 1.x Host controller + Interface**](https://en.wikipedia.org/wiki/Host_controller_interface_%28USB… + - Intel proprietary USB 1.x Host controller. * Unreal mode - Real mode running in a way that allows it to access the entire 4GiB of the 32-bit address space - Also known as Big real mode or Flat mode. -* UMA - Unified Memory Architecture +* UMA - Unified Memory Architecture. * UMI - AMD: [**Unified Media Interface**](https://en.wikipedia.org/wiki/Unified_Media_Interface) -* UPD - Updatable Product Data -* UPS - Uninterruptible Power Supply -* USART - Universal Synchronous/Asynchronous Receiver/Transmitter -* USB - Universal Serial Bus -* USF - Intel: Universal Scalable Firmware +* UPD - Updatable Product Data. +* UPS - Uninterruptible Power Supply. +* USART - Universal Synchronous/Asynchronous Receiver/Transmitter. +* USB - Universal Serial Bus. +* USF - Intel: Universal Scalable Firmware. ## V -* VBIOS - Video BIOS -* VBNV - Vboot Non-Volatile storage +* VBIOS - **Video BIOS** - The firmware that initializes and controls + the graphics hardware in a computer system. This is the firmware that + runs on the graphics card or integrated graphics processor to handle + low-level graphics operations and provide basic video functionality + before the operating system's graphics drivers take over. +* VBNV - **Vboot Non-Volatile storage** - A storage area used by Chrome + OS's vboot system to store persistent data across system reboots. This + is a specific implementation used in Chrome OS devices to store + important system state information that needs to persist even when the + system is powered off. +* VBOOT / vboot - **Google Verified Boot** - The secure boot process used + by Google, primarily on ChromeOS devices, to verify the integrity of + the firmware and OS. * VBT - [**Video BIOS Table**](https://www.kernel.org/doc/html/latest/gpu/i915.html#video-bios-ta… -* VDDQ Memory/Power: The supply voltage to the output buffers of a memory chip. -* VESA - Video Electronics Standards Association -* VGA: Video Graphics Array -* VID: Vendor Identifier -* VID: AMD: Voltage Identifier -* VLB - VESA Local Bus -* VOIP - Voice over IP +* VDDQ Memory/Power: The supply voltage for the DQ/DQS (data and data + strobe) signals of DRAM chips, which is typically around 1.435V by + default in modern systems. The DQ/DQS signals are used for actual data + transfer between the memory controller and the DRAM chips. +* VESA - **Video Electronics Standards Association** - An organization + that develops and maintains display and display interface standards + for the computer industry. This organization is best known for + developing standards like VGA (Video Graphics Array), DisplayPort, and + other display-related specifications that are widely used in computer + graphics and display technology. +* VGA - **Video Graphics Array** - A display standard for a video + interface introduced by IBM in 1987 that was widely used in x86 PCs + from the late 1980s through the 1990s, and its legacy support is still + present in modern systems through VGA ports or adapters. +* VID - **Vendor Identifier**. +* VID - AMD: **Voltage Identifier** - A value used to indicate the + voltage requested by or supplied to an AMD component. +* VLB - **VESA Local Bus** - A 32-bit computer bus standard that was + primarily used for video cards in the early 1990s, designed to provide + faster access to system memory than the ISA bus. This was a historical + bus standard that was popular in the early 1990s for video cards, but + was eventually replaced by PCI. It was designed to provide faster + access to system memory by directly connecting to the CPU's memory + bus. +* VOIP - **Voice over IP** - A technology that allows voice + communications and multimedia sessions to be transmitted over Internet + Protocol (IP) networks, such as the Internet. * Voodoo mode - a silly name for Big Real mode. -* VMX - Intel: CPU flag for Hardware Virtualization -* VPD - Vital Product Data -* VPN - Virtual Private Network -* VPU - Intel: Versatile Processor Unit -* VR - Voltage Regulator -* VRAM - Video Random Access Memory -* VREF Memory/Power: Reference voltage for the input lines of a chip that determines the voltage level at which the threshold between a logical 1 and a logical 0 occurs. Usually 1/2 VDDQ. -* VRM - Voltage Regulator Module -* VT-d - Intel: Virtualization Technology for Directed I/O -* VTT Memory/Power: Tracking Termination Voltage -* vUART - Virtual UART +* VMX - Intel: **Virtual Machine Extensions** - Intel's hardware + virtualization technology that provides CPU-level support for running + multiple operating systems simultaneously on a single processor. +* VPD - **Vital Product Data** - Used to store essential product + information and configuration data in a computer system's firmware. +* VPN - **Virtual Private Network** - A secure network connection that + creates an encrypted tunnel between a device and a remote server, + allowing secure data transmission over public networks. +* VPU - Intel: **Versatile Processor Unit** - A specialized processing + unit in Intel processors designed for handling specific workloads and + tasks, similar to other specialized processing units like NPUs (Neural + Processing Units) or GPUs (Graphics Processing Units). +* VR - **Voltage Regulator** - A device that maintains a constant output + voltage regardless of changes in input voltage or load conditions. + This is a fundamental component in computer systems that helps + maintain stable power delivery to various components, ensuring + reliable operation. +* VRAM - **Video Random Access Memory** - A specialized type of memory + used to store image data for display on a computer screen, commonly + found on graphics cards and integrated graphics processors. +* VREF Memory/Power: Reference voltage for the input lines of a chip + that determines the voltage level at which the threshold between a + logical 1 and a logical 0 occurs. Usually 1/2 VDDQ. +* VRM - **Voltage Regulator Module** - A module that provides the + correct voltage to a microprocessor or other component by converting + the main system voltage to the required voltage level. +* VT-d - Intel: **Virtualization Technology for Directed I/O** - Intel's + hardware virtualization feature that provides I/O device + virtualization and DMA protection for virtual machines. This + technology allows virtual machines to directly access physical I/O + devices while maintaining isolation and security through + hardware-enforced memory protection and DMA remapping. +* VTT Memory/Power: **Tracking Termination Voltage** - A voltage + reference used in memory systems for proper signal termination and + impedance matching. This voltage is particularly important in memory + systems as it helps maintain signal integrity by providing the correct + termination voltage for data lines. It's typically half of the main + memory voltage (VDDQ) and is used to properly terminate memory bus + signals. +* vUART - **Virtual UART**. ## W * WAN - [**Wide Area Network**](https://en.wikipedia.org/wiki/Wide_area_network) + - A telecommunications network that extends over a large geographic + area, typically connecting multiple local area networks (LANs) + together. * WB - Cache Policy: [**Write-Back**](https://en.wikipedia.org/wiki/Cache_%28computing%29) + - A cache policy where writes are initially stored only in the cache + and written back to memory later, improving performance but requiring + cache coherency mechanisms. * WC - Cache Policy: [**Write-Combining**](https://en.wikipedia.org/wiki/Cache_%28computing%29) -* WCAM - World-facing Camera - A camera on a device that is not intended - to be used as a webcam, but instead to film scenes away from the user. - For clamshell devices, his may be on the keyboard panel for devices - devices that open 360 degrees, or on the outside of the cover. For - tablets, it's on the the side away from the screen. -* WDT - [**WatchDog Timer**](https://en.wikipedia.org/wiki/Watchdog_timer) -* WFC - World Facing Camera -* WLAN - Wireless LAN (Local Area Network) -* WWAN - Telecommunication: Wireless WAN (Wide Area Network) -* WP - Cache policy: [**Write-Protected**](https://en.wikipedia.org/wiki/Cache_%28computing%29) -* WPT - Intel: Wildcat Point - PCH for Broadwell -* WO - Write-only -* WOL - [**Wake-on-LAN**](https://en.wikipedia.org/wiki/Wake-on-LAN) + - A cache policy where multiple write operations to the same cache + line are buffered and combined before being written to memory, which + can improve performance by reducing the number of memory bus + transactions. +* WCAM - **World-facing Camera** - A camera on a device that is not + intended to be used as a webcam, but instead to film scenes away from + the user. For clamshell devices, this may be on the keyboard panel for + devices that open 360 degrees, or on the outside of the cover. For + tablets, it's on the side away from the screen. +* WDT - [**WatchDog Timer**](https://en.wikipedia.org/wiki/Watchdog_timer) - A + hardware timer that automatically resets a computer system if it + becomes unresponsive or hangs, helping to recover from system + failures. +* WFC - **World Facing Camera**: see WCAM. +* WLAN - **Wireless Local Area Network** - A wireless computer network + that links two or more devices using wireless communication to form a + local area network within a limited area such as a home, school, + computer laboratory, or office building. +* WWAN - Telecommunication: **Wireless WAN** - A wireless wide area + network that provides wireless broadband access over a large + geographic area, typically using cellular networks like 4G or 5G. +* WP - Cache policy: [**Write-Protect**](https://en.wikipedia.org/wiki/Cache_%28computing%29) + - A cache policy that prevents modification of cached data, which can + be useful for protecting critical system data or read-only memory + regions. +* WPT - Intel: **Wildcat Point** - PCH for Broadwell. +* WO - **Write-only** - A register that can only be written to, not read + from. This is a common hardware register access mode where the + register can only be modified by writing to it, but its current value + cannot be read back. This is often used for registers that trigger + actions when written to, where reading the value back would not be + meaningful or could cause side effects. +* WOL - [**Wake-on-LAN**](https://en.wikipedia.org/wiki/Wake-on-LAN) - A + networking standard that allows a computer to be turned on remotely by + sending a special network packet (magic packet) to its network + interface. * WT - Cache Policy: [**Write Through**](https://en.wikipedia.org/wiki/Cache_%28computing%29) + - A cache policy where any write operation is immediately propagated + to both the cache and the underlying memory, ensuring data consistency + but potentially at the cost of performance since every write must + complete both operations. ## X -* x64 - Another name for [**x86-64**](https://en.wikipedia.org/wiki/X86-64) or AMD64. -* x86 - [**x86**](https://en.wikipedia.org/wiki/X86) Originally referred to any device compatible with the 8088/8086 - architectures, this now typically means compatibility with the 80386 - 32-bit instruction set (also referred to as IA-32) -* x86-64 - The 64-bit extension to the x86 architecture. Also known as - [**AMD64**](https://en.wikipedia.org/wiki/X86-64) as it was developed by AMD. Long-mode refers to when the - processor is running in the 64-bit mode. -* XBAR - AMD: Abbreviation for crossbar, their command packet switch - which determines what data goes where within the processor or SoC -* XHCI - USB: [**Extensible Host Controller Interface**](https://en.wikipedia.org/wiki/Extensible_Host_Controller_Inter… - USB Host controller - supporting 1.x, 2.0, and 3.x devices. +* x64 - Another name for [**x86-64**](https://en.wikipedia.org/wiki/X86-64) + or AMD64. This is the 64-bit extension to the x86 architecture, which + was originally developed by AMD and is now widely used in modern + processors from both AMD and Intel. It allows x86 processors to run in + 64-bit mode, providing access to larger amounts of memory and + additional CPU features. +* x86 - [**x86**](https://en.wikipedia.org/wiki/X86) Originally referred + to any device compatible with the 8088/8086 architectures, this now + typically means compatibility with the 80386 32-bit instruction set + (also referred to as IA-32). +* x86-64 - The 64-bit extension to the x86 architecture. Also known as + [**AMD64**](https://en.wikipedia.org/wiki/X86-64) as it was developed + by AMD. Long-mode refers to when the processor is running in the + 64-bit mode. +* XBAR - AMD: Abbreviation for **crossbar**, their command packet switch + which manages data flow between different components within their + processors and System-on-Chips (SoCs). +* XHCI - USB: [**Extensible Host Controller Interface**](https://en.wikipedia.org/wiki/Extensible_Host_Controller_Inter… + - USB Host controller supporting 1.x, 2.0, and 3.x devices. ## Y -* YCC - Color Space: [**YCbCr**](https://en.wikipedia.org/wiki/YCbCr) - A family of color spaces used in video - +* YCC - Color Space: [**YCbCr**](https://en.wikipedia.org/wiki/YCbCr) - + This is a color space format commonly used in video and digital + imaging where Y represents the luma (brightness) component, and Cb and + Cr represent the blue-difference and red-difference chroma components + respectively. ## Z -* ZIF - Zero Insertion Force +* ZIF - **Zero Insertion Force** - A type of chip socket that allows a + chip to be inserted and removed without applying any force, using a + lever or other mechanism to secure the chip in place. This is + particularly important for protecting delicate CPU pins and ensuring + safe installation/removal of processors in computer systems. ## References: -- To view, visit https://review.coreboot.org/c/coreboot/+/87184?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0d5c76f6cf6118635c0fae217d5d37d39c8403a9 Gerrit-Change-Number: 87184 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com>

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[XS] Change in coreboot[main]: soc/amd/glinda/psp_verstage/Makefile.mk: Fix incorrect syntax
by Felix Singer (Code Review) 05 Apr '25

05 Apr '25

Attention is currently required from: Ana Carolina Cabral, Martin L Roth, Maximilian Brune, Patrick Rudolph. Felix Singer has posted comments on this change by Maximilian Brune. ( https://review.coreboot.org/c/coreboot/+/86865?usp=email ) Change subject: soc/amd/glinda/psp_verstage/Makefile.mk: Fix incorrect syntax ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86865?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I78996cd35085c7649c4952d9b121957c8cedd84b Gerrit-Change-Number: 86865 Gerrit-PatchSet: 3 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Ana Carolina Cabral <ana.cpmelo95(a)gmail.com> Gerrit-Reviewer: Andy Ebrahiem <ahmet.ebrahiem(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Ana Carolina Cabral <ana.cpmelo95(a)gmail.com> Gerrit-Comment-Date: Sat, 05 Apr 2025 19:35:43 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: doc/contributing/gerrit_guidelines.md: Update reference to rebase.sh
by Felix Singer (Code Review) 05 Apr '25

05 Apr '25

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/87063?usp=email ) Change subject: doc/contributing/gerrit_guidelines.md: Update reference to rebase.sh ...................................................................... doc/contributing/gerrit_guidelines.md: Update reference to rebase.sh Since commit cd48d198367b ("Rename and move util/gitconfig/rebase.sh"), the script util/gitconfig/rebase.sh was moved to util/scripts/cross-repo-cherrypick. Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com> Change-Id: Ibecafd6cca9d312c48cfc8c38ff11e686ee184d4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/87063 Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> --- M Documentation/contributing/gerrit_guidelines.md 1 file changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Felix Singer: Looks good to me, approved Matt DeVillier: Looks good to me, approved diff --git a/Documentation/contributing/gerrit_guidelines.md b/Documentation/contributing/gerrit_guidelines.md index 3b92d08..04fb34f 100644 --- a/Documentation/contributing/gerrit_guidelines.md +++ b/Documentation/contributing/gerrit_guidelines.md @@ -348,8 +348,8 @@ * Tested-by: * Reviewed-by: -The script `util/gitconfig/rebase.sh` can be used to help automate this. -Other tags such as 'Commit-Queue' can simply be removed. +The script `util/scripts/cross-repo-cherrypick` can be used to help +automate this. Other tags such as 'Commit-Queue' can simply be removed. * Check if there's documentation that needs to be updated to remain current after your change. If there's no documentation for the part of coreboot -- To view, visit https://review.coreboot.org/c/coreboot/+/87063?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibecafd6cca9d312c48cfc8c38ff11e686ee184d4 Gerrit-Change-Number: 87063 Gerrit-PatchSet: 2 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: doc/contributing/gerrit_guidelines.md: Update reference to rebase.sh
by Felix Singer (Code Review) 05 Apr '25

05 Apr '25

Attention is currently required from: Angel Pons, David Hendricks, Martin L Roth, Maximilian Brune. Felix Singer has posted comments on this change by Maximilian Brune. ( https://review.coreboot.org/c/coreboot/+/87063?usp=email ) Change subject: doc/contributing/gerrit_guidelines.md: Update reference to rebase.sh ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/87063?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibecafd6cca9d312c48cfc8c38ff11e686ee184d4 Gerrit-Change-Number: 87063 Gerrit-PatchSet: 1 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Sat, 05 Apr 2025 19:34:29 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: doc/contributing/gerrit_guidelines.md: Update reference to rebase.sh
by Matt DeVillier (Code Review) 05 Apr '25

05 Apr '25

Attention is currently required from: Angel Pons, David Hendricks, Felix Singer, Martin L Roth, Maximilian Brune. Matt DeVillier has posted comments on this change by Maximilian Brune. ( https://review.coreboot.org/c/coreboot/+/87063?usp=email ) Change subject: doc/contributing/gerrit_guidelines.md: Update reference to rebase.sh ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/87063?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibecafd6cca9d312c48cfc8c38ff11e686ee184d4 Gerrit-Change-Number: 87063 Gerrit-PatchSet: 1 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Sat, 05 Apr 2025 18:50:15 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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