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Change subject: mb/google/nissa/var/telith: Support x32 memory configuration
......................................................................
Patch Set 2: Code-Review+1
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Change subject: mb/google/nissa/var/glassway: Support Memory Hynix H58G56CK8BX146
......................................................................
Patch Set 1: Code-Review+2
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Change subject: mb/google/nissa/var/glassway: Support Memory Hynix H58G56CK8BX146
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
Hi Googler, Kindly ping to review the CL if no concern. Thanks.
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Hello Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Qinghong Zeng, Subrata Banik, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/87212?usp=email
to look at the new patch set (#2).
The following approvals got outdated and were removed:
Code-Review+1 by Qinghong Zeng, Verified+1 by build bot (Jenkins)
Change subject: mb/google/nissa/var/telith: Support x32 memory configuration
......................................................................
mb/google/nissa/var/telith: Support x32 memory configuration
Use GPP_E19 level to determine whether x32 memory configuration is
supported.
BUG=b:405303038
TEST=emerge-nissa coreboot chromeos-bootimage
Change-Id: I969fea2aba858f76870c1a31ad4bd884ec9b6ff3
Signed-off-by: Kun Liu <liukun11(a)huaqin.corp-partner.google.com>
---
M src/mainboard/google/brya/Kconfig
M src/mainboard/google/brya/variants/telith/Makefile.mk
M src/mainboard/google/brya/variants/telith/gpio.c
A src/mainboard/google/brya/variants/telith/memory.c
4 files changed, 27 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/87212/2
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Change subject: mb/intel/ptlrvp: Introduce PTL RVP External and Internal EC Configurations
......................................................................
Patch Set 11:
(6 comments)
File src/mainboard/intel/ptlrvp/Kconfig:
https://review.coreboot.org/c/coreboot/+/86991/comment/ea3bcddb_1b549f03?us… :
PS11, Line 61: P_EXT_EC
Could it be `BOARD_INTEL_PTLRVP_GOOGLE_CHROMEEC` ?
File src/mainboard/intel/ptlrvp/Kconfig.name:
https://review.coreboot.org/c/coreboot/+/86991/comment/08c82bb7_8eda149d?us… :
PS11, Line 9: Ptlrvp External EC
Google Chrome EC
File src/mainboard/intel/ptlrvp/chromeos.c:
https://review.coreboot.org/c/coreboot/+/86991/comment/211a10e2_f52d2ee8?us… :
PS11, Line 27: int get_lid_switch(void)
In an effort to limit file differences with fatcat, I would suggest a dedicated C file like non_google.c to hold those, or something even more suitable. What do you think?
File src/mainboard/intel/ptlrvp/ec.c:
https://review.coreboot.org/c/coreboot/+/86991/comment/da8791a9_b4b3c7ed?us… :
PS11, Line 24: google_chromeec_events_init
Could we have defined as a stub in my suggested non_intel.c source file?
File src/mainboard/intel/ptlrvp/smihandler.c:
https://review.coreboot.org/c/coreboot/+/86991/comment/e9fcb0b9_1fffc2df?us… :
PS11, Line 10: void mainboard_smi_sleep(u8 slp_typ)
Could we have a non_chromeec_smihandler.c compiled instead ?
File src/mainboard/intel/ptlrvp/variants/baseboard/ptlrvp/ramstage.c:
https://review.coreboot.org/c/coreboot/+/86991/comment/01fcef90_83b130c5?us… :
PS11, Line 55: EC_GOOGLE_CHROMEEC
Couldn't we just skip compiling this file is not EC_GOOGLE_CHROMEEC ?
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Change subject: mb/intel/ptlrvp: Introduce PTL RVP External and Internal EC Configurations
......................................................................
Patch Set 11:
(1 comment)
File src/mainboard/intel/ptlrvp/chromeos.c:
https://review.coreboot.org/c/coreboot/+/86991/comment/f47a7b49_1a9264aa?us… :
PS5, Line 29: /* Lid always open */
> Jeremy I thought I fixed this already between patchset 6 and 7. Am I missing something? […]
This is indeed resolved, I mis-used gerrit WebUI. Discard it.
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Hello Bora Guvendik, Cliff Huang, Jamie Ryu, Jérémy Compostella, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Change subject: ec/intel: read board ID one time from EC per stage
......................................................................
ec/intel: read board ID one time from EC per stage
Using static variables to store the board ID optimizes boot time by
reading the ID once per stage and retaining it for subsequent use.
This approach reduces redundant hardware access, ensuring efficient
and consistent retrieval of the board ID throughout the boot process.
Static variables help streamline operations, minimize overhead, and
improve performance by maintaining the board ID in a fixed memory
location, enhancing the efficiency of each boot stage.
Rewrite function to avoid unnecessary ChromeEC wrapper function.
Signed-off-by: Wonkyu Kim <wonkyu.kim(a)intel.com>
Change-Id: I166ca1abdf7838f91319d0bcf11354055ed93eef
---
M src/ec/intel/board_id.c
1 file changed, 31 insertions(+), 16 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/87247/9
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Change subject: mb/intel/ptlrvp: Introduce PTL RVP External and Internal EC Configurations
......................................................................
Patch Set 11:
(1 comment)
File src/mainboard/intel/ptlrvp/chromeos.c:
https://review.coreboot.org/c/coreboot/+/86991/comment/d18edfc7_f1766ec4?us… :
PS5, Line 29: /* Lid always open */
> > `code indent should use tabs where possible` […]
Jeremy I thought I fixed this already between patchset 6 and 7. Am I missing something?
https://review.coreboot.org/c/coreboot/+/86991/6..7/src/mainboard/intel/ptl…
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Change subject: ec/intel: read board ID one time from EC per stage
......................................................................
Patch Set 8: Code-Review+1
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