coreboot-gerrit April 2025

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[S] Change in coreboot[main]: ec/intel: read board ID one time from EC per stage
by Jérémy Compostella (Code Review) 10 Apr '25

10 Apr '25

Attention is currently required from: Bora Guvendik, Cliff Huang, Jamie Ryu, Wonkyu Kim. Jérémy Compostella has posted comments on this change by Wonkyu Kim. ( https://review.coreboot.org/c/coreboot/+/87247?usp=email ) Change subject: ec/intel: read board ID one time from EC per stage ...................................................................... Patch Set 5: (1 comment) File src/ec/intel/board_id.c: https://review.coreboot.org/c/coreboot/+/87247/comment/ca7ded18_5715e95e?us… : PS5, Line 21: get_rvp_board_id > We could actually make this function much flatter and read-able in my opinion. […] We could actually make this function much flatter and read-able in my opinion. What do you think of the following? int get_rvp_board_id(void) { static int id = BOARD_ID_UNKNOWN; static bool initialized; static const char *ec_system; /* If already initialized, return the cached board ID. */ if (initialized) return id; /* Mark as initialized after the first read attempt. */ initialized = true; if (CONFIG(EC_GOOGLE_CHROMEEC)) { /* Chrome EC */ ec_system = "ChromeEC"; id = get_board_id_via_ext_ec(); } else if (send_ec_command(EC_FAB_ID_CMD) == 0) { /* Windows EC */ /* Windows EC */ ec_system = "WinEC"; id = recv_ec_data() << 8; id |= recv_ec_data(); } else { /* Error or unknown system */ return id; } /* Mask the board ID and log the information. */ id &= BOARD_ID_MASK; printk(BIOS_INFO, "[%s] board id: 0x%x\n", ec_system, id); return id; } -- To view, visit https://review.coreboot.org/c/coreboot/+/87247?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I166ca1abdf7838f91319d0bcf11354055ed93eef Gerrit-Change-Number: 87247 Gerrit-PatchSet: 5 Gerrit-Owner: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Comment-Date: Thu, 10 Apr 2025 17:43:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com>

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[S] Change in coreboot[main]: ec/intel: read board ID one time from EC per stage
by Jérémy Compostella (Code Review) 10 Apr '25

10 Apr '25

Attention is currently required from: Bora Guvendik, Cliff Huang, Jamie Ryu, Wonkyu Kim. Jérémy Compostella has posted comments on this change by Wonkyu Kim. ( https://review.coreboot.org/c/coreboot/+/87247?usp=email ) Change subject: ec/intel: read board ID one time from EC per stage ...................................................................... Patch Set 5: (1 comment) File src/ec/intel/board_id.c: https://review.coreboot.org/c/coreboot/+/87247/comment/55699662_ea8256bd?us… : PS5, Line 21: get_rvp_board_id We could actually make this function much flatter and read-able in my opinion. What do you think of the following? int get_rvp_board_id(void) { static int id = BOARD_ID_UNKNOWN; char *ec_system; /* Reading board ID after the first time reading. */ if (id != BOARD_ID_UNKNOWN) return id; /* Reading from EC failed. */ if (id == BOARD_ID_INIT) return BOARD_ID_UNKNOWN; /* Reading board ID for the first time. */ /* Chrome_EC */ if (CONFIG(EC_GOOGLE_CHROMEEC)) { ec_system = "ChromeEC"; id = get_board_id_via_ext_ec(); goto done; } /* Windows EC */ if (send_ec_command(EC_FAB_ID_CMD) != 0) { id = BOARD_ID_INIT; goto out; } ec_system = "WinEC"; id = recv_ec_data() << 8; id |= recv_ec_data(); done: id &= BOARD_ID_MASK; printk(BIOS_INFO, "[%s] board id: 0x%x\n", ec_system, id); out: return id; } -- To view, visit https://review.coreboot.org/c/coreboot/+/87247?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I166ca1abdf7838f91319d0bcf11354055ed93eef Gerrit-Change-Number: 87247 Gerrit-PatchSet: 5 Gerrit-Owner: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Comment-Date: Thu, 10 Apr 2025 17:34:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: ec/intel: read board ID one time from EC per stage
by Jérémy Compostella (Code Review) 10 Apr '25

10 Apr '25

Attention is currently required from: Bora Guvendik, Cliff Huang, Jamie Ryu, Wonkyu Kim. Jérémy Compostella has posted comments on this change by Wonkyu Kim. ( https://review.coreboot.org/c/coreboot/+/87247?usp=email ) Change subject: ec/intel: read board ID one time from EC per stage ...................................................................... Patch Set 5: (3 comments) File src/ec/intel/board_id.c: https://review.coreboot.org/c/coreboot/+/87247/comment/df15aca3_1f32ccd2?us… : PS5, Line 21: int get_rvp_board_id(void) I am realizing that it has little flow. The goal is to avoid communication with EC each time the function is called. But if `send_ec_command()` fails, you will end up calling over and over. I suggest setting `id` to `BOARD_ID_INIT` when `send_ec_command()` fails and adding the following at the beginning of the function: if (id == BOARD_ID_INIT) return BOARD_ID_UNKNOWN; https://review.coreboot.org/c/coreboot/+/87247/comment/813787ee_4df63601?us… : PS5, Line 25: Reading board id after first time reading nit: Reading board **ID** after **the** first time reading https://review.coreboot.org/c/coreboot/+/87247/comment/2002eaf7_ac97e318?us… : PS5, Line 29: Reading board id first time Reading board **ID for the** first time -- To view, visit https://review.coreboot.org/c/coreboot/+/87247?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I166ca1abdf7838f91319d0bcf11354055ed93eef Gerrit-Change-Number: 87247 Gerrit-PatchSet: 5 Gerrit-Owner: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Comment-Date: Thu, 10 Apr 2025 17:24:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: soc/intel/common/cse: Skip CSE state setting with LITE_SYNC_BY_PAYLOAD
by Subrata Banik (Code Review) 10 Apr '25

10 Apr '25

Attention is currently required from: Intel coreboot Reviewers. Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/87266?usp=email ) Change subject: soc/intel/common/cse: Skip CSE state setting with LITE_SYNC_BY_PAYLOAD ...................................................................... soc/intel/common/cse: Skip CSE state setting with LITE_SYNC_BY_PAYLOAD The CSE state setting logic in `cse_set_state` is not required when the `SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD` configuration option is enabled. This commit adds a conditional check to skip the state setting in such cases, potentially optimizing the CBFS travering time to locate `option/me_state` file. TEST=Able to build and boot google/fatcat. Change-Id: I43f5daab450989307d9b3529949e9f03cba4404d Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/soc/intel/common/block/cse/cse.c 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/87266/1 diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index 2e0f2db..68d0c21 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -1298,6 +1298,9 @@ static void cse_set_state(struct device *dev) { + if (CONFIG(SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD)) + return; + /* (CS)ME Disable Command */ struct me_disable_command { struct mkhi_hdr hdr; -- To view, visit https://review.coreboot.org/c/coreboot/+/87266?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I43f5daab450989307d9b3529949e9f03cba4404d Gerrit-Change-Number: 87266 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com>

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[XS] Change in coreboot[main]: soc/intel/pantherlake: Increase heap size for high-quality FW splash
by Subrata Banik (Code Review) 10 Apr '25

10 Apr '25

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/87265?usp=email ) Change subject: soc/intel/pantherlake: Increase heap size for high-quality FW splash ...................................................................... soc/intel/pantherlake: Increase heap size for high-quality FW splash This patch increases the default heap size from 1MB to 2MB (0x200000) to accommodate rendering high-quality firmware splash BMP logos. The previous 1MB heap size might be insufficient for larger, more detailed OEM logos, potentially leading to memory exhaustion during the splash screen display. TEST=Able to render an OEM logo size ~512KB w/o any corruption. Change-Id: I850247befc3904b6dc52e9872e8b99d53c2c9564 Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/soc/intel/pantherlake/Kconfig 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/87265/1 diff --git a/src/soc/intel/pantherlake/Kconfig b/src/soc/intel/pantherlake/Kconfig index 36417db..6e7cc3f 100644 --- a/src/soc/intel/pantherlake/Kconfig +++ b/src/soc/intel/pantherlake/Kconfig @@ -174,6 +174,10 @@ Refer to Platform FSP integration guide document to know the exact FSP requirement for Heap setup. +config HEAP_SIZE + hex + default 0x200000 + config CHIPSET_DEVICETREE string default "soc/intel/pantherlake/chipset.cb" -- To view, visit https://review.coreboot.org/c/coreboot/+/87265?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I850247befc3904b6dc52e9872e8b99d53c2c9564 Gerrit-Change-Number: 87265 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com>

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[XS] Change in coreboot[main]: mb/google/skywalker: Set up USB host in ramstage
by Yu-Ping Wu (Code Review) 10 Apr '25

10 Apr '25

Yu-Ping Wu has posted comments on this change by Vince Liu. ( https://review.coreboot.org/c/coreboot/+/87022?usp=email ) Change subject: mb/google/skywalker: Set up USB host in ramstage ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/87022?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3f77d116033338f979d14ce34ddf03e00d024e5d Gerrit-Change-Number: 87022 Gerrit-PatchSet: 3 Gerrit-Owner: Vince Liu <vince-wl.liu(a)mediatek.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Liu Liu <ot_liu.liu(a)mediatek.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Thu, 10 Apr 2025 16:36:30 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: soc/mediatek/mt8189: Reserve DRAM buffers for HW TX TRACKING
by Yu-Ping Wu (Code Review) 10 Apr '25

10 Apr '25

Yu-Ping Wu has posted comments on this change by Vince Liu. ( https://review.coreboot.org/c/coreboot/+/87039?usp=email ) Change subject: soc/mediatek/mt8189: Reserve DRAM buffers for HW TX TRACKING ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/87039?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2ecfe42dc9f1882163d03f50cf9b5ff8e98c2972 Gerrit-Change-Number: 87039 Gerrit-PatchSet: 3 Gerrit-Owner: Vince Liu <vince-wl.liu(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 10 Apr 2025 16:36:00 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: mb/google/skywalker: Add DRAM calibration init entry
by Yu-Ping Wu (Code Review) 10 Apr '25

10 Apr '25

Yu-Ping Wu has posted comments on this change by Vince Liu. ( https://review.coreboot.org/c/coreboot/+/87038?usp=email ) Change subject: mb/google/skywalker: Add DRAM calibration init entry ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/87038?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iabdcabefc77a262c548019e801daf5b269eaa97a Gerrit-Change-Number: 87038 Gerrit-PatchSet: 3 Gerrit-Owner: Vince Liu <vince-wl.liu(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 10 Apr 2025 16:35:12 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: soc/mediatek/common: Move DRAMC function declarations to common header
by Yu-Ping Wu (Code Review) 10 Apr '25

10 Apr '25

Yu-Ping Wu has posted comments on this change by Vince Liu. ( https://review.coreboot.org/c/coreboot/+/87209?usp=email ) Change subject: soc/mediatek/common: Move DRAMC function declarations to common header ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/87209?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iab24f07b4c02da22779ea1c76f3237c144d92b98 Gerrit-Change-Number: 87209 Gerrit-PatchSet: 2 Gerrit-Owner: Vince Liu <vince-wl.liu(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 10 Apr 2025 16:34:53 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: soc/mediatek/mt8196: Move TX TRACKING from MT8196 to common folder
by Yu-Ping Wu (Code Review) 10 Apr '25

10 Apr '25

Yu-Ping Wu has posted comments on this change by Vince Liu. ( https://review.coreboot.org/c/coreboot/+/87036?usp=email ) Change subject: soc/mediatek/mt8196: Move TX TRACKING from MT8196 to common folder ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/87036?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3fdd9d2f7ab1bbdcc097510556929da2134f7d95 Gerrit-Change-Number: 87036 Gerrit-PatchSet: 4 Gerrit-Owner: Vince Liu <vince-wl.liu(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 10 Apr 2025 16:33:51 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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