coreboot-gerrit April 2025

coreboot-gerrit@coreboot.org

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[M] Change in coreboot[main]: arch/x86: Unify GDT entries
by Patrick Rudolph (Code Review) 10 Apr '25

10 Apr '25

Attention is currently required from: Jérémy Compostella, Patrick Rudolph, Shuo Liu. Hello Jérémy Compostella, Shuo Liu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/87255?usp=email to look at the new patch set (#3). The following approvals got outdated and were removed: Verified-1 by build bot (Jenkins) Change subject: arch/x86: Unify GDT entries ...................................................................... arch/x86: Unify GDT entries Currently there are 3 GDTs used on x86: - preRAM (gdt_init.S) - SMM (smm_stub.S) - RAM (c_start.S) They have different layouts and thus different offset for the segments being using in assembly code. Stop using different GDT segments and make sure that for ROM (preRAM + SMM) and RAM (ramstage) the segments match. RAM will have additional entries, not found in pre RAM GDT, but the segments for protected mode and 64-bit mode now match in all stages. This allows to use the same defines in all stages. It also drops the need to know in which stage the code is compiled and it's no longer necessary to switch the code segment between stages. While on it fix the comments in the ramstage GDT and drop unused declarations from header files. Change-Id: I208496e6e4cc82833636f4f42503b44b0d702b9e Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/arch/x86/c_start.S D src/arch/x86/include/arch/ram_segs.h D src/arch/x86/include/arch/rom_segs.h M src/arch/x86/wakeup.S M src/cpu/x86/64bit/entry64.inc M src/cpu/x86/64bit/exit32.inc M src/cpu/x86/entry16.S M src/cpu/x86/entry32.S M src/cpu/x86/sipi_vector.S M src/cpu/x86/smm/smm_stub.S M src/device/oprom/realmode/x86_asm.S M src/include/cpu/x86/gdt.h M src/security/intel/stm/StmPlatformSmm.c M src/security/intel/txt/getsec_enteraccs.S 14 files changed, 81 insertions(+), 125 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/87255/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/87255?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I208496e6e4cc82833636f4f42503b44b0d702b9e Gerrit-Change-Number: 87255 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com>

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[L] Change in coreboot[main]: mb/asus/p8z77-v: Add support to reconfigure PCIe lanes
by Keith Hui (Code Review) 10 Apr '25

10 Apr '25

Attention is currently required from: Angel Pons, Bill XIE, Nicholas Chin. Keith Hui has posted comments on this change by Keith Hui. ( https://review.coreboot.org/c/coreboot/+/85413?usp=email ) Change subject: mb/asus/p8z77-v: Add support to reconfigure PCIe lanes ...................................................................... Patch Set 8: (1 comment) File src/mainboard/asus/p8x7x-series/variants/p8z77-v/pcielane.c: https://review.coreboot.org/c/coreboot/+/85413/comment/f4164214_0da8185b?us… : PS8, Line 131: gpio5 = 0x20; > > When PCIEPCS1 == 0, PCIEX1_2 remains not working with X_QSW_SEL2,3,4 being 111 and the following l […] Here is the big test. Can you test changing pciex16_3_bandwidth using nvramtool? It should now also attempt to change PCIEPCS1 as well. Be ready to recover. Changing it between Auto/x1, x2, x4 (so that the soft strap changes) should result in 1-2 power cycles, not more. If you clean the ME, these changes should only power cycle once. And if ME is intact, it should not report as disabled after strap is updated. Check that flash contents is preserved except the strap at offset 0x124 at all times. Check that no reflash is attempted going in and out of S3 and everything is preserved - GPIOs, straps, functionality. Check if PCIEX1_2 works with pciex16_3_bandwidth=x1, and SATA work with _bandwidth=Auto and always_use_sata6ge=Yes. Check console logs. -- To view, visit https://review.coreboot.org/c/coreboot/+/85413?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If41197a1f817a48c209d25fc1ae461ec97ccf16c Gerrit-Change-Number: 85413 Gerrit-PatchSet: 8 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Thu, 10 Apr 2025 11:39:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Bill XIE <persmule(a)hardenedlinux.org>

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[S] Change in coreboot[main]: mb/starlabs/starbook/tgl: Correct GPIO configs
by Sean Rhodes (Code Review) 10 Apr '25

10 Apr '25

Attention is currently required from: Matt DeVillier. Sean Rhodes has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/87261?usp=email ) Change subject: mb/starlabs/starbook/tgl: Correct GPIO configs ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/87261?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id41ea5d2f4f4321526d25b27411dad02fbde90b6 Gerrit-Change-Number: 87261 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Comment-Date: Thu, 10 Apr 2025 11:05:13 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

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[M] Change in coreboot[main]: mb/starlabs/starbook/tgl: Disconnect unused GPIOs
by Sean Rhodes (Code Review) 10 Apr '25

10 Apr '25

Attention is currently required from: Matt DeVillier. Sean Rhodes has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/87260?usp=email ) Change subject: mb/starlabs/starbook/tgl: Disconnect unused GPIOs ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/87260?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iaee9f3fc5639d5147f5bdf45fb5311a0121e2c78 Gerrit-Change-Number: 87260 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Comment-Date: Thu, 10 Apr 2025 11:05:11 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: mb/starlabs/starbook/tgl: Move webcam GPIO to it's own group
by Sean Rhodes (Code Review) 10 Apr '25

10 Apr '25

Attention is currently required from: Matt DeVillier. Sean Rhodes has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/87259?usp=email ) Change subject: mb/starlabs/starbook/tgl: Move webcam GPIO to it's own group ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/87259?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I88fa42782e4f262f6595bb6394f21f65bb3c1b21 Gerrit-Change-Number: 87259 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Comment-Date: Thu, 10 Apr 2025 11:05:09 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: mb/starlabs/starbook/tgl: Reconfigure PCH Strap GPIOs
by Sean Rhodes (Code Review) 10 Apr '25

10 Apr '25

Sean Rhodes has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/87258?usp=email ) Change subject: mb/starlabs/starbook/tgl: Reconfigure PCH Strap GPIOs ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/87258?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I944744f103aa2d1c347856a059d3dd6231b219c4 Gerrit-Change-Number: 87258 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Comment-Date: Thu, 10 Apr 2025 11:05:06 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

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[L] Change in coreboot[main]: mb/asus/p8z77-v: Add support to reconfigure PCIe lanes
by Bill XIE (Code Review) 10 Apr '25

10 Apr '25

Attention is currently required from: Angel Pons, Keith Hui, Nicholas Chin. Bill XIE has posted comments on this change by Keith Hui. ( https://review.coreboot.org/c/coreboot/+/85413?usp=email ) Change subject: mb/asus/p8z77-v: Add support to reconfigure PCIe lanes ...................................................................... Patch Set 8: (1 comment) File src/mainboard/asus/p8x7x-series/variants/p8z77-v/pcielane.c: https://review.coreboot.org/c/coreboot/+/85413/comment/afd027c4_30cd5555?us… : PS8, Line 131: gpio5 = 0x20; > When PCIEPCS1 == 0, PCIEX1_2 remains not working with X_QSW_SEL2,3,4 being 111 and the following log: Sorry, I forgot to write that this was just observed on patchset 8. -- To view, visit https://review.coreboot.org/c/coreboot/+/85413?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If41197a1f817a48c209d25fc1ae461ec97ccf16c Gerrit-Change-Number: 85413 Gerrit-PatchSet: 8 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Attention: Keith Hui <buurin(a)gmail.com> Gerrit-Comment-Date: Thu, 10 Apr 2025 10:40:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: soc/amd/common/cpu/noncar: Compute core info
by Naresh Solanki (Code Review) 10 Apr '25

10 Apr '25

Attention is currently required from: Angel Pons, Felix Held, Fred Reitberger, Jason Glenesk, Marvin Drees, Matt DeVillier. Naresh Solanki has posted comments on this change by Naresh Solanki. ( https://review.coreboot.org/c/coreboot/+/85640?usp=email ) Change subject: soc/amd/common/cpu/noncar: Compute core info ...................................................................... Patch Set 16: (1 comment) File src/soc/amd/common/block/include/amdblocks/cpu.h: https://review.coreboot.org/c/coreboot/+/85640/comment/92c1b14c_31999fdd?us… : PS15, Line 17: size_t l3_cache_size; > I would specify that somewhere, at least in the comment: […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/85640?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I46947e8ac62c903036a81642e03201e353c3dac6 Gerrit-Change-Number: 85640 Gerrit-PatchSet: 16 Gerrit-Owner: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marvin Drees <marvin.drees(a)9elements.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Marvin Drees <marvin.drees(a)9elements.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 10 Apr 2025 10:31:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Naresh Solanki <naresh.solanki(a)9elements.com>

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[S] Change in coreboot[main]: soc/amd/common/cpu/noncar: Compute core info
by Angel Pons (Code Review) 10 Apr '25

10 Apr '25

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Marvin Drees, Matt DeVillier, Naresh Solanki. Angel Pons has posted comments on this change by Naresh Solanki. ( https://review.coreboot.org/c/coreboot/+/85640?usp=email ) Change subject: soc/amd/common/cpu/noncar: Compute core info ...................................................................... Patch Set 15: (1 comment) File src/soc/amd/common/block/include/amdblocks/cpu.h: https://review.coreboot.org/c/coreboot/+/85640/comment/2f4f95d5_b47853cf?us… : PS15, Line 17: size_t l3_cache_size; > byte I would specify that somewhere, at least in the comment: ``` /* L3 Cache block unique ID & size (in bytes) */ ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/85640?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I46947e8ac62c903036a81642e03201e353c3dac6 Gerrit-Change-Number: 85640 Gerrit-PatchSet: 15 Gerrit-Owner: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marvin Drees <marvin.drees(a)9elements.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Marvin Drees <marvin.drees(a)9elements.com> Gerrit-Attention: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 10 Apr 2025 10:24:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Naresh Solanki <naresh.solanki(a)9elements.com>

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[S] Change in coreboot[main]: smmrelocate: Drop unused parameter
by Patrick Rudolph (Code Review) 10 Apr '25

10 Apr '25

Attention is currently required from: Christian Walter, Intel coreboot Reviewers, Johnny Lin, Jonathan Zhang, Shuo Liu, Tim Chu. Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/87257?usp=email ) Change subject: smmrelocate: Drop unused parameter ...................................................................... smmrelocate: Drop unused parameter The parameter CPU isn't used, thus drop it. Change-Id: Ie7f6179f0545f905463752e94243b438143d8234 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/cpu/intel/haswell/smmrelocate.c M src/soc/intel/common/block/cpu/smmrelocate.c M src/soc/intel/xeon_sp/smmrelocate.c 3 files changed, 12 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/87257/1 diff --git a/src/cpu/intel/haswell/smmrelocate.c b/src/cpu/intel/haswell/smmrelocate.c index 9e3554f..47946e8 100644 --- a/src/cpu/intel/haswell/smmrelocate.c +++ b/src/cpu/intel/haswell/smmrelocate.c @@ -17,9 +17,9 @@ #include <smp/node.h> #include "haswell.h" -static void update_save_state(int cpu, uintptr_t curr_smbase, - uintptr_t staggered_smbase, - struct smm_relocation_params *relo_params) +static void update_save_state(uintptr_t curr_smbase, + uintptr_t staggered_smbase, + struct smm_relocation_params *relo_params) { u32 smbase; u32 iedbase; @@ -120,7 +120,7 @@ } /* Make appropriate changes to the save state map. */ - update_save_state(cpu, curr_smbase, staggered_smbase, relo_params); + update_save_state(curr_smbase, staggered_smbase, relo_params); /* Write PRMRR and SMRR MSRs based on indicated support. */ mtrr_cap = rdmsr(MTRR_CAP_MSR); diff --git a/src/soc/intel/common/block/cpu/smmrelocate.c b/src/soc/intel/common/block/cpu/smmrelocate.c index 4df90fd..2069782 100644 --- a/src/soc/intel/common/block/cpu/smmrelocate.c +++ b/src/soc/intel/common/block/cpu/smmrelocate.c @@ -19,9 +19,9 @@ #include <string.h> #include <types.h> -static void update_save_state(int cpu, uintptr_t curr_smbase, - uintptr_t staggered_smbase, - struct smm_relocation_params *relo_params) +static void update_save_state(uintptr_t curr_smbase, + uintptr_t staggered_smbase, + struct smm_relocation_params *relo_params) { u32 smbase; u32 iedbase; @@ -136,7 +136,7 @@ } /* Make appropriate changes to the save state map. */ - update_save_state(cpu, curr_smbase, staggered_smbase, relo_params); + update_save_state(curr_smbase, staggered_smbase, relo_params); /* * The SMRR MSRs are core-level registers, so if two threads that share diff --git a/src/soc/intel/xeon_sp/smmrelocate.c b/src/soc/intel/xeon_sp/smmrelocate.c index c359237..c1079d3 100644 --- a/src/soc/intel/xeon_sp/smmrelocate.c +++ b/src/soc/intel/xeon_sp/smmrelocate.c @@ -84,9 +84,9 @@ *smm_save_state_size = sizeof(em64t101_smm_state_save_area_t); } -static void update_save_state(int cpu, uintptr_t curr_smbase, - uintptr_t staggered_smbase, - struct smm_relocation_params *relo_params) +static void update_save_state(uintptr_t curr_smbase, + uintptr_t staggered_smbase, + struct smm_relocation_params *relo_params) { u32 smbase; u32 iedbase; @@ -122,7 +122,7 @@ printk(BIOS_DEBUG, "%s : CPU %d\n", __func__, cpu); /* Make appropriate changes to the save state map. */ - update_save_state(cpu, curr_smbase, staggered_smbase, relo_params); + update_save_state(curr_smbase, staggered_smbase, relo_params); /* Write SMRR MSRs based on indicated support. */ mtrr_cap = rdmsr(MTRR_CAP_MSR); -- To view, visit https://review.coreboot.org/c/coreboot/+/87257?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie7f6179f0545f905463752e94243b438143d8234 Gerrit-Change-Number: 87257 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com>

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coreboot-gerrit April 2025