coreboot-gerrit April 2025

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[S] Change in coreboot[main]: soc/amd: add I3C controller base addresses and devicetree entries
by Felix Held (Code Review) 11 Apr '25

11 Apr '25

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/87276?usp=email ) Change subject: soc/amd: add I3C controller base addresses and devicetree entries ...................................................................... soc/amd: add I3C controller base addresses and devicetree entries Add the base addresses of the I3C controllers and the mmio devices to the devicetree for the SoCs that have I3C controllers. The following documentation was used to verify this: Mendocino: #57243 Rev 3.08 Rembrandt: #56558 Rev 3.09 (in Mendocino directory) Phoenix: #57019 Rev 3.09 Glinda: #57254 Rev 3.00 Faegan: #57928 Rev 1.51 (in Glinda directory) For Genoa, those entries already existed in both its iomap.h and its devicetree. Cezanne and Picasso don't have I3C controllers. Change-Id: I6e8073e6498266b909b6cc5f589353f2ed23a62f Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/glinda/chipset.cb M src/soc/amd/glinda/include/soc/iomap.h M src/soc/amd/mendocino/chipset_mendocino.cb M src/soc/amd/mendocino/chipset_rembrandt.cb M src/soc/amd/mendocino/include/soc/iomap.h M src/soc/amd/phoenix/chipset_fsp.cb M src/soc/amd/phoenix/chipset_opensil.cb M src/soc/amd/phoenix/include/soc/iomap.h 8 files changed, 35 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/87276/1 diff --git a/src/soc/amd/glinda/chipset.cb b/src/soc/amd/glinda/chipset.cb index a76be1a..321ecb7 100644 --- a/src/soc/amd/glinda/chipset.cb +++ b/src/soc/amd/glinda/chipset.cb @@ -148,4 +148,8 @@ device mmio 0xfedce000 alias uart_2 off ops amd_uart_mmio_ops end device mmio 0xfedcf000 alias uart_3 off ops amd_uart_mmio_ops end device mmio 0xfedd1000 alias uart_4 off ops amd_uart_mmio_ops end + device mmio 0xfedd2000 alias i3c_0 off end + device mmio 0xfedd3000 alias i3c_1 off end + device mmio 0xfedd4000 alias i3c_2 off end + device mmio 0xfedd6000 alias i3c_3 off end end diff --git a/src/soc/amd/glinda/include/soc/iomap.h b/src/soc/amd/glinda/include/soc/iomap.h index eb4b5810..bb68e17 100644 --- a/src/soc/amd/glinda/include/soc/iomap.h +++ b/src/soc/amd/glinda/include/soc/iomap.h @@ -33,6 +33,11 @@ #define APU_DMAC4_BASE 0xfedd0000 #define APU_UART4_BASE 0xfedd1000 +#define APU_I3C0_BASE 0xfedd2000 +#define APU_I3C1_BASE 0xfedd3000 +#define APU_I3C2_BASE 0xfedd4000 +#define APU_I3C3_BASE 0xfedd6000 + #endif /* ENV_X86 */ #define FLASH_BASE_ADDR ((0xffffffff - CONFIG_ROM_SIZE) + 1) diff --git a/src/soc/amd/mendocino/chipset_mendocino.cb b/src/soc/amd/mendocino/chipset_mendocino.cb index 3458cae..81a7932 100644 --- a/src/soc/amd/mendocino/chipset_mendocino.cb +++ b/src/soc/amd/mendocino/chipset_mendocino.cb @@ -93,4 +93,8 @@ device mmio 0xfedce000 alias uart_2 off ops amd_uart_mmio_ops end device mmio 0xfedcf000 alias uart_3 off ops amd_uart_mmio_ops end device mmio 0xfedd1000 alias uart_4 off ops amd_uart_mmio_ops end + device mmio 0xfedd2000 alias i3c_0 off end + device mmio 0xfedd3000 alias i3c_1 off end + device mmio 0xfedd4000 alias i3c_2 off end + device mmio 0xfedd6000 alias i3c_3 off end end diff --git a/src/soc/amd/mendocino/chipset_rembrandt.cb b/src/soc/amd/mendocino/chipset_rembrandt.cb index aef0a89..cb549cf 100644 --- a/src/soc/amd/mendocino/chipset_rembrandt.cb +++ b/src/soc/amd/mendocino/chipset_rembrandt.cb @@ -96,4 +96,8 @@ device mmio 0xfedce000 alias uart_2 off ops amd_uart_mmio_ops end device mmio 0xfedcf000 alias uart_3 off ops amd_uart_mmio_ops end device mmio 0xfedd1000 alias uart_4 off ops amd_uart_mmio_ops end + device mmio 0xfedd2000 alias i3c_0 off end + device mmio 0xfedd3000 alias i3c_1 off end + device mmio 0xfedd4000 alias i3c_2 off end + device mmio 0xfedd6000 alias i3c_3 off end end diff --git a/src/soc/amd/mendocino/include/soc/iomap.h b/src/soc/amd/mendocino/include/soc/iomap.h index d70773d..bffdb5f 100644 --- a/src/soc/amd/mendocino/include/soc/iomap.h +++ b/src/soc/amd/mendocino/include/soc/iomap.h @@ -33,6 +33,11 @@ #define APU_DMAC4_BASE 0xfedd0000 #define APU_UART4_BASE 0xfedd1000 +#define APU_I3C0_BASE 0xfedd2000 +#define APU_I3C1_BASE 0xfedd3000 +#define APU_I3C2_BASE 0xfedd4000 +#define APU_I3C3_BASE 0xfedd6000 + #endif /* ENV_X86 */ #define FLASH_BASE_ADDR ((0xffffffff - CONFIG_ROM_SIZE) + 1) diff --git a/src/soc/amd/phoenix/chipset_fsp.cb b/src/soc/amd/phoenix/chipset_fsp.cb index d461ac5..de05cbf 100644 --- a/src/soc/amd/phoenix/chipset_fsp.cb +++ b/src/soc/amd/phoenix/chipset_fsp.cb @@ -145,4 +145,8 @@ device mmio 0xfedce000 alias uart_2 off ops amd_uart_mmio_ops end device mmio 0xfedcf000 alias uart_3 off ops amd_uart_mmio_ops end device mmio 0xfedd1000 alias uart_4 off ops amd_uart_mmio_ops end + device mmio 0xfedd2000 alias i3c_0 off end + device mmio 0xfedd3000 alias i3c_1 off end + device mmio 0xfedd4000 alias i3c_2 off end + device mmio 0xfedd6000 alias i3c_3 off end end diff --git a/src/soc/amd/phoenix/chipset_opensil.cb b/src/soc/amd/phoenix/chipset_opensil.cb index fd1563b..c2ea6c0 100644 --- a/src/soc/amd/phoenix/chipset_opensil.cb +++ b/src/soc/amd/phoenix/chipset_opensil.cb @@ -165,4 +165,8 @@ device mmio 0xfedce000 alias uart_2 off ops amd_uart_mmio_ops end device mmio 0xfedcf000 alias uart_3 off ops amd_uart_mmio_ops end device mmio 0xfedd1000 alias uart_4 off ops amd_uart_mmio_ops end + device mmio 0xfedd2000 alias i3c_0 off end + device mmio 0xfedd3000 alias i3c_1 off end + device mmio 0xfedd4000 alias i3c_2 off end + device mmio 0xfedd6000 alias i3c_3 off end end diff --git a/src/soc/amd/phoenix/include/soc/iomap.h b/src/soc/amd/phoenix/include/soc/iomap.h index 0b93057..63d8b08 100644 --- a/src/soc/amd/phoenix/include/soc/iomap.h +++ b/src/soc/amd/phoenix/include/soc/iomap.h @@ -33,6 +33,11 @@ #define APU_DMAC4_BASE 0xfedd0000 #define APU_UART4_BASE 0xfedd1000 +#define APU_I3C0_BASE 0xfedd2000 +#define APU_I3C1_BASE 0xfedd3000 +#define APU_I3C2_BASE 0xfedd4000 +#define APU_I3C3_BASE 0xfedd6000 + #endif /* ENV_X86 */ #define FLASH_BASE_ADDR ((0xffffffff - CONFIG_ROM_SIZE) + 1) -- To view, visit https://review.coreboot.org/c/coreboot/+/87276?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6e8073e6498266b909b6cc5f589353f2ed23a62f Gerrit-Change-Number: 87276 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de>

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[XS] Change in coreboot[main]: mb/google/nissa/var/guren: Add SPD IDs for new memory part
by Brian Hsu (Code Review) 11 Apr '25

11 Apr '25

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik. Brian Hsu has posted comments on this change by Brian Hsu. ( https://review.coreboot.org/c/coreboot/+/87275?usp=email ) Change subject: mb/google/nissa/var/guren: Add SPD IDs for new memory part ...................................................................... Patch Set 2: Code-Review+1 (1 comment) Patchset: PS2: Hi all, the memory part was verified by our EE team, please help review if no concern. Thanks a lot. -- To view, visit https://review.coreboot.org/c/coreboot/+/87275?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4616b44a164391d7a14cc97efb059e731d35c308 Gerrit-Change-Number: 87275 Gerrit-PatchSet: 2 Gerrit-Owner: Brian Hsu <brian_hsu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Brian Hsu <brian_hsu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-CC: David Li <david_li(a)pegatron.corp-partner.google.com> Gerrit-CC: Samuel Chen <samuel_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Wayne3 Wang <wayne3_wang(a)pegatron.corp-partner.google.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Fri, 11 Apr 2025 12:18:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: mb/google/nissa/var/guren: Add SPD IDs for new memory part
by Brian Hsu (Code Review) 11 Apr '25

11 Apr '25

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik. Hello Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/87275?usp=email to look at the new patch set (#2). Change subject: mb/google/nissa/var/guren: Add SPD IDs for new memory part ...................................................................... mb/google/nissa/var/guren: Add SPD IDs for new memory part Support Memory of H58G56CK8BX146 in mem_parts_used list, and generate SPD ID for these part. DRAM Part Name Vendor Model Spec ID to assign H58G56CK8BX146 SK hynix LPDDR5X 8533 32Gb 6 (0110) BUG=b:409971450 BRANCH=firmware-nissa-15217.B TEST=Run command "go run ./util/spd_tools/src/part_id_gen/\ part_id_gen.go ADL lp5 \ src/mainboard/google/brya/variants/guren/memory/ \ src/mainboard/google/brya/variants/guren/memory/\ mem_parts_used.txt" Change-Id: I4616b44a164391d7a14cc97efb059e731d35c308 Signed-off-by: Brian Hsu <Brian_Hsu(a)pegatron.corp-partner.google.com> --- M src/mainboard/google/brya/variants/guren/memory/Makefile.mk M src/mainboard/google/brya/variants/guren/memory/dram_id.generated.txt M src/mainboard/google/brya/variants/guren/memory/mem_parts_used.txt 3 files changed, 5 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/87275/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/87275?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4616b44a164391d7a14cc97efb059e731d35c308 Gerrit-Change-Number: 87275 Gerrit-PatchSet: 2 Gerrit-Owner: Brian Hsu <brian_hsu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org>

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[XS] Change in coreboot[main]: mb/google/nissa/var/guren: Add SPD IDs for new memory parts
by Brian Hsu (Code Review) 11 Apr '25

11 Apr '25

Brian Hsu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/87275?usp=email ) Change subject: mb/google/nissa/var/guren: Add SPD IDs for new memory parts ...................................................................... mb/google/nissa/var/guren: Add SPD IDs for new memory parts Support Memory of H58G56CK8BX146 in mem_parts_used list, and generate SPD ID for these part. DRAM Part Name Vendor Model Spec ID to assign H58G56CK8BX146 SK hynix LPDDR5X 8533 32Gb 6 (0110) BUG=b:409971450 BRANCH=firmware-nissa-15217.B TEST=Run command "go run ./util/spd_tools/src/part_id_gen/\ part_id_gen.go ADL lp5 \ src/mainboard/google/brya/variants/guren/memory/ \ src/mainboard/google/brya/variants/guren/memory/\ mem_parts_used.txt" Change-Id: I4616b44a164391d7a14cc97efb059e731d35c308 Signed-off-by: Brian Hsu <Brian_Hsu(a)pegatron.corp-partner.google.com> --- M src/mainboard/google/brya/variants/guren/memory/Makefile.mk M src/mainboard/google/brya/variants/guren/memory/dram_id.generated.txt M src/mainboard/google/brya/variants/guren/memory/mem_parts_used.txt 3 files changed, 5 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/87275/1 diff --git a/src/mainboard/google/brya/variants/guren/memory/Makefile.mk b/src/mainboard/google/brya/variants/guren/memory/Makefile.mk index 943dfba..87fd132 100644 --- a/src/mainboard/google/brya/variants/guren/memory/Makefile.mk +++ b/src/mainboard/google/brya/variants/guren/memory/Makefile.mk @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-or-later # This is an auto-generated file. Do not edit!! # Generated by: -# /tmp/go-build776947141/b001/exe/part_id_gen ADL lp5 src/mainboard/google/brya/variants/guren/memory/ src/mainboard/google/brya/variants/guren/memory/mem_parts_used.txt +# /tmp/go-build3837031112/b001/exe/part_id_gen ADL lp5 src/mainboard/google/brya/variants/guren/memory/ src/mainboard/google/brya/variants/guren/memory/mem_parts_used.txt SPD_SOURCES = SPD_SOURCES += spd/lp5/set-0/spd-7.hex # ID = 0(0b0000) Parts = K3KL8L80CM-MGCT @@ -10,3 +10,4 @@ SPD_SOURCES += spd/lp5/set-0/spd-1.hex # ID = 3(0b0011) Parts = H9JCNNNBK3MLYR-N6E SPD_SOURCES += spd/lp5/set-0/spd-6.hex # ID = 4(0b0100) Parts = H58G66AK6BX070 SPD_SOURCES += spd/lp5/set-0/spd-8.hex # ID = 5(0b0101) Parts = K3KL9L90CM-MGCT +SPD_SOURCES += spd/lp5/set-0/spd-11.hex # ID = 6(0b0110) Parts = H58G56CK8BX146 diff --git a/src/mainboard/google/brya/variants/guren/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/guren/memory/dram_id.generated.txt index 62cd085..cb4da42 100644 --- a/src/mainboard/google/brya/variants/guren/memory/dram_id.generated.txt +++ b/src/mainboard/google/brya/variants/guren/memory/dram_id.generated.txt @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-or-later # This is an auto-generated file. Do not edit!! # Generated by: -# /tmp/go-build776947141/b001/exe/part_id_gen ADL lp5 src/mainboard/google/brya/variants/guren/memory/ src/mainboard/google/brya/variants/guren/memory/mem_parts_used.txt +# /tmp/go-build3837031112/b001/exe/part_id_gen ADL lp5 src/mainboard/google/brya/variants/guren/memory/ src/mainboard/google/brya/variants/guren/memory/mem_parts_used.txt DRAM Part Name ID to assign K3KL8L80CM-MGCT 0 (0000) @@ -11,3 +11,4 @@ H58G66AK6BX070 4 (0100) K3KL9L90CM-MGCT 5 (0101) K3LKBKB0BM-MGCP 2 (0010) +H58G56CK8BX146 6 (0110) diff --git a/src/mainboard/google/brya/variants/guren/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/guren/memory/mem_parts_used.txt index a7e8120..796d10a 100644 --- a/src/mainboard/google/brya/variants/guren/memory/mem_parts_used.txt +++ b/src/mainboard/google/brya/variants/guren/memory/mem_parts_used.txt @@ -16,3 +16,4 @@ H58G66AK6BX070 K3KL9L90CM-MGCT K3LKBKB0BM-MGCP +H58G56CK8BX146 -- To view, visit https://review.coreboot.org/c/coreboot/+/87275?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4616b44a164391d7a14cc97efb059e731d35c308 Gerrit-Change-Number: 87275 Gerrit-PatchSet: 1 Gerrit-Owner: Brian Hsu <brian_hsu(a)pegatron.corp-partner.google.com>

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[XS] Change in coreboot[main]: soc/qualcomm/common: Avoid hardcoding SPI bus from QUP range
by Subrata Banik (Code Review) 11 Apr '25

11 Apr '25

Attention is currently required from: Julius Werner, Kapil Porwal. Subrata Banik has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/87270?usp=email ) Change subject: soc/qualcomm/common: Avoid hardcoding SPI bus from QUP range ...................................................................... Patch Set 1: (1 comment) File src/soc/qualcomm/common/spi.c: https://review.coreboot.org/c/coreboot/+/87270/comment/c66ad587_dcf4ee47?us… : PS1, Line 32: CONFIG_BOOT_DEVICE_SPI_FLASH_BUS > Can we use `QUPV3_SE_MAX` here? Let's wait to hear from Julius? -- To view, visit https://review.coreboot.org/c/coreboot/+/87270?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7e9ec555a6d72d93bc23285e48eab52030978e1a Gerrit-Change-Number: 87270 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Fri, 11 Apr 2025 10:49:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Kapil Porwal <kapilporwal(a)google.com>

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[XS] Change in coreboot[main]: Update arm-trusted-firmware submodule to upstream master
by Yu-Ping Wu (Code Review) 11 Apr '25

11 Apr '25

Attention is currently required from: Yidi Lin. Yu-Ping Wu has posted comments on this change by Yidi Lin. ( https://review.coreboot.org/c/coreboot/+/87269?usp=email ) Change subject: Update arm-trusted-firmware submodule to upstream master ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/87269?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I22ec128c99e84fd80fbc7de06f2791c627ae790a Gerrit-Change-Number: 87269 Gerrit-PatchSet: 1 Gerrit-Owner: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Fri, 11 Apr 2025 10:02:26 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: util/scripts/update_submodules: Fix "branch: unbound variable" error
by Yu-Ping Wu (Code Review) 11 Apr '25

11 Apr '25

Attention is currently required from: Felix Singer, Yidi Lin. Yu-Ping Wu has posted comments on this change by Yidi Lin. ( https://review.coreboot.org/c/coreboot/+/87268?usp=email ) Change subject: util/scripts/update_submodules: Fix "branch: unbound variable" error ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/87268?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia528379b8721e6d419984bab28de7cf427e42423 Gerrit-Change-Number: 87268 Gerrit-PatchSet: 1 Gerrit-Owner: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Fri, 11 Apr 2025 10:02:17 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: mb/google/rauru: Add FORCE_MAX_SWING quirk for ATNA40HQ01-0
by Yu-Ping Wu (Code Review) 11 Apr '25

11 Apr '25

Attention is currently required from: Hung-Te Lin, Yidi Lin. Yu-Ping Wu has posted comments on this change by Yidi Lin. ( https://review.coreboot.org/c/coreboot/+/87028?usp=email ) Change subject: mb/google/rauru: Add FORCE_MAX_SWING quirk for ATNA40HQ01-0 ...................................................................... Patch Set 2: (1 comment) File src/mainboard/google/rauru/devicetree.cb: https://review.coreboot.org/c/coreboot/+/87028/comment/a00b02a7_26beabc1?us… : PS2, Line 4: field OLED_WQXGA_PLUS 1 1 In ChromeOS config, this is defined for navi only. I think we'll need variants/navi/overridetree.cb. -- To view, visit https://review.coreboot.org/c/coreboot/+/87028?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4797ef8fe2257a9b578a969794d624d6e0f97d07 Gerrit-Change-Number: 87028 Gerrit-PatchSet: 2 Gerrit-Owner: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Bincai Liu <bincai.liu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Fri, 11 Apr 2025 10:01:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: arch/x86/c_start: Drop switching the code selector
by Shuo Liu (Code Review) 11 Apr '25

11 Apr '25

Attention is currently required from: Jérémy Compostella, Patrick Rudolph. Shuo Liu has posted comments on this change by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/87256?usp=email ) Change subject: arch/x86/c_start: Drop switching the code selector ...................................................................... Patch Set 4: (1 comment) Patchset: PS4: Maybe keeping the switches helps the code robustness. Since there is still lgdt, so the following switching seems natural. -- To view, visit https://review.coreboot.org/c/coreboot/+/87256?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I67200fe691ddd9f2fd8de5b4464f6e48fd31e75b Gerrit-Change-Number: 87256 Gerrit-PatchSet: 4 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Comment-Date: Fri, 11 Apr 2025 10:01:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[M] Change in coreboot[main]: arch/x86: Unify GDT entries
by Shuo Liu (Code Review) 11 Apr '25

11 Apr '25

Attention is currently required from: Jérémy Compostella, Patrick Rudolph. Shuo Liu has posted comments on this change by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/87255?usp=email ) Change subject: arch/x86: Unify GDT entries ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: It would be beneficial to merge all definitions into one. However, maybe the gdt tables implementation are also needs to be merged, e.g. smm_relocate_gdt. -- To view, visit https://review.coreboot.org/c/coreboot/+/87255?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I208496e6e4cc82833636f4f42503b44b0d702b9e Gerrit-Change-Number: 87255 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Comment-Date: Fri, 11 Apr 2025 09:58:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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