coreboot-gerrit April 2025

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[M] Change in coreboot[main]: soc/intel/common: Add Wildcat Lake PCIE and CPU device IDs
by Appukuttan V K (Code Review) 11 Apr '25

11 Apr '25

Attention is currently required from: Sowmya Aralguppe, Usha P, Varun Upadhyay. Appukuttan V K has posted comments on this change by Appukuttan V K. ( https://review.coreboot.org/c/coreboot/+/87263?usp=email ) Change subject: soc/intel/common: Add Wildcat Lake PCIE and CPU device IDs ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/87263?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0f8ea74423fa9c09c2a88200d8154408c7460e3e Gerrit-Change-Number: 87263 Gerrit-PatchSet: 12 Gerrit-Owner: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-Reviewer: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Varun Upadhyay <varun.upadhyay(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-Attention: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Attention: Varun Upadhyay <varun.upadhyay(a)intel.com> Gerrit-Attention: Usha P <usha.p(a)intel.com> Gerrit-Comment-Date: Fri, 11 Apr 2025 16:06:59 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

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[M] Change in coreboot[main]: soc/intel: Add Wildcat Lake CPU and PCIE device IDs
by Appukuttan V K (Code Review) 11 Apr '25

11 Apr '25

Attention is currently required from: Sowmya Aralguppe, Usha P, Varun Upadhyay. Appukuttan V K has posted comments on this change by Appukuttan V K. ( https://review.coreboot.org/c/coreboot/+/87262?usp=email ) Change subject: soc/intel: Add Wildcat Lake CPU and PCIE device IDs ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/87262?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4bc7a8ea898ee30d565a95b9f85d6f19886bcffb Gerrit-Change-Number: 87262 Gerrit-PatchSet: 7 Gerrit-Owner: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-Reviewer: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Varun Upadhyay <varun.upadhyay(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-Attention: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Attention: Varun Upadhyay <varun.upadhyay(a)intel.com> Gerrit-Attention: Usha P <usha.p(a)intel.com> Gerrit-Comment-Date: Fri, 11 Apr 2025 16:06:52 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

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[M] Change in coreboot[main]: src/soc/amd/* : Move CPU init in common code
by Felix Held (Code Review) 11 Apr '25

11 Apr '25

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/87214?usp=email ) Change subject: src/soc/amd/* : Move CPU init in common code ...................................................................... src/soc/amd/* : Move CPU init in common code AMD SoC from family 17h share common cpu init code. Move those to common/block/cpu/noncar/cpu.c TEST=Build for glinda SoC & check for boot. Change-Id: If53455f359302f368f7c979defa2c1088c5c2f16 Signed-off-by: Naresh Solanki <naresh.solanki(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/87214 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/cezanne/cpu.c M src/soc/amd/common/block/cpu/noncar/cpu.c M src/soc/amd/common/block/include/amdblocks/cpu.h M src/soc/amd/genoa_poc/cpu.c M src/soc/amd/glinda/cpu.c M src/soc/amd/mendocino/cpu.c M src/soc/amd/phoenix/cpu.c M src/soc/amd/picasso/cpu.c 8 files changed, 20 insertions(+), 66 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved Angel Pons: Looks good to me, approved diff --git a/src/soc/amd/cezanne/cpu.c b/src/soc/amd/cezanne/cpu.c index 4f39aef..52d2e2b 100644 --- a/src/soc/amd/cezanne/cpu.c +++ b/src/soc/amd/cezanne/cpu.c @@ -1,8 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <amdblocks/cpu.h> -#include <amdblocks/mca.h> -#include <cpu/amd/microcode.h> #include <cpu/cpu.h> #include <device/device.h> #include <soc/cpu.h> @@ -10,16 +8,8 @@ _Static_assert(CONFIG_MAX_CPUS == 16, "Do not override MAX_CPUS. To reduce the number of " "available cores, use the downcore_mode and disable_smt devicetree settings instead."); -static void zen_2_3_init(struct device *dev) -{ - check_mca(); - set_cstate_io_addr(); - - amd_apply_microcode_patch(); -} - static struct device_operations cpu_dev_ops = { - .init = zen_2_3_init, + .init = amd_cpu_init, }; static struct cpu_device_id cpu_table[] = { diff --git a/src/soc/amd/common/block/cpu/noncar/cpu.c b/src/soc/amd/common/block/cpu/noncar/cpu.c index e67d669..c97e2f4 100644 --- a/src/soc/amd/common/block/cpu/noncar/cpu.c +++ b/src/soc/amd/common/block/cpu/noncar/cpu.c @@ -1,10 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <amdblocks/cpu.h> +#include <amdblocks/mca.h> #include <arch/cpuid.h> #include <cpu/cpu.h> #include <cpu/x86/msr.h> #include <cpu/amd/cpuid.h> +#include <cpu/amd/microcode.h> #include <cpu/amd/msr.h> #include <cpu/amd/mtrr.h> #include <smbios.h> @@ -100,3 +102,14 @@ return (cpuid_ebx(CPUID_EBX_MEM_ENCRYPT) & CPUID_EBX_MEM_ENCRYPT_ADDR_BITS_MASK) >> CPUID_EBX_MEM_ENCRYPT_ADDR_BITS_SHIFT; } + +void amd_cpu_init(struct device *dev) +{ + if (CONFIG(SOC_AMD_COMMON_BLOCK_MCA_COMMON)) + check_mca(); + + set_cstate_io_addr(); + + if (CONFIG(SOC_AMD_COMMON_BLOCK_UCODE)) + amd_apply_microcode_patch(); +} diff --git a/src/soc/amd/common/block/include/amdblocks/cpu.h b/src/soc/amd/common/block/include/amdblocks/cpu.h index 4aa225b..ce0b2da 100644 --- a/src/soc/amd/common/block/include/amdblocks/cpu.h +++ b/src/soc/amd/common/block/include/amdblocks/cpu.h @@ -22,5 +22,6 @@ uint32_t get_pstate_core_freq(union pstate_msr pstate_reg); uint32_t get_pstate_core_uvolts(union pstate_msr pstate_reg); const acpi_cstate_t *get_cstate_config_data(size_t *size); +void amd_cpu_init(struct device *dev); #endif /* AMD_BLOCK_CPU_H */ diff --git a/src/soc/amd/genoa_poc/cpu.c b/src/soc/amd/genoa_poc/cpu.c index 241bec2..a91720a 100644 --- a/src/soc/amd/genoa_poc/cpu.c +++ b/src/soc/amd/genoa_poc/cpu.c @@ -1,22 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <amdblocks/cpu.h> -#include <amdblocks/mca.h> -#include <cpu/amd/microcode.h> #include <cpu/cpu.h> #include <device/device.h> #include <soc/cpu.h> -static void model_19_init(struct device *dev) -{ - check_mca(); - set_cstate_io_addr(); - - amd_apply_microcode_patch(); -} - static struct device_operations cpu_dev_ops = { - .init = model_19_init, + .init = amd_cpu_init, }; static struct cpu_device_id cpu_table[] = { diff --git a/src/soc/amd/glinda/cpu.c b/src/soc/amd/glinda/cpu.c index a716127..2dcc3c5 100644 --- a/src/soc/amd/glinda/cpu.c +++ b/src/soc/amd/glinda/cpu.c @@ -3,8 +3,6 @@ /* TODO: Update for Glinda */ #include <amdblocks/cpu.h> -#include <amdblocks/mca.h> -#include <cpu/amd/microcode.h> #include <cpu/cpu.h> #include <device/device.h> #include <soc/cpu.h> @@ -12,16 +10,8 @@ _Static_assert(CONFIG_MAX_CPUS == 24, "Do not override MAX_CPUS. To reduce the number of " "available cores, use the downcore_mode and disable_smt devicetree settings instead."); -static void zen_2_3_init(struct device *dev) -{ - check_mca(); - set_cstate_io_addr(); - - amd_apply_microcode_patch(); -} - static struct device_operations cpu_dev_ops = { - .init = zen_2_3_init, + .init = amd_cpu_init, }; static struct cpu_device_id cpu_table[] = { diff --git a/src/soc/amd/mendocino/cpu.c b/src/soc/amd/mendocino/cpu.c index 842b04f..e2e1f53 100644 --- a/src/soc/amd/mendocino/cpu.c +++ b/src/soc/amd/mendocino/cpu.c @@ -1,8 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <amdblocks/cpu.h> -#include <amdblocks/mca.h> -#include <cpu/amd/microcode.h> #include <cpu/cpu.h> #include <device/device.h> #include <soc/cpu.h> @@ -10,16 +8,8 @@ _Static_assert(CONFIG_MAX_CPUS == 8, "Do not override MAX_CPUS. To reduce the number of " "available cores, use the downcore_mode and disable_smt devicetree settings instead."); -static void zen_2_3_init(struct device *dev) -{ - check_mca(); - set_cstate_io_addr(); - - amd_apply_microcode_patch(); -} - static struct device_operations cpu_dev_ops = { - .init = zen_2_3_init, + .init = amd_cpu_init, }; static struct cpu_device_id cpu_table[] = { diff --git a/src/soc/amd/phoenix/cpu.c b/src/soc/amd/phoenix/cpu.c index 05dac9a..5d15b1d 100644 --- a/src/soc/amd/phoenix/cpu.c +++ b/src/soc/amd/phoenix/cpu.c @@ -3,8 +3,6 @@ /* TODO: Update for Phoenix */ #include <amdblocks/cpu.h> -#include <amdblocks/mca.h> -#include <cpu/amd/microcode.h> #include <cpu/cpu.h> #include <device/device.h> #include <soc/cpu.h> @@ -12,16 +10,8 @@ _Static_assert(CONFIG_MAX_CPUS == 16, "Do not override MAX_CPUS. To reduce the number of " "available cores, use the downcore_mode and disable_smt devicetree settings instead."); -static void zen_2_3_init(struct device *dev) -{ - check_mca(); - set_cstate_io_addr(); - - amd_apply_microcode_patch(); -} - static struct device_operations cpu_dev_ops = { - .init = zen_2_3_init, + .init = amd_cpu_init, }; static struct cpu_device_id cpu_table[] = { diff --git a/src/soc/amd/picasso/cpu.c b/src/soc/amd/picasso/cpu.c index 4f84629..702f626 100644 --- a/src/soc/amd/picasso/cpu.c +++ b/src/soc/amd/picasso/cpu.c @@ -1,8 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <amdblocks/cpu.h> -#include <amdblocks/mca.h> -#include <cpu/amd/microcode.h> #include <cpu/cpu.h> #include <device/device.h> #include <soc/cpu.h> @@ -10,16 +8,8 @@ _Static_assert(CONFIG_MAX_CPUS == 8, "Do not override MAX_CPUS. To reduce the number of " "available cores, use the downcore_mode and disable_smt devicetree settings instead."); -static void model_17_init(struct device *dev) -{ - check_mca(); - set_cstate_io_addr(); - - amd_apply_microcode_patch(); -} - static struct device_operations cpu_dev_ops = { - .init = model_17_init, + .init = amd_cpu_init, }; static struct cpu_device_id cpu_table[] = { -- To view, visit https://review.coreboot.org/c/coreboot/+/87214?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If53455f359302f368f7c979defa2c1088c5c2f16 Gerrit-Change-Number: 87214 Gerrit-PatchSet: 4 Gerrit-Owner: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in coreboot[main]: src/soc/amd/* : Move CPU init in common code
by Felix Held (Code Review) 11 Apr '25

11 Apr '25

Attention is currently required from: Martin L Roth, Naresh Solanki. Felix Held has posted comments on this change by Naresh Solanki. ( https://review.coreboot.org/c/coreboot/+/87214?usp=email ) Change subject: src/soc/amd/* : Move CPU init in common code ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/87214?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If53455f359302f368f7c979defa2c1088c5c2f16 Gerrit-Change-Number: 87214 Gerrit-PatchSet: 3 Gerrit-Owner: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Comment-Date: Fri, 11 Apr 2025 15:41:37 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: soc/amd: add functions to retrieve I3C controller info
by Felix Held (Code Review) 11 Apr '25

11 Apr '25

Attention is currently required from: Martin L Roth. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/87280?usp=email ) Change subject: soc/amd: add functions to retrieve I3C controller info ...................................................................... soc/amd: add functions to retrieve I3C controller info Similarly to how things are done for the I2C controller configuration, implement the 'soc_get_i3c_ctrlr_info' function in all SoCs that have I3C controllers. This function returns the contents of the SoC's 'i3c_ctrlr' array containing the base addresses and ACPI names of the I3C controllers. This function will eventually be called by the common I3C code which will be implemented in future patches. Change-Id: Ib23fd896925770f49e567324bc8d12ac4c0944bd Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/common/block/include/amdblocks/i2c.h M src/soc/amd/genoa_poc/i2c.c M src/soc/amd/genoa_poc/include/soc/iomap.h M src/soc/amd/glinda/i2c.c M src/soc/amd/glinda/include/soc/iomap.h M src/soc/amd/mendocino/i2c.c M src/soc/amd/mendocino/include/soc/iomap.h M src/soc/amd/phoenix/i2c.c M src/soc/amd/phoenix/include/soc/iomap.h 9 files changed, 64 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/87280/1 diff --git a/src/soc/amd/common/block/include/amdblocks/i2c.h b/src/soc/amd/common/block/include/amdblocks/i2c.h index b02487a..94ac173 100644 --- a/src/soc/amd/common/block/include/amdblocks/i2c.h +++ b/src/soc/amd/common/block/include/amdblocks/i2c.h @@ -68,6 +68,11 @@ enum i2c_pad_rx_level rx_level; }; +struct soc_i3c_ctrlr_info { + uintptr_t bar; + const char *acpi_name; +}; + void fch_i2c_pad_init(unsigned int bus, enum i2c_speed speed, const struct i2c_pad_control *ctrl); @@ -94,4 +99,7 @@ /* Reset I2C peripherals. */ void sb_reset_i2c_peripherals(const struct soc_i2c_peripheral_reset_info *reset_info); +/* Getter function to get the SoC I3C controller information. */ +const struct soc_i3c_ctrlr_info *soc_get_i3c_ctrlr_info(size_t *num_ctrlrs); + #endif /* AMD_COMMON_BLOCK_I2C_H */ diff --git a/src/soc/amd/genoa_poc/i2c.c b/src/soc/amd/genoa_poc/i2c.c index 6436e3d..3d18123 100644 --- a/src/soc/amd/genoa_poc/i2c.c +++ b/src/soc/amd/genoa_poc/i2c.c @@ -25,6 +25,13 @@ { I2C_MASTER_MODE, APU_I2C5_BASE, "I2C5" } }; +static const struct soc_i3c_ctrlr_info i3c_ctrlr[I3C_CTRLR_COUNT] = { + { APU_I3C0_BASE, "I3C0" }, + { APU_I3C1_BASE, "I3C1" }, + { APU_I3C2_BASE, "I3C2" }, + { APU_I3C3_BASE, "I3C3" } +}; + void reset_i2c_peripherals(void) { const struct soc_amd_genoa_poc_config *cfg = config_of_soc(); @@ -54,3 +61,9 @@ *num_buses = ARRAY_SIZE(config->i2c); return config->i2c; } + +const struct soc_i3c_ctrlr_info *soc_get_i3c_ctrlr_info(size_t *num_ctrlrs) +{ + *num_ctrlrs = ARRAY_SIZE(i3c_ctrlr); + return i3c_ctrlr; +} diff --git a/src/soc/amd/genoa_poc/include/soc/iomap.h b/src/soc/amd/genoa_poc/include/soc/iomap.h index f7a1bac..179fb3d 100644 --- a/src/soc/amd/genoa_poc/include/soc/iomap.h +++ b/src/soc/amd/genoa_poc/include/soc/iomap.h @@ -6,6 +6,7 @@ #define I2C_MASTER_DEV_COUNT 6 #define I2C_PERIPHERAL_DEV_COUNT 0 #define I2C_CTRLR_COUNT (I2C_MASTER_DEV_COUNT + I2C_PERIPHERAL_DEV_COUNT) +#define I3C_CTRLR_COUNT 4 #define SPI_BASE_ADDRESS 0xfec10000 diff --git a/src/soc/amd/glinda/i2c.c b/src/soc/amd/glinda/i2c.c index ab45ff5..99184ac 100644 --- a/src/soc/amd/glinda/i2c.c +++ b/src/soc/amd/glinda/i2c.c @@ -43,6 +43,13 @@ } #endif +static const struct soc_i3c_ctrlr_info i3c_ctrlr[I3C_CTRLR_COUNT] = { + { APU_I3C0_BASE, "I3C0" }, + { APU_I3C1_BASE, "I3C1" }, + { APU_I3C2_BASE, "I3C2" }, + { APU_I3C3_BASE, "I3C3" } +}; + void reset_i2c_peripherals(void) { const struct soc_amd_glinda_config *cfg = config_of_soc(); @@ -77,3 +84,9 @@ *num_buses = ARRAY_SIZE(config->i2c); return config->i2c; } + +const struct soc_i3c_ctrlr_info *soc_get_i3c_ctrlr_info(size_t *num_ctrlrs) +{ + *num_ctrlrs = ARRAY_SIZE(i3c_ctrlr); + return i3c_ctrlr; +} diff --git a/src/soc/amd/glinda/include/soc/iomap.h b/src/soc/amd/glinda/include/soc/iomap.h index bb68e17..32890dd 100644 --- a/src/soc/amd/glinda/include/soc/iomap.h +++ b/src/soc/amd/glinda/include/soc/iomap.h @@ -6,6 +6,7 @@ #define I2C_MASTER_DEV_COUNT 4 #define I2C_PERIPHERAL_DEV_COUNT 0 /* TODO: Only master for now. */ #define I2C_CTRLR_COUNT (I2C_MASTER_DEV_COUNT + I2C_PERIPHERAL_DEV_COUNT) +#define I3C_CTRLR_COUNT 4 #if ENV_X86 diff --git a/src/soc/amd/mendocino/i2c.c b/src/soc/amd/mendocino/i2c.c index 92433a7..51c34f6 100644 --- a/src/soc/amd/mendocino/i2c.c +++ b/src/soc/amd/mendocino/i2c.c @@ -41,6 +41,13 @@ } #endif +static const struct soc_i3c_ctrlr_info i3c_ctrlr[I3C_CTRLR_COUNT] = { + { APU_I3C0_BASE, "I3C0" }, + { APU_I3C1_BASE, "I3C1" }, + { APU_I3C2_BASE, "I3C2" }, + { APU_I3C3_BASE, "I3C3" } +}; + void reset_i2c_peripherals(void) { const struct soc_amd_mendocino_config *cfg = config_of_soc(); @@ -75,3 +82,9 @@ *num_buses = ARRAY_SIZE(config->i2c); return config->i2c; } + +const struct soc_i3c_ctrlr_info *soc_get_i3c_ctrlr_info(size_t *num_ctrlrs) +{ + *num_ctrlrs = ARRAY_SIZE(i3c_ctrlr); + return i3c_ctrlr; +} diff --git a/src/soc/amd/mendocino/include/soc/iomap.h b/src/soc/amd/mendocino/include/soc/iomap.h index bffdb5f..81a5d17 100644 --- a/src/soc/amd/mendocino/include/soc/iomap.h +++ b/src/soc/amd/mendocino/include/soc/iomap.h @@ -6,6 +6,7 @@ #define I2C_MASTER_DEV_COUNT 4 #define I2C_PERIPHERAL_DEV_COUNT 0 /* TODO: Only master for now. */ #define I2C_CTRLR_COUNT (I2C_MASTER_DEV_COUNT + I2C_PERIPHERAL_DEV_COUNT) +#define I3C_CTRLR_COUNT 4 #if ENV_X86 diff --git a/src/soc/amd/phoenix/i2c.c b/src/soc/amd/phoenix/i2c.c index e069c23..cfcf9a8 100644 --- a/src/soc/amd/phoenix/i2c.c +++ b/src/soc/amd/phoenix/i2c.c @@ -41,6 +41,13 @@ } #endif +static const struct soc_i3c_ctrlr_info i3c_ctrlr[I3C_CTRLR_COUNT] = { + { APU_I3C0_BASE, "I3C0" }, + { APU_I3C1_BASE, "I3C1" }, + { APU_I3C2_BASE, "I3C2" }, + { APU_I3C3_BASE, "I3C3" } +}; + void reset_i2c_peripherals(void) { const struct soc_amd_phoenix_config *cfg = config_of_soc(); @@ -75,3 +82,9 @@ *num_buses = ARRAY_SIZE(config->i2c); return config->i2c; } + +const struct soc_i3c_ctrlr_info *soc_get_i3c_ctrlr_info(size_t *num_ctrlrs) +{ + *num_ctrlrs = ARRAY_SIZE(i3c_ctrlr); + return i3c_ctrlr; +} diff --git a/src/soc/amd/phoenix/include/soc/iomap.h b/src/soc/amd/phoenix/include/soc/iomap.h index 63d8b08..d5dadaf 100644 --- a/src/soc/amd/phoenix/include/soc/iomap.h +++ b/src/soc/amd/phoenix/include/soc/iomap.h @@ -6,6 +6,7 @@ #define I2C_MASTER_DEV_COUNT 4 #define I2C_PERIPHERAL_DEV_COUNT 0 /* TODO: Only master for now. */ #define I2C_CTRLR_COUNT (I2C_MASTER_DEV_COUNT + I2C_PERIPHERAL_DEV_COUNT) +#define I3C_CTRLR_COUNT 4 #if ENV_X86 -- To view, visit https://review.coreboot.org/c/coreboot/+/87280?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib23fd896925770f49e567324bc8d12ac4c0944bd Gerrit-Change-Number: 87280 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com>

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[S] Change in coreboot[main]: soc/amd/*/include/aoac_defs.h: add I3C controller AOAC IDs
by Felix Held (Code Review) 11 Apr '25

11 Apr '25

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/87279?usp=email ) Change subject: soc/amd/*/include/aoac_defs.h: add I3C controller AOAC IDs ...................................................................... soc/amd/*/include/aoac_defs.h: add I3C controller AOAC IDs Add the AOAC IDs of the I3C controllers. The following documentation was used to verify this: Genoa: #55901 Rev 0.40 Mendocino: #57243 Rev 3.08 Rembrandt: #56558 Rev 3.09 (in Mendocino directory) Phoenix: #57019 Rev 3.09 Glinda: #57254 Rev 3.00 Faegan: #57928 Rev 1.51 (in Glinda directory) Change-Id: I54d049c58756251506f94d220e1970ccec170918 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/genoa_poc/include/soc/aoac_defs.h M src/soc/amd/glinda/include/soc/aoac_defs.h M src/soc/amd/mendocino/include/soc/aoac_defs.h M src/soc/amd/phoenix/include/soc/aoac_defs.h 4 files changed, 16 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/87279/1 diff --git a/src/soc/amd/genoa_poc/include/soc/aoac_defs.h b/src/soc/amd/genoa_poc/include/soc/aoac_defs.h index c5c11bb..6225399 100644 --- a/src/soc/amd/genoa_poc/include/soc/aoac_defs.h +++ b/src/soc/amd/genoa_poc/include/soc/aoac_defs.h @@ -13,8 +13,12 @@ #define FCH_AOAC_DEV_I2C5 10 #define FCH_AOAC_DEV_UART0 11 #define FCH_AOAC_DEV_UART1 12 +#define FCH_AOAC_DEV_I3C1 13 +#define FCH_AOAC_DEV_I3C2 14 +#define FCH_AOAC_DEV_I3C3 15 #define FCH_AOAC_DEV_UART2 16 #define FCH_AOAC_DEV_AMBA 17 +#define FCH_AOAC_DEV_I3C0 21 #define FCH_AOAC_DEV_ESPI 27 #endif /* AMD_GENOA_POC_AOAC_DEFS_H */ diff --git a/src/soc/amd/glinda/include/soc/aoac_defs.h b/src/soc/amd/glinda/include/soc/aoac_defs.h index 98fb4ce..8704d9c 100644 --- a/src/soc/amd/glinda/include/soc/aoac_defs.h +++ b/src/soc/amd/glinda/include/soc/aoac_defs.h @@ -13,9 +13,13 @@ #define FCH_AOAC_DEV_I2C3 8 #define FCH_AOAC_DEV_UART0 11 #define FCH_AOAC_DEV_UART1 12 +#define FCH_AOAC_DEV_I3C1 13 +#define FCH_AOAC_DEV_I3C2 14 +#define FCH_AOAC_DEV_I3C3 15 #define FCH_AOAC_DEV_UART2 16 #define FCH_AOAC_DEV_AMBA 17 #define FCH_AOAC_DEV_UART4 20 +#define FCH_AOAC_DEV_I3C0 21 #define FCH_AOAC_DEV_UART3 26 #define FCH_AOAC_DEV_ESPI 27 diff --git a/src/soc/amd/mendocino/include/soc/aoac_defs.h b/src/soc/amd/mendocino/include/soc/aoac_defs.h index 5dcca03..e81b610 100644 --- a/src/soc/amd/mendocino/include/soc/aoac_defs.h +++ b/src/soc/amd/mendocino/include/soc/aoac_defs.h @@ -13,9 +13,13 @@ #define FCH_AOAC_DEV_I2C5 10 #define FCH_AOAC_DEV_UART0 11 #define FCH_AOAC_DEV_UART1 12 +#define FCH_AOAC_DEV_I3C1 13 +#define FCH_AOAC_DEV_I3C2 14 +#define FCH_AOAC_DEV_I3C3 15 #define FCH_AOAC_DEV_UART2 16 #define FCH_AOAC_DEV_AMBA 17 #define FCH_AOAC_DEV_UART4 20 +#define FCH_AOAC_DEV_I3C0 21 #define FCH_AOAC_DEV_UART3 26 #define FCH_AOAC_DEV_ESPI 27 diff --git a/src/soc/amd/phoenix/include/soc/aoac_defs.h b/src/soc/amd/phoenix/include/soc/aoac_defs.h index 96df50ba..2fe0cb7 100644 --- a/src/soc/amd/phoenix/include/soc/aoac_defs.h +++ b/src/soc/amd/phoenix/include/soc/aoac_defs.h @@ -13,9 +13,13 @@ #define FCH_AOAC_DEV_I2C5 10 #define FCH_AOAC_DEV_UART0 11 #define FCH_AOAC_DEV_UART1 12 +#define FCH_AOAC_DEV_I3C1 13 +#define FCH_AOAC_DEV_I3C2 14 +#define FCH_AOAC_DEV_I3C3 15 #define FCH_AOAC_DEV_UART2 16 #define FCH_AOAC_DEV_AMBA 17 #define FCH_AOAC_DEV_UART4 20 +#define FCH_AOAC_DEV_I3C0 21 #define FCH_AOAC_DEV_UART3 26 #define FCH_AOAC_DEV_ESPI 27 -- To view, visit https://review.coreboot.org/c/coreboot/+/87279?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I54d049c58756251506f94d220e1970ccec170918 Gerrit-Change-Number: 87279 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de>

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[M] Change in coreboot[main]: soc/amd: report I3C controller MMIO to resource allocator
by Maximilian Brune (Code Review) 11 Apr '25

11 Apr '25

Attention is currently required from: Ana Carolina Cabral, Felix Held, Martin L Roth, Patrick Rudolph. Maximilian Brune has posted comments on this change by Felix Held. ( https://review.coreboot.org/c/coreboot/+/87277?usp=email ) Change subject: soc/amd: report I3C controller MMIO to resource allocator ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/87277?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iebf709d2548f2535b2a2a03a4f6da9531559c238 Gerrit-Change-Number: 87277 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Ana Carolina Cabral <ana.cpmelo95(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Ana Carolina Cabral <ana.cpmelo95(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 11 Apr 2025 14:41:00 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: soc/amd: add I3C controller base addresses and devicetree entries
by Maximilian Brune (Code Review) 11 Apr '25

11 Apr '25

Attention is currently required from: Ana Carolina Cabral, Felix Held, Patrick Rudolph. Maximilian Brune has posted comments on this change by Felix Held. ( https://review.coreboot.org/c/coreboot/+/87276?usp=email ) Change subject: soc/amd: add I3C controller base addresses and devicetree entries ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/87276?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6e8073e6498266b909b6cc5f589353f2ed23a62f Gerrit-Change-Number: 87276 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Ana Carolina Cabral <ana.cpmelo95(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Ana Carolina Cabral <ana.cpmelo95(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 11 Apr 2025 14:35:28 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[L] Change in coreboot[main]: Documentation: Add chip operations
by Matt DeVillier (Code Review) 11 Apr '25

11 Apr '25

Attention is currently required from: Martin L Roth. Matt DeVillier has posted comments on this change by Martin L Roth. ( https://review.coreboot.org/c/coreboot/+/87201?usp=email ) Change subject: Documentation: Add chip operations ...................................................................... Patch Set 2: Code-Review+1 (1 comment) Patchset: PS2: I think this is a great start. My only quarrel would be that it reads like chip_ops only exist at the SoC/chipset or mainboard level, and ignores their use in devicetree drivers. I'd have to think about how to best integrate that part though. -- To view, visit https://review.coreboot.org/c/coreboot/+/87201?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5373eab2de2e255f9e3576794b9ad02d9711a6c2 Gerrit-Change-Number: 87201 Gerrit-PatchSet: 2 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Comment-Date: Fri, 11 Apr 2025 14:11:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: soc/amd: report I3C controller MMIO to resource allocator
by Felix Held (Code Review) 11 Apr '25

11 Apr '25

Attention is currently required from: Martin L Roth. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/87277?usp=email ) Change subject: soc/amd: report I3C controller MMIO to resource allocator ...................................................................... soc/amd: report I3C controller MMIO to resource allocator Add minimal common AMD I3C controller code that reports the MMIO region used by the different I3C controllers to the resource allocator. For this to work, select the introduced SOC_AMD_COMMON_BLOCK_I3C Kconfig option and add the 'soc_amd_i3c_mmio_ops' device operations to the I3C device devicetree entries on all SoCs that include I3C controllers. Change-Id: Iebf709d2548f2535b2a2a03a4f6da9531559c238 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/common/block/i2c/Kconfig M src/soc/amd/common/block/i2c/Makefile.mk A src/soc/amd/common/block/i2c/i3c.c M src/soc/amd/genoa_poc/Kconfig M src/soc/amd/genoa_poc/chipset.cb M src/soc/amd/glinda/Kconfig M src/soc/amd/glinda/chipset.cb M src/soc/amd/mendocino/Kconfig M src/soc/amd/mendocino/chipset_mendocino.cb M src/soc/amd/mendocino/chipset_rembrandt.cb M src/soc/amd/phoenix/Kconfig M src/soc/amd/phoenix/chipset_fsp.cb M src/soc/amd/phoenix/chipset_opensil.cb 13 files changed, 50 insertions(+), 24 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/87277/1 diff --git a/src/soc/amd/common/block/i2c/Kconfig b/src/soc/amd/common/block/i2c/Kconfig index 9cdf8f5..91f6907 100644 --- a/src/soc/amd/common/block/i2c/Kconfig +++ b/src/soc/amd/common/block/i2c/Kconfig @@ -27,3 +27,8 @@ connected, which is shared between x86 and PSP. This is necessary to ensure proper communication with I2C peripherals connected to such bus. + +config SOC_AMD_COMMON_BLOCK_I3C + bool + help + Select this option to add FCH I3C controller functions to the build. diff --git a/src/soc/amd/common/block/i2c/Makefile.mk b/src/soc/amd/common/block/i2c/Makefile.mk index 2812fb3..5bce8f9 100644 --- a/src/soc/amd/common/block/i2c/Makefile.mk +++ b/src/soc/amd/common/block/i2c/Makefile.mk @@ -2,3 +2,4 @@ all-$(CONFIG_SOC_AMD_COMMON_BLOCK_I2C) += i2c.c all-$(CONFIG_SOC_AMD_COMMON_BLOCK_I2C_PAD_CTRL) += i2c_pad_ctrl.c all-$(CONFIG_SOC_AMD_COMMON_BLOCK_I23C_PAD_CTRL) += i23c_pad_ctrl.c +all-$(CONFIG_SOC_AMD_COMMON_BLOCK_I3C) += i3c.c diff --git a/src/soc/amd/common/block/i2c/i3c.c b/src/soc/amd/common/block/i2c/i3c.c new file mode 100644 index 0000000..26230c2 --- /dev/null +++ b/src/soc/amd/common/block/i2c/i3c.c @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <amdblocks/i2c.h> +#include <device/device.h> +#include <device/i2c.h> +#include <device/mmio.h> + +static void i3c_read_resources(struct device *dev) +{ + mmio_range(dev, 0, dev->path.mmio.addr, 4 * KiB); +} + +struct device_operations soc_amd_i3c_mmio_ops = { + .read_resources = i3c_read_resources, + .set_resources = noop_set_resources, +}; diff --git a/src/soc/amd/genoa_poc/Kconfig b/src/soc/amd/genoa_poc/Kconfig index 3e7246b..503b9fd 100644 --- a/src/soc/amd/genoa_poc/Kconfig +++ b/src/soc/amd/genoa_poc/Kconfig @@ -29,6 +29,7 @@ select SOC_AMD_COMMON_BLOCK_DATA_FABRIC_EXTENDED_MMIO select SOC_AMD_COMMON_BLOCK_HAS_ESPI select SOC_AMD_COMMON_BLOCK_I2C + select SOC_AMD_COMMON_BLOCK_I3C select SOC_AMD_COMMON_BLOCK_IOMMU select SOC_AMD_COMMON_BLOCK_LPC select SOC_AMD_COMMON_BLOCK_MCAX diff --git a/src/soc/amd/genoa_poc/chipset.cb b/src/soc/amd/genoa_poc/chipset.cb index 60eea56..b22c186 100644 --- a/src/soc/amd/genoa_poc/chipset.cb +++ b/src/soc/amd/genoa_poc/chipset.cb @@ -386,9 +386,9 @@ device mmio 0xfedc9000 alias uart_0 off ops amd_uart_mmio_ops end device mmio 0xfedca000 alias uart_1 off ops amd_uart_mmio_ops end device mmio 0xfedce000 alias uart_2 off ops amd_uart_mmio_ops end - device mmio 0xfedd2000 alias i3c_0 off end - device mmio 0xfedd3000 alias i3c_1 off end - device mmio 0xfedd4000 alias i3c_2 off end - device mmio 0xfedd6000 alias i3c_3 off end + device mmio 0xfedd2000 alias i3c_0 off ops soc_amd_i3c_mmio_ops end + device mmio 0xfedd3000 alias i3c_1 off ops soc_amd_i3c_mmio_ops end + device mmio 0xfedd4000 alias i3c_2 off ops soc_amd_i3c_mmio_ops end + device mmio 0xfedd6000 alias i3c_3 off ops soc_amd_i3c_mmio_ops end end diff --git a/src/soc/amd/glinda/Kconfig b/src/soc/amd/glinda/Kconfig index a02492c..17b349f 100644 --- a/src/soc/amd/glinda/Kconfig +++ b/src/soc/amd/glinda/Kconfig @@ -53,6 +53,7 @@ select SOC_AMD_COMMON_BLOCK_HAS_ESPI_ALERT_ENABLE # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_I2C # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_I23C_PAD_CTRL # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_I3C select SOC_AMD_COMMON_BLOCK_IOMMU # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_LPC # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_MCAX # TODO: Check if this is still correct diff --git a/src/soc/amd/glinda/chipset.cb b/src/soc/amd/glinda/chipset.cb index 321ecb7..853e052 100644 --- a/src/soc/amd/glinda/chipset.cb +++ b/src/soc/amd/glinda/chipset.cb @@ -148,8 +148,8 @@ device mmio 0xfedce000 alias uart_2 off ops amd_uart_mmio_ops end device mmio 0xfedcf000 alias uart_3 off ops amd_uart_mmio_ops end device mmio 0xfedd1000 alias uart_4 off ops amd_uart_mmio_ops end - device mmio 0xfedd2000 alias i3c_0 off end - device mmio 0xfedd3000 alias i3c_1 off end - device mmio 0xfedd4000 alias i3c_2 off end - device mmio 0xfedd6000 alias i3c_3 off end + device mmio 0xfedd2000 alias i3c_0 off ops soc_amd_i3c_mmio_ops end + device mmio 0xfedd3000 alias i3c_1 off ops soc_amd_i3c_mmio_ops end + device mmio 0xfedd4000 alias i3c_2 off ops soc_amd_i3c_mmio_ops end + device mmio 0xfedd6000 alias i3c_3 off ops soc_amd_i3c_mmio_ops end end diff --git a/src/soc/amd/mendocino/Kconfig b/src/soc/amd/mendocino/Kconfig index f67ecb2..b51e9e9 100644 --- a/src/soc/amd/mendocino/Kconfig +++ b/src/soc/amd/mendocino/Kconfig @@ -53,6 +53,7 @@ select SOC_AMD_COMMON_BLOCK_HAS_ESPI_ALERT_ENABLE select SOC_AMD_COMMON_BLOCK_I2C select SOC_AMD_COMMON_BLOCK_I23C_PAD_CTRL + select SOC_AMD_COMMON_BLOCK_I3C select SOC_AMD_COMMON_BLOCK_IOMMU select SOC_AMD_COMMON_BLOCK_LPC select SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA diff --git a/src/soc/amd/mendocino/chipset_mendocino.cb b/src/soc/amd/mendocino/chipset_mendocino.cb index 81a7932..5ab6a9c 100644 --- a/src/soc/amd/mendocino/chipset_mendocino.cb +++ b/src/soc/amd/mendocino/chipset_mendocino.cb @@ -93,8 +93,8 @@ device mmio 0xfedce000 alias uart_2 off ops amd_uart_mmio_ops end device mmio 0xfedcf000 alias uart_3 off ops amd_uart_mmio_ops end device mmio 0xfedd1000 alias uart_4 off ops amd_uart_mmio_ops end - device mmio 0xfedd2000 alias i3c_0 off end - device mmio 0xfedd3000 alias i3c_1 off end - device mmio 0xfedd4000 alias i3c_2 off end - device mmio 0xfedd6000 alias i3c_3 off end + device mmio 0xfedd2000 alias i3c_0 off ops soc_amd_i3c_mmio_ops end + device mmio 0xfedd3000 alias i3c_1 off ops soc_amd_i3c_mmio_ops end + device mmio 0xfedd4000 alias i3c_2 off ops soc_amd_i3c_mmio_ops end + device mmio 0xfedd6000 alias i3c_3 off ops soc_amd_i3c_mmio_ops end end diff --git a/src/soc/amd/mendocino/chipset_rembrandt.cb b/src/soc/amd/mendocino/chipset_rembrandt.cb index cb549cf..0783b2f 100644 --- a/src/soc/amd/mendocino/chipset_rembrandt.cb +++ b/src/soc/amd/mendocino/chipset_rembrandt.cb @@ -96,8 +96,8 @@ device mmio 0xfedce000 alias uart_2 off ops amd_uart_mmio_ops end device mmio 0xfedcf000 alias uart_3 off ops amd_uart_mmio_ops end device mmio 0xfedd1000 alias uart_4 off ops amd_uart_mmio_ops end - device mmio 0xfedd2000 alias i3c_0 off end - device mmio 0xfedd3000 alias i3c_1 off end - device mmio 0xfedd4000 alias i3c_2 off end - device mmio 0xfedd6000 alias i3c_3 off end + device mmio 0xfedd2000 alias i3c_0 off ops soc_amd_i3c_mmio_ops end + device mmio 0xfedd3000 alias i3c_1 off ops soc_amd_i3c_mmio_ops end + device mmio 0xfedd4000 alias i3c_2 off ops soc_amd_i3c_mmio_ops end + device mmio 0xfedd6000 alias i3c_3 off ops soc_amd_i3c_mmio_ops end end diff --git a/src/soc/amd/phoenix/Kconfig b/src/soc/amd/phoenix/Kconfig index b15c12d..07b1bc0 100644 --- a/src/soc/amd/phoenix/Kconfig +++ b/src/soc/amd/phoenix/Kconfig @@ -49,6 +49,7 @@ select SOC_AMD_COMMON_BLOCK_HAS_ESPI_ALERT_ENABLE select SOC_AMD_COMMON_BLOCK_I2C select SOC_AMD_COMMON_BLOCK_I23C_PAD_CTRL + select SOC_AMD_COMMON_BLOCK_I3C select SOC_AMD_COMMON_BLOCK_IOMMU select SOC_AMD_COMMON_BLOCK_LPC select SOC_AMD_COMMON_BLOCK_MCAX diff --git a/src/soc/amd/phoenix/chipset_fsp.cb b/src/soc/amd/phoenix/chipset_fsp.cb index de05cbf..dcd51f5 100644 --- a/src/soc/amd/phoenix/chipset_fsp.cb +++ b/src/soc/amd/phoenix/chipset_fsp.cb @@ -145,8 +145,8 @@ device mmio 0xfedce000 alias uart_2 off ops amd_uart_mmio_ops end device mmio 0xfedcf000 alias uart_3 off ops amd_uart_mmio_ops end device mmio 0xfedd1000 alias uart_4 off ops amd_uart_mmio_ops end - device mmio 0xfedd2000 alias i3c_0 off end - device mmio 0xfedd3000 alias i3c_1 off end - device mmio 0xfedd4000 alias i3c_2 off end - device mmio 0xfedd6000 alias i3c_3 off end + device mmio 0xfedd2000 alias i3c_0 off ops soc_amd_i3c_mmio_ops end + device mmio 0xfedd3000 alias i3c_1 off ops soc_amd_i3c_mmio_ops end + device mmio 0xfedd4000 alias i3c_2 off ops soc_amd_i3c_mmio_ops end + device mmio 0xfedd6000 alias i3c_3 off ops soc_amd_i3c_mmio_ops end end diff --git a/src/soc/amd/phoenix/chipset_opensil.cb b/src/soc/amd/phoenix/chipset_opensil.cb index c2ea6c0..157daf7 100644 --- a/src/soc/amd/phoenix/chipset_opensil.cb +++ b/src/soc/amd/phoenix/chipset_opensil.cb @@ -165,8 +165,8 @@ device mmio 0xfedce000 alias uart_2 off ops amd_uart_mmio_ops end device mmio 0xfedcf000 alias uart_3 off ops amd_uart_mmio_ops end device mmio 0xfedd1000 alias uart_4 off ops amd_uart_mmio_ops end - device mmio 0xfedd2000 alias i3c_0 off end - device mmio 0xfedd3000 alias i3c_1 off end - device mmio 0xfedd4000 alias i3c_2 off end - device mmio 0xfedd6000 alias i3c_3 off end + device mmio 0xfedd2000 alias i3c_0 off ops soc_amd_i3c_mmio_ops end + device mmio 0xfedd3000 alias i3c_1 off ops soc_amd_i3c_mmio_ops end + device mmio 0xfedd4000 alias i3c_2 off ops soc_amd_i3c_mmio_ops end + device mmio 0xfedd6000 alias i3c_3 off ops soc_amd_i3c_mmio_ops end end -- To view, visit https://review.coreboot.org/c/coreboot/+/87277?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iebf709d2548f2535b2a2a03a4f6da9531559c238 Gerrit-Change-Number: 87277 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com>

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