coreboot-gerrit April 2025

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[S] Change in coreboot[main]: soc/amd/common/block: Read SPI rom remapping
by Felix Held (Code Review) 11 Apr '25

11 Apr '25

Attention is currently required from: Fred Reitberger, Jason Glenesk, Matt DeVillier, Patrick Rudolph. Felix Held has posted comments on this change by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/87175?usp=email ) Change subject: soc/amd/common/block: Read SPI rom remapping ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/87175?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I046e029e6135ab57f79b675c62b233203f00d705 Gerrit-Change-Number: 87175 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Fri, 11 Apr 2025 20:35:10 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: soc/amd/picasso/chipset.cb: Enable gpp_bridge_[a/b] by default
by Felix Held (Code Review) 11 Apr '25

11 Apr '25

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86598?usp=email ) Change subject: soc/amd/picasso/chipset.cb: Enable gpp_bridge_[a/b] by default ...................................................................... soc/amd/picasso/chipset.cb: Enable gpp_bridge_[a/b] by default Since FSP doesn't support disabling bridges and has no UPDs for that, they must be enabled in DT to make sure they are properly initialized during PCI enumeration as expected by the payload (EDK2 for example). It might be OK to have them set to off when all devices behind the bridge are also off and FSP disables those secondary devices. In general something that cannot be hidden/shut off shouldn't be marked as such, as later stages (payload/OS) might find it active, but unconfigured. Change-Id: I4104a6af00304b0a7c50ba0e09ad19a0ed9d2733 Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86598 Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/zork/variants/baseboard/dalboz/devicetree.cb M src/mainboard/google/zork/variants/baseboard/trembyle/devicetree.cb M src/soc/amd/picasso/chipset.cb 3 files changed, 4 insertions(+), 2 deletions(-) Approvals: Matt DeVillier: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/google/zork/variants/baseboard/dalboz/devicetree.cb b/src/mainboard/google/zork/variants/baseboard/dalboz/devicetree.cb index e8b73ca..4af7231 100644 --- a/src/mainboard/google/zork/variants/baseboard/dalboz/devicetree.cb +++ b/src/mainboard/google/zork/variants/baseboard/dalboz/devicetree.cb @@ -344,6 +344,7 @@ device ref hda off end # HDA device ref mp2 on end # non-Sensor Fusion Hub device end + device ref internal_bridge_b off end # internal bridge to bus B device ref lpc_bridge on chip ec/google/chromeec device pnp 0c09.0 alias cros_ec on diff --git a/src/mainboard/google/zork/variants/baseboard/trembyle/devicetree.cb b/src/mainboard/google/zork/variants/baseboard/trembyle/devicetree.cb index d6f2136..9b5a4c0 100644 --- a/src/mainboard/google/zork/variants/baseboard/trembyle/devicetree.cb +++ b/src/mainboard/google/zork/variants/baseboard/trembyle/devicetree.cb @@ -370,6 +370,7 @@ device ref hda off end # HDA device ref mp2 on end # non-Sensor Fusion Hub device end + device ref internal_bridge_b off end # internal bridge to bus B device ref lpc_bridge on chip ec/google/chromeec device pnp 0c09.0 alias cros_ec on diff --git a/src/soc/amd/picasso/chipset.cb b/src/soc/amd/picasso/chipset.cb index c11d502..a254cea 100644 --- a/src/soc/amd/picasso/chipset.cb +++ b/src/soc/amd/picasso/chipset.cb @@ -17,7 +17,7 @@ device pci 01.6 alias gpp_bridge_5 off ops amd_external_pcie_gpp_ops end device pci 01.7 alias gpp_bridge_6 off ops amd_external_pcie_gpp_ops end device pci 08.0 on end # Dummy device function, do not disable - device pci 08.1 alias internal_bridge_a off # internal bridge to bus A + device pci 08.1 alias internal_bridge_a on # internal bridge to bus A ops amd_internal_pcie_gpp_ops device pci 0.0 alias gfx off ops amd_graphics_ops end # internal GPU device pci 0.1 alias gfx_hda off end # display HD Audio controller @@ -32,7 +32,7 @@ device pci 0.6 alias hda off end # main HD Audio Controller device pci 0.7 alias mp2 off end # sensor fusion hub (MP2) end - device pci 08.2 alias internal_bridge_b off # internal bridge to bus B + device pci 08.2 alias internal_bridge_b on # internal bridge to bus B ops amd_internal_pcie_gpp_ops device pci 0.0 alias sata off ops amd_sata_ops end device pci 0.1 alias xgbe_0 off end -- To view, visit https://review.coreboot.org/c/coreboot/+/86598?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4104a6af00304b0a7c50ba0e09ad19a0ed9d2733 Gerrit-Change-Number: 86598 Gerrit-PatchSet: 3 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: soc/amd/cezanne/chipset.cb: Enable gpp_bridge_[a/b/c] by default
by Felix Held (Code Review) 11 Apr '25

11 Apr '25

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86272?usp=email ) Change subject: soc/amd/cezanne/chipset.cb: Enable gpp_bridge_[a/b/c] by default ...................................................................... soc/amd/cezanne/chipset.cb: Enable gpp_bridge_[a/b/c] by default Since FSP doesn't support disabling bridges and has no UPDs for that, they must be enabled in DT to make sure they are properly initialized during PCI enumeration as expected by the payload (EDK2 for example). It might be OK to have them set to off when all devices behind the bridge are also off and FSP disables those secondary devices. In general something that cannot be hidden/shut off shouldn't be marked as such, as later stages (payload/OS) might find it active, but unconfigured. Change-Id: Ie34bb2abc0211963b2613d1b50b1767df31c1062 Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86272 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/mainboard/google/guybrush/variants/baseboard/devicetree.cb M src/soc/amd/cezanne/chipset.cb 2 files changed, 5 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved Matt DeVillier: Looks good to me, approved diff --git a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb index b58dc2c..147112a 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb @@ -350,6 +350,8 @@ end end # Audio end + device ref gpp_bridge_b off end # Internal GPP Bridge 1 to Bus B + device ref gpp_bridge_c off end # Internal GPP Bridge 2 to Bus C device ref lpc_bridge on chip ec/google/chromeec diff --git a/src/soc/amd/cezanne/chipset.cb b/src/soc/amd/cezanne/chipset.cb index ccce485..14dba64 100644 --- a/src/soc/amd/cezanne/chipset.cb +++ b/src/soc/amd/cezanne/chipset.cb @@ -22,7 +22,7 @@ device pci 02.7 alias gpp_bridge_6 off ops amd_external_pcie_gpp_ops end device pci 08.0 on end # Dummy device function, do not disable - device pci 08.1 alias gpp_bridge_a off # Internal GPP Bridge 0 to Bus A + device pci 08.1 alias gpp_bridge_a on # Internal GPP Bridge 0 to Bus A ops amd_internal_pcie_gpp_ops device pci 0.0 alias gfx off ops amd_graphics_ops end # Internal GPU (GFX) device pci 0.1 alias gfx_hda off end # Display HD Audio Controller (GFXAZ) @@ -83,14 +83,14 @@ device pci 0.6 alias hda off end # Audio Processor HD Audio Controller (main AZ) device pci 0.7 alias mp2 off end # Sensor Fusion Hub (MP2) end - device pci 08.2 alias gpp_bridge_b off # Internal GPP Bridge 1 to Bus B + device pci 08.2 alias gpp_bridge_b on # Internal GPP Bridge 1 to Bus B ops amd_internal_pcie_gpp_ops device pci 0.0 alias sata_0 off end # first SATA controller; AHCI Mode device pci 0.1 alias sata_1 off end # second SATA Controller; SATA Raid/AHCI Mode device pci 0.2 alias xgbe_0 off end # 10 GbE Controller Port 0 (XGBE0) device pci 0.3 alias xgbe_1 off end # 10 GbE Controller Port 1 (XGBE1) end - device pci 08.3 alias gpp_bridge_c off # Internal GPP Bridge 2 to Bus C + device pci 08.3 alias gpp_bridge_c on # Internal GPP Bridge 2 to Bus C ops amd_internal_pcie_gpp_ops device pci 0.0 alias dummy_function_c off end # PCIe Dummy Function device pci 0.2 alias i2s_ac97 off end # I2S/AC'97 Audio -- To view, visit https://review.coreboot.org/c/coreboot/+/86272?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie34bb2abc0211963b2613d1b50b1767df31c1062 Gerrit-Change-Number: 86272 Gerrit-PatchSet: 5 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com>

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[XS] Change in coreboot[main]: soc/intel/pantherlake: Remove implicit VBOOT_MUST_REQUEST_DISPLAY sel...
by Subrata Banik (Code Review) 11 Apr '25

11 Apr '25

Attention is currently required from: Intel coreboot Reviewers, Jayvik Desai, Kapil Porwal, Pranava Y N, Yu-Ping Wu. Hello Intel coreboot Reviewers, Jayvik Desai, Kapil Porwal, Pranava Y N, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/87284?usp=email to look at the new patch set (#2). Change subject: soc/intel/pantherlake: Remove implicit VBOOT_MUST_REQUEST_DISPLAY selection ...................................................................... soc/intel/pantherlake: Remove implicit VBOOT_MUST_REQUEST_DISPLAY selection The explicit selection of `CONFIG_VBOOT_MUST_REQUEST_DISPLAY` for Panther Lake SoC has been removed. Panther Lake platforms inherently enable display across all boot modes (normal, developer, recovery) when vboot is active. Therefore, explicitly selecting `VBOOT_MUST_REQUEST_DISPLAY` becomes redundant, especially when `VBOOT_ALWAYS_ENABLE_DISPLAY` is enabled due to the selection of `BMP_LOGO` for ChromeOS devices. TEST=Able to perform ec sync without any additional reboots. Change-Id: Ifa222d6910664a22eacdb6fea54e73b099ca96d1 Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/soc/intel/pantherlake/Kconfig 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/87284/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/87284?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifa222d6910664a22eacdb6fea54e73b099ca96d1 Gerrit-Change-Number: 87284 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com>

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[M] Change in coreboot[main]: soc/intel: Add Wildcat Lake CPU and PCIE device IDs
by Subrata Banik (Code Review) 11 Apr '25

11 Apr '25

Attention is currently required from: Appukuttan V K, Avi Uday, Intel coreboot Reviewers, Nick Vaccaro, Sowmya Aralguppe, Usha P, Varun Upadhyay. Subrata Banik has posted comments on this change by Appukuttan V K. ( https://review.coreboot.org/c/coreboot/+/87262?usp=email ) Change subject: soc/intel: Add Wildcat Lake CPU and PCIE device IDs ...................................................................... Patch Set 7: (1 comment) Patchset: PS7: why not combine all DID cls into one CB:87263 ? -- To view, visit https://review.coreboot.org/c/coreboot/+/87262?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4bc7a8ea898ee30d565a95b9f85d6f19886bcffb Gerrit-Change-Number: 87262 Gerrit-PatchSet: 7 Gerrit-Owner: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-Reviewer: Avi Uday <aviuday(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Varun Upadhyay <varun.upadhyay(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-Attention: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-Attention: Avi Uday <aviuday(a)google.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Attention: Varun Upadhyay <varun.upadhyay(a)intel.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Usha P <usha.p(a)intel.com> Gerrit-Comment-Date: Fri, 11 Apr 2025 18:02:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: soc/intel/pantherlake: Remove implicit VBOOT_MUST_REQUEST_DISPLAY sel...
by Subrata Banik (Code Review) 11 Apr '25

11 Apr '25

Attention is currently required from: Intel coreboot Reviewers, Jayvik Desai, Kapil Porwal, Pranava Y N. Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/87284?usp=email ) Change subject: soc/intel/pantherlake: Remove implicit VBOOT_MUST_REQUEST_DISPLAY selection ...................................................................... soc/intel/pantherlake: Remove implicit VBOOT_MUST_REQUEST_DISPLAY selection The explicit selection of `CONFIG_VBOOT_MUST_REQUEST_DISPLAY` for Panther Lake SoC has been removed. Panther Lake platforms inherently enable display across all boot modes (normal, developer, recovery) when vboot is active. Therefore, explicitly selecting `VBOOT_MUST_REQUEST_DISPLAY` becomes redundant, especially when `VBOOT_ALWAYS_ENABLE_DISPLAY` is enabled due to the selection of `_BMP_LOGO` for ChromeOS devices. TEST=Able to perform ec sync without any additional reboots. Change-Id: Ifa222d6910664a22eacdb6fea54e73b099ca96d1 Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/soc/intel/pantherlake/Kconfig 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/87284/1 diff --git a/src/soc/intel/pantherlake/Kconfig b/src/soc/intel/pantherlake/Kconfig index 36417db..1e956d1 100644 --- a/src/soc/intel/pantherlake/Kconfig +++ b/src/soc/intel/pantherlake/Kconfig @@ -300,7 +300,6 @@ default 0x7fff config VBOOT - select VBOOT_MUST_REQUEST_DISPLAY select VBOOT_SEPARATE_VERSTAGE select VBOOT_STARTS_IN_BOOTBLOCK select VBOOT_VBNV_CMOS -- To view, visit https://review.coreboot.org/c/coreboot/+/87284?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifa222d6910664a22eacdb6fea54e73b099ca96d1 Gerrit-Change-Number: 87284 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com>

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[XS] Change in coreboot[main]: lib/bootmode: Enforce display init requirement for vboot
by Subrata Banik (Code Review) 11 Apr '25

11 Apr '25

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/87283?usp=email ) Change subject: lib/bootmode: Enforce display init requirement for vboot ...................................................................... lib/bootmode: Enforce display init requirement for vboot The `display_init_required` function for vboot now mandates that either `CONFIG_VBOOT_MUST_REQUEST_DISPLAY` or `CONFIG_VBOOT_ALWAYS_ENABLE_DISPLAY` must be enabled. If neither of these Kconfig options is set when `CONFIG_VBOOT` is enabled, the code will now trigger `dead_code()`. This enforces the requirement that display initialization is explicitly requested or always enabled when vboot is active, aligning with the intended usage of `VB2_CONTEXT_DISPLAY_INIT`. TEST=Able to build google/fatcat. Change-Id: I371c0533057fb088ea15a5da6bd76173cea525aa Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/lib/bootmode.c 1 file changed, 5 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/87283/1 diff --git a/src/lib/bootmode.c b/src/lib/bootmode.c index 3cf77d6..dbfeb32 100644 --- a/src/lib/bootmode.c +++ b/src/lib/bootmode.c @@ -23,9 +23,11 @@ { /* For vboot, honor VB2_CONTEXT_DISPLAY_INIT. */ if (CONFIG(VBOOT)) { - /* Must always select MUST_REQUEST_DISPLAY when using this - function. */ - if (!CONFIG(VBOOT_MUST_REQUEST_DISPLAY)) + /* + * Display init requires VBOOT_MUST_REQUEST_DISPLAY || VBOOT_ALWAYS_ENABLE_DISPLAY; + * else assert build. + */ + if (!CONFIG(VBOOT_MUST_REQUEST_DISPLAY) && !CONFIG(VBOOT_ALWAYS_ENABLE_DISPLAY)) dead_code(); return vboot_get_context()->flags & VB2_CONTEXT_DISPLAY_INIT; } -- To view, visit https://review.coreboot.org/c/coreboot/+/87283?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I371c0533057fb088ea15a5da6bd76173cea525aa Gerrit-Change-Number: 87283 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com>

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[S] Change in coreboot[main]: arch/x86: Use defines for GDT segments
by Jérémy Compostella (Code Review) 11 Apr '25

11 Apr '25

Attention is currently required from: Patrick Rudolph. Jérémy Compostella has posted comments on this change by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/87254?usp=email ) Change subject: arch/x86: Use defines for GDT segments ...................................................................... Patch Set 2: Code-Review+2 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/87254/comment/a828bed1_5ae02319?us… : PS2, Line 9: GDT nit: GDT (Global Descriptor Table) -- To view, visit https://review.coreboot.org/c/coreboot/+/87254?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I40c15f6341bdef9cd457619ec81e7ac624ec2d63 Gerrit-Change-Number: 87254 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Comment-Date: Fri, 11 Apr 2025 17:14:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[XL] Change in coreboot[main]: vc/intel/fsp/ptl: Update header files from FSP 3071_00 to FSP 3103_05
by Subrata Banik (Code Review) 11 Apr '25

11 Apr '25

Attention is currently required from: Alok Agarwal, Intel coreboot Reviewers, Kapil Porwal, Paul Menzel, Pranava Y N, Ronak Kanabar, srinivas.kulkarni(a)intel.com. Subrata Banik has posted comments on this change by Alok Agarwal. ( https://review.coreboot.org/c/coreboot/+/87000?usp=email ) Change subject: vc/intel/fsp/ptl: Update header files from FSP 3071_00 to FSP 3103_05 ...................................................................... Patch Set 3: (1 comment) File src/vendorcode/intel/fsp/fsp2_0/pantherlake/MemInfoHob.h: https://review.coreboot.org/c/coreboot/+/87000/comment/dfd947e3_ebd3bdd3?us… : PS3, Line 2: file contains definitions required for creation of : Memory S3 Save data, Memory Info data and Memory Platform : data hobs. : : @copyright : Copyright (c) 1999 - 2024, Intel Corporation. All rights reserved.<BR> : This program and the accompanying materials are licensed and made available under : the terms and conditions of the BSD License that accompanies this distribution. : The full text of the license may be found at : http://opensource.org/licenses/bsd-license.php. : THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, : : WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. : : @par Specification Reference: : **/ : : #ifndef _MEM_INFO_HOB_H_ : #define _MEM_INFO_HOB_H_ : > Way too many changes here. It looks like you are changing the file encoding (unix vs. windows) +2 -- To view, visit https://review.coreboot.org/c/coreboot/+/87000?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I054e419ef23ada67347750e7a68014c2bb112199 Gerrit-Change-Number: 87000 Gerrit-PatchSet: 3 Gerrit-Owner: Alok Agarwal <alok.agarwal(a)intel.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: srinivas.kulkarni(a)intel.com Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Attention: Alok Agarwal <alok.agarwal(a)intel.com> Gerrit-Attention: srinivas.kulkarni(a)intel.com Gerrit-Comment-Date: Fri, 11 Apr 2025 17:14:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com>

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[XS] Change in coreboot[main]: soc/intel/common/cse: Skip CSE state setting with LITE_SYNC_BY_PAYLOAD
by Subrata Banik (Code Review) 11 Apr '25

11 Apr '25

Attention is currently required from: Intel coreboot Reviewers, Jérémy Compostella, Pranava Y N. Subrata Banik has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/87266?usp=email ) Change subject: soc/intel/common/cse: Skip CSE state setting with LITE_SYNC_BY_PAYLOAD ...................................................................... Patch Set 2: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/87266/comment/96be590b_df82e6e8?us… : PS1, Line 14: travering > traversing ? Acknowledged https://review.coreboot.org/c/coreboot/+/87266/comment/c3dfe32d_315a3d53?us… : PS1, Line 15: `option/me_state` file. > nit: **the** `option/me_state` file. Acknowledged -- To view, visit https://review.coreboot.org/c/coreboot/+/87266?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I43f5daab450989307d9b3529949e9f03cba4404d Gerrit-Change-Number: 87266 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Fri, 11 Apr 2025 17:14:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com>

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