coreboot-gerrit April 2025

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[XS] Change in coreboot[main]: soc/intel/common/cse: Skip CSE state setting with LITE_SYNC_BY_PAYLOAD
by Subrata Banik (Code Review) 11 Apr '25

11 Apr '25

Attention is currently required from: Intel coreboot Reviewers, Pranava Y N, Subrata Banik. Hello Intel coreboot Reviewers, Kapil Porwal, Pranava Y N, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/87266?usp=email to look at the new patch set (#2). Change subject: soc/intel/common/cse: Skip CSE state setting with LITE_SYNC_BY_PAYLOAD ...................................................................... soc/intel/common/cse: Skip CSE state setting with LITE_SYNC_BY_PAYLOAD This commit introduces a conditional bypass for ME state setting, potentially reducing CBFS traversal time when searching for the `option/me_state` file. TEST=Able to build and boot google/fatcat. Change-Id: I43f5daab450989307d9b3529949e9f03cba4404d Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/soc/intel/common/block/cse/cse.c 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/87266/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/87266?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I43f5daab450989307d9b3529949e9f03cba4404d Gerrit-Change-Number: 87266 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com>

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[XS] Change in coreboot[main]: soc/intel/common/cse: Skip CSE state setting with LITE_SYNC_BY_PAYLOAD
by Jérémy Compostella (Code Review) 11 Apr '25

11 Apr '25

Attention is currently required from: Intel coreboot Reviewers, Pranava Y N, Subrata Banik. Jérémy Compostella has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/87266?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: soc/intel/common/cse: Skip CSE state setting with LITE_SYNC_BY_PAYLOAD ...................................................................... Patch Set 1: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/87266/comment/9363dcef_db0b458b?us… : PS1, Line 14: travering traversing ? https://review.coreboot.org/c/coreboot/+/87266/comment/86d5196f_4cd72d8e?us… : PS1, Line 15: `option/me_state` file. nit: **the** `option/me_state` file. -- To view, visit https://review.coreboot.org/c/coreboot/+/87266?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I43f5daab450989307d9b3529949e9f03cba4404d Gerrit-Change-Number: 87266 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Fri, 11 Apr 2025 17:10:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: soc/intel/pantherlake: Adopt the MEMORY_INFO_DATA_HOB
by Jérémy Compostella (Code Review) 11 Apr '25

11 Apr '25

Attention is currently required from: Alok Agarwal, Intel coreboot Reviewers, Jayvik Desai, Pranava Y N, Ronak Kanabar, Subrata Banik, srinivas.kulkarni(a)intel.com. Jérémy Compostella has posted comments on this change by Alok Agarwal. ( https://review.coreboot.org/c/coreboot/+/86949?usp=email ) Change subject: soc/intel/pantherlake: Adopt the MEMORY_INFO_DATA_HOB ...................................................................... Patch Set 6: (1 comment) Patchset: PS6: Should it be on top of https://review.coreboot.org/c/coreboot/+/87000? -- To view, visit https://review.coreboot.org/c/coreboot/+/86949?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1f7ee111e299ef53795912f80b444c07facde11e Gerrit-Change-Number: 86949 Gerrit-PatchSet: 6 Gerrit-Owner: Alok Agarwal <alok.agarwal(a)intel.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: srinivas.kulkarni(a)intel.com Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Alok Agarwal <alok.agarwal(a)intel.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Attention: srinivas.kulkarni(a)intel.com Gerrit-Comment-Date: Fri, 11 Apr 2025 17:08:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XL] Change in coreboot[main]: vc/intel/fsp/ptl: Update header files from FSP 3071_00 to FSP 3103_05
by Jérémy Compostella (Code Review) 11 Apr '25

11 Apr '25

Attention is currently required from: Alok Agarwal, Intel coreboot Reviewers, Kapil Porwal, Paul Menzel, Pranava Y N, Ronak Kanabar, Subrata Banik, srinivas.kulkarni(a)intel.com. Jérémy Compostella has posted comments on this change by Alok Agarwal. ( https://review.coreboot.org/c/coreboot/+/87000?usp=email ) Change subject: vc/intel/fsp/ptl: Update header files from FSP 3071_00 to FSP 3103_05 ...................................................................... Patch Set 3: Code-Review-1 (1 comment) File src/vendorcode/intel/fsp/fsp2_0/pantherlake/MemInfoHob.h: https://review.coreboot.org/c/coreboot/+/87000/comment/089f1138_59049aa4?us… : PS3, Line 2: file contains definitions required for creation of : Memory S3 Save data, Memory Info data and Memory Platform : data hobs. : : @copyright : Copyright (c) 1999 - 2024, Intel Corporation. All rights reserved.<BR> : This program and the accompanying materials are licensed and made available under : the terms and conditions of the BSD License that accompanies this distribution. : The full text of the license may be found at : http://opensource.org/licenses/bsd-license.php. : THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, : : WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. : : @par Specification Reference: : **/ : : #ifndef _MEM_INFO_HOB_H_ : #define _MEM_INFO_HOB_H_ : Way too many changes here. It looks like you are changing the file encoding (unix vs. windows) -- To view, visit https://review.coreboot.org/c/coreboot/+/87000?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I054e419ef23ada67347750e7a68014c2bb112199 Gerrit-Change-Number: 87000 Gerrit-PatchSet: 3 Gerrit-Owner: Alok Agarwal <alok.agarwal(a)intel.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: srinivas.kulkarni(a)intel.com Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Attention: Alok Agarwal <alok.agarwal(a)intel.com> Gerrit-Attention: srinivas.kulkarni(a)intel.com Gerrit-Comment-Date: Fri, 11 Apr 2025 17:07:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: soc/intel/pantherlake: Adopt the MEMORY_INFO_DATA_HOB
by Jérémy Compostella (Code Review) 11 Apr '25

11 Apr '25

Attention is currently required from: Alok Agarwal, Intel coreboot Reviewers, Jayvik Desai, Pranava Y N, Ronak Kanabar, Subrata Banik, srinivas.kulkarni(a)intel.com. Jérémy Compostella has posted comments on this change by Alok Agarwal. ( https://review.coreboot.org/c/coreboot/+/86949?usp=email ) Change subject: soc/intel/pantherlake: Adopt the MEMORY_INFO_DATA_HOB ...................................................................... Patch Set 6: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/86949/comment/c9b4f5da_3e61adf0?us… : PS6, Line 9: of to https://review.coreboot.org/c/coreboot/+/86949/comment/085b9723_1bc435c5?us… : PS6, Line 9: Update MEMORY_INFO_DATA_HOB, child structures and their data for SMBIOS type 16/17 design change. Related changes of MEMORY_INFO_DATA_HOB are available from FSP 3103_05 onwards. Reflow to comply with coreboot line length commit style. https://review.coreboot.org/c/coreboot/+/86949/comment/fab47769_f9a4d48a?us… : PS6, Line 19: Signed-off-by: Alok Agarwal <alok.agarwal(a)intel.corp-partner.google.com> nit: Use your Intel email address. -- To view, visit https://review.coreboot.org/c/coreboot/+/86949?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1f7ee111e299ef53795912f80b444c07facde11e Gerrit-Change-Number: 86949 Gerrit-PatchSet: 6 Gerrit-Owner: Alok Agarwal <alok.agarwal(a)intel.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: srinivas.kulkarni(a)intel.com Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Alok Agarwal <alok.agarwal(a)intel.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Attention: srinivas.kulkarni(a)intel.com Gerrit-Comment-Date: Fri, 11 Apr 2025 17:04:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[M] Change in coreboot[main]: soc/amd: add functions to retrieve I3C controller info
by Felix Held (Code Review) 11 Apr '25

11 Apr '25

Attention is currently required from: Martin L Roth. Felix Held has posted comments on this change by Felix Held. ( https://review.coreboot.org/c/coreboot/+/87280?usp=email ) Change subject: soc/amd: add functions to retrieve I3C controller info ...................................................................... Patch Set 2: (1 comment) File src/soc/amd/common/block/include/amdblocks/i2c.h: PS2: i'm still undecided whether there should be a separate amdblocks/i3c.h header, since the i2c/i3c pad configuration function prototypes are in the amdblocks/i2c.h -- To view, visit https://review.coreboot.org/c/coreboot/+/87280?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib23fd896925770f49e567324bc8d12ac4c0944bd Gerrit-Change-Number: 87280 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Comment-Date: Fri, 11 Apr 2025 16:37:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[L] Change in coreboot[main]: [WIP] soc/amd: add ACPI code for I3C controller
by Felix Held (Code Review) 11 Apr '25

11 Apr '25

Attention is currently required from: Martin L Roth. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/87282?usp=email ) Change subject: [WIP] soc/amd: add ACPI code for I3C controller ...................................................................... [WIP] soc/amd: add ACPI code for I3C controller Change-Id: I309d54c81056486573c32d4da54de61b36b5c378 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/common/block/i2c/i3c.c M src/soc/amd/genoa_poc/acpi/mmio.asl M src/soc/amd/glinda/acpi/mmio.asl M src/soc/amd/mendocino/acpi/mmio.asl M src/soc/amd/phoenix/acpi/mmio.asl 5 files changed, 632 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/87282/1 diff --git a/src/soc/amd/common/block/i2c/i3c.c b/src/soc/amd/common/block/i2c/i3c.c index 9fb75d9..43eae71 100644 --- a/src/soc/amd/common/block/i2c/i3c.c +++ b/src/soc/amd/common/block/i2c/i3c.c @@ -1,6 +1,38 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <acpi/acpigen.h> +#include <amdblocks/i2c.h> +#include <console/console.h> #include <device/device.h> +#include <types.h> + +#if CONFIG(HAVE_ACPI_TABLES) +static const char *i3c_acpi_name(const struct device *dev) +{ + size_t i; + size_t num_ctrlrs; + const struct soc_i3c_ctrlr_info *ctrlr = soc_get_i3c_ctrlr_info(&num_ctrlrs); + + if (!(uintptr_t)dev->path.mmio.addr) { + printk(BIOS_ERR, "NULL MMIO address at %s\n", __func__); + return NULL; + } + + for (i = 0; i < num_ctrlrs; i++) { + if ((uintptr_t)dev->path.mmio.addr == ctrlr[i].bar) + return ctrlr[i].acpi_name; + } + printk(BIOS_ERR, "%s: Could not find %lu\n", __func__, (uintptr_t)dev->path.mmio.addr); + return NULL; +} + +static void i3c_acpi_fill_ssdt(const struct device *dev) +{ + acpigen_write_scope(acpi_device_path(dev)); + acpigen_write_store_int_to_namestr(acpi_device_status(dev), "STAT"); + acpigen_pop_len(); /* Scope */ +} +#endif static void i3c_read_resources(struct device *dev) { @@ -10,4 +42,8 @@ struct device_operations soc_amd_i3c_mmio_ops = { .read_resources = i3c_read_resources, .set_resources = noop_set_resources, +#if CONFIG(HAVE_ACPI_TABLES) + .acpi_name = i3c_acpi_name, + .acpi_fill_ssdt = i3c_acpi_fill_ssdt, +#endif }; diff --git a/src/soc/amd/genoa_poc/acpi/mmio.asl b/src/soc/amd/genoa_poc/acpi/mmio.asl index 9b5e1d2..dac18b1 100644 --- a/src/soc/amd/genoa_poc/acpi/mmio.asl +++ b/src/soc/amd/genoa_poc/acpi/mmio.asl @@ -392,6 +392,155 @@ AOAC_DEVICE(FCH_AOAC_DEV_I2C5, 0) } +Device (I3C0) { + Name (_HID, "AMDI0015") + Name (_UID, 0x0) + Method (_CRS, 0) { + Local0 = ResourceTemplate() { + Interrupt ( + ResourceConsumer, + Edge, + ActiveHigh, + Exclusive, , , IRQR) + { 0 } + Memory32Fixed (ReadWrite, APU_I3C0_BASE, 0x1000) + } + CreateDWordField (Local0, IRQR._INT, IRQN) + If (PICM) { + IRQN = II20 + } Else { + IRQN = PI20 + } + If (IRQN == 0x1f) { + Return (ResourceTemplate() { + Memory32Fixed (ReadWrite, APU_I3C0_BASE, 0x1000) + }) + } Else { + Return (Local0) + } + } + + Name (STAT, 0x0) + Method (_STA, 0x0, NotSerialized) + { + Return (STAT) + } + + AOAC_DEVICE(FCH_AOAC_DEV_I3C0, 0) +} + +Device (I3C1) { + Name (_HID, "AMDI0015") + Name (_UID, 0x1) + Method (_CRS, 0) { + Local0 = ResourceTemplate() { + Interrupt ( + ResourceConsumer, + Edge, + ActiveHigh, + Exclusive, , , IRQR) + { 0 } + Memory32Fixed (ReadWrite, APU_I3C1_BASE, 0x1000) + } + CreateDWordField (Local0, IRQR._INT, IRQN) + If (PICM) { + IRQN = II21 + } Else { + IRQN = PI21 + } + If (IRQN == 0x1f) { + Return (ResourceTemplate() { + Memory32Fixed (ReadWrite, APU_I3C1_BASE, 0x1000) + }) + } Else { + Return (Local0) + } + } + + Name (STAT, 0x0) + Method (_STA, 0x0, NotSerialized) + { + Return (STAT) + } + + AOAC_DEVICE(FCH_AOAC_DEV_I3C1, 0) +} + +Device (I3C2) { + Name (_HID, "AMDI0015") + Name (_UID, 0x2) + Method (_CRS, 0) { + Local0 = ResourceTemplate() { + Interrupt ( + ResourceConsumer, + Edge, + ActiveHigh, + Exclusive, , , IRQR) + { 0 } + Memory32Fixed (ReadWrite, APU_I3C2_BASE, 0x1000) + } + CreateDWordField (Local0, IRQR._INT, IRQN) + If (PICM) { + IRQN = II22 + } Else { + IRQN = PI22 + } + If (IRQN == 0x1f) { + Return (ResourceTemplate() { + Memory32Fixed (ReadWrite, APU_I3C2_BASE, 0x1000) + }) + } Else { + Return (Local0) + } + } + + Name (STAT, 0x0) + Method (_STA, 0x0, NotSerialized) + { + Return (STAT) + } + + AOAC_DEVICE(FCH_AOAC_DEV_I3C2, 0) +} + +Device (I3C3) +{ + Name (_HID, "AMDI0015") + Name (_UID, 0x3) + Method (_CRS, 0) { + Local0 = ResourceTemplate() { + Interrupt ( + ResourceConsumer, + Edge, + ActiveHigh, + Exclusive, , , IRQR) + { 0 } + Memory32Fixed (ReadWrite, APU_I3C3_BASE, 0x1000) + } + CreateDWordField (Local0, IRQR._INT, IRQN) + If (PICM) { + IRQN = II23 + } Else { + IRQN = PI23 + } + If (IRQN == 0x1f) { + Return (ResourceTemplate() { + Memory32Fixed (ReadWrite, APU_I3C3_BASE, 0x1000) + }) + } Else { + Return (Local0) + } + } + + Name (STAT, 0x0) + Method (_STA, 0x0, NotSerialized) + { + Return (STAT) + } + + AOAC_DEVICE(FCH_AOAC_DEV_I3C3, 0) +} + Device (MISC) { Name (_HID, "AMD0040") diff --git a/src/soc/amd/glinda/acpi/mmio.asl b/src/soc/amd/glinda/acpi/mmio.asl index 3d7b882..7416041 100644 --- a/src/soc/amd/glinda/acpi/mmio.asl +++ b/src/soc/amd/glinda/acpi/mmio.asl @@ -401,6 +401,155 @@ #endif } +Device (I3C0) { + Name (_HID, "AMDI0015") + Name (_UID, 0x0) + Method (_CRS, 0) { + Local0 = ResourceTemplate() { + Interrupt ( + ResourceConsumer, + Edge, + ActiveHigh, + Exclusive, , , IRQR) + { 0 } + Memory32Fixed (ReadWrite, APU_I3C0_BASE, 0x1000) + } + CreateDWordField (Local0, IRQR._INT, IRQN) + If (PICM) { + IRQN = II20 + } Else { + IRQN = PI20 + } + If (IRQN == 0x1f) { + Return (ResourceTemplate() { + Memory32Fixed (ReadWrite, APU_I3C0_BASE, 0x1000) + }) + } Else { + Return (Local0) + } + } + + Name (STAT, 0x0) + Method (_STA, 0x0, NotSerialized) + { + Return (STAT) + } + + AOAC_DEVICE(FCH_AOAC_DEV_I3C0, 0) +} + +Device (I3C1) { + Name (_HID, "AMDI0015") + Name (_UID, 0x1) + Method (_CRS, 0) { + Local0 = ResourceTemplate() { + Interrupt ( + ResourceConsumer, + Edge, + ActiveHigh, + Exclusive, , , IRQR) + { 0 } + Memory32Fixed (ReadWrite, APU_I3C1_BASE, 0x1000) + } + CreateDWordField (Local0, IRQR._INT, IRQN) + If (PICM) { + IRQN = II21 + } Else { + IRQN = PI21 + } + If (IRQN == 0x1f) { + Return (ResourceTemplate() { + Memory32Fixed (ReadWrite, APU_I3C1_BASE, 0x1000) + }) + } Else { + Return (Local0) + } + } + + Name (STAT, 0x0) + Method (_STA, 0x0, NotSerialized) + { + Return (STAT) + } + + AOAC_DEVICE(FCH_AOAC_DEV_I3C1, 0) +} + +Device (I3C2) { + Name (_HID, "AMDI0015") + Name (_UID, 0x2) + Method (_CRS, 0) { + Local0 = ResourceTemplate() { + Interrupt ( + ResourceConsumer, + Edge, + ActiveHigh, + Exclusive, , , IRQR) + { 0 } + Memory32Fixed (ReadWrite, APU_I3C2_BASE, 0x1000) + } + CreateDWordField (Local0, IRQR._INT, IRQN) + If (PICM) { + IRQN = II22 + } Else { + IRQN = PI22 + } + If (IRQN == 0x1f) { + Return (ResourceTemplate() { + Memory32Fixed (ReadWrite, APU_I3C2_BASE, 0x1000) + }) + } Else { + Return (Local0) + } + } + + Name (STAT, 0x0) + Method (_STA, 0x0, NotSerialized) + { + Return (STAT) + } + + AOAC_DEVICE(FCH_AOAC_DEV_I3C2, 0) +} + +Device (I3C3) +{ + Name (_HID, "AMDI0015") + Name (_UID, 0x3) + Method (_CRS, 0) { + Local0 = ResourceTemplate() { + Interrupt ( + ResourceConsumer, + Edge, + ActiveHigh, + Exclusive, , , IRQR) + { 0 } + Memory32Fixed (ReadWrite, APU_I3C3_BASE, 0x1000) + } + CreateDWordField (Local0, IRQR._INT, IRQN) + If (PICM) { + IRQN = II23 + } Else { + IRQN = PI23 + } + If (IRQN == 0x1f) { + Return (ResourceTemplate() { + Memory32Fixed (ReadWrite, APU_I3C3_BASE, 0x1000) + }) + } Else { + Return (Local0) + } + } + + Name (STAT, 0x0) + Method (_STA, 0x0, NotSerialized) + { + Return (STAT) + } + + AOAC_DEVICE(FCH_AOAC_DEV_I3C3, 0) +} + Device (MISC) { Name (_HID, "AMD0040") diff --git a/src/soc/amd/mendocino/acpi/mmio.asl b/src/soc/amd/mendocino/acpi/mmio.asl index d4459d6..9d29b2c 100644 --- a/src/soc/amd/mendocino/acpi/mmio.asl +++ b/src/soc/amd/mendocino/acpi/mmio.asl @@ -402,6 +402,155 @@ #endif } +Device (I3C0) { + Name (_HID, "AMDI0015") + Name (_UID, 0x0) + Method (_CRS, 0) { + Local0 = ResourceTemplate() { + Interrupt ( + ResourceConsumer, + Edge, + ActiveHigh, + Exclusive, , , IRQR) + { 0 } + Memory32Fixed (ReadWrite, APU_I3C0_BASE, 0x1000) + } + CreateDWordField (Local0, IRQR._INT, IRQN) + If (PICM) { + IRQN = II20 + } Else { + IRQN = PI20 + } + If (IRQN == 0x1f) { + Return (ResourceTemplate() { + Memory32Fixed (ReadWrite, APU_I3C0_BASE, 0x1000) + }) + } Else { + Return (Local0) + } + } + + Name (STAT, 0x0) + Method (_STA, 0x0, NotSerialized) + { + Return (STAT) + } + + AOAC_DEVICE(FCH_AOAC_DEV_I3C0, 0) +} + +Device (I3C1) { + Name (_HID, "AMDI0015") + Name (_UID, 0x1) + Method (_CRS, 0) { + Local0 = ResourceTemplate() { + Interrupt ( + ResourceConsumer, + Edge, + ActiveHigh, + Exclusive, , , IRQR) + { 0 } + Memory32Fixed (ReadWrite, APU_I3C1_BASE, 0x1000) + } + CreateDWordField (Local0, IRQR._INT, IRQN) + If (PICM) { + IRQN = II21 + } Else { + IRQN = PI21 + } + If (IRQN == 0x1f) { + Return (ResourceTemplate() { + Memory32Fixed (ReadWrite, APU_I3C1_BASE, 0x1000) + }) + } Else { + Return (Local0) + } + } + + Name (STAT, 0x0) + Method (_STA, 0x0, NotSerialized) + { + Return (STAT) + } + + AOAC_DEVICE(FCH_AOAC_DEV_I3C1, 0) +} + +Device (I3C2) { + Name (_HID, "AMDI0015") + Name (_UID, 0x2) + Method (_CRS, 0) { + Local0 = ResourceTemplate() { + Interrupt ( + ResourceConsumer, + Edge, + ActiveHigh, + Exclusive, , , IRQR) + { 0 } + Memory32Fixed (ReadWrite, APU_I3C2_BASE, 0x1000) + } + CreateDWordField (Local0, IRQR._INT, IRQN) + If (PICM) { + IRQN = II22 + } Else { + IRQN = PI22 + } + If (IRQN == 0x1f) { + Return (ResourceTemplate() { + Memory32Fixed (ReadWrite, APU_I3C2_BASE, 0x1000) + }) + } Else { + Return (Local0) + } + } + + Name (STAT, 0x0) + Method (_STA, 0x0, NotSerialized) + { + Return (STAT) + } + + AOAC_DEVICE(FCH_AOAC_DEV_I3C2, 0) +} + +Device (I3C3) +{ + Name (_HID, "AMDI0015") + Name (_UID, 0x3) + Method (_CRS, 0) { + Local0 = ResourceTemplate() { + Interrupt ( + ResourceConsumer, + Edge, + ActiveHigh, + Exclusive, , , IRQR) + { 0 } + Memory32Fixed (ReadWrite, APU_I3C3_BASE, 0x1000) + } + CreateDWordField (Local0, IRQR._INT, IRQN) + If (PICM) { + IRQN = II23 + } Else { + IRQN = PI23 + } + If (IRQN == 0x1f) { + Return (ResourceTemplate() { + Memory32Fixed (ReadWrite, APU_I3C3_BASE, 0x1000) + }) + } Else { + Return (Local0) + } + } + + Name (STAT, 0x0) + Method (_STA, 0x0, NotSerialized) + { + Return (STAT) + } + + AOAC_DEVICE(FCH_AOAC_DEV_I3C3, 0) +} + Device (MISC) { Name (_HID, "AMD0040") diff --git a/src/soc/amd/phoenix/acpi/mmio.asl b/src/soc/amd/phoenix/acpi/mmio.asl index b0253b5..f35cf55b 100644 --- a/src/soc/amd/phoenix/acpi/mmio.asl +++ b/src/soc/amd/phoenix/acpi/mmio.asl @@ -402,6 +402,155 @@ #endif } +Device (I3C0) { + Name (_HID, "AMDI0015") + Name (_UID, 0x0) + Method (_CRS, 0) { + Local0 = ResourceTemplate() { + Interrupt ( + ResourceConsumer, + Edge, + ActiveHigh, + Exclusive, , , IRQR) + { 0 } + Memory32Fixed (ReadWrite, APU_I3C0_BASE, 0x1000) + } + CreateDWordField (Local0, IRQR._INT, IRQN) + If (PICM) { + IRQN = II20 + } Else { + IRQN = PI20 + } + If (IRQN == 0x1f) { + Return (ResourceTemplate() { + Memory32Fixed (ReadWrite, APU_I3C0_BASE, 0x1000) + }) + } Else { + Return (Local0) + } + } + + Name (STAT, 0x0) + Method (_STA, 0x0, NotSerialized) + { + Return (STAT) + } + + AOAC_DEVICE(FCH_AOAC_DEV_I3C0, 0) +} + +Device (I3C1) { + Name (_HID, "AMDI0015") + Name (_UID, 0x1) + Method (_CRS, 0) { + Local0 = ResourceTemplate() { + Interrupt ( + ResourceConsumer, + Edge, + ActiveHigh, + Exclusive, , , IRQR) + { 0 } + Memory32Fixed (ReadWrite, APU_I3C1_BASE, 0x1000) + } + CreateDWordField (Local0, IRQR._INT, IRQN) + If (PICM) { + IRQN = II21 + } Else { + IRQN = PI21 + } + If (IRQN == 0x1f) { + Return (ResourceTemplate() { + Memory32Fixed (ReadWrite, APU_I3C1_BASE, 0x1000) + }) + } Else { + Return (Local0) + } + } + + Name (STAT, 0x0) + Method (_STA, 0x0, NotSerialized) + { + Return (STAT) + } + + AOAC_DEVICE(FCH_AOAC_DEV_I3C1, 0) +} + +Device (I3C2) { + Name (_HID, "AMDI0015") + Name (_UID, 0x2) + Method (_CRS, 0) { + Local0 = ResourceTemplate() { + Interrupt ( + ResourceConsumer, + Edge, + ActiveHigh, + Exclusive, , , IRQR) + { 0 } + Memory32Fixed (ReadWrite, APU_I3C2_BASE, 0x1000) + } + CreateDWordField (Local0, IRQR._INT, IRQN) + If (PICM) { + IRQN = II22 + } Else { + IRQN = PI22 + } + If (IRQN == 0x1f) { + Return (ResourceTemplate() { + Memory32Fixed (ReadWrite, APU_I3C2_BASE, 0x1000) + }) + } Else { + Return (Local0) + } + } + + Name (STAT, 0x0) + Method (_STA, 0x0, NotSerialized) + { + Return (STAT) + } + + AOAC_DEVICE(FCH_AOAC_DEV_I3C2, 0) +} + +Device (I3C3) +{ + Name (_HID, "AMDI0015") + Name (_UID, 0x3) + Method (_CRS, 0) { + Local0 = ResourceTemplate() { + Interrupt ( + ResourceConsumer, + Edge, + ActiveHigh, + Exclusive, , , IRQR) + { 0 } + Memory32Fixed (ReadWrite, APU_I3C3_BASE, 0x1000) + } + CreateDWordField (Local0, IRQR._INT, IRQN) + If (PICM) { + IRQN = II23 + } Else { + IRQN = PI23 + } + If (IRQN == 0x1f) { + Return (ResourceTemplate() { + Memory32Fixed (ReadWrite, APU_I3C3_BASE, 0x1000) + }) + } Else { + Return (Local0) + } + } + + Name (STAT, 0x0) + Method (_STA, 0x0, NotSerialized) + { + Return (STAT) + } + + AOAC_DEVICE(FCH_AOAC_DEV_I3C3, 0) +} + Device (MISC) { Name (_HID, "AMD0040") -- To view, visit https://review.coreboot.org/c/coreboot/+/87282?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I309d54c81056486573c32d4da54de61b36b5c378 Gerrit-Change-Number: 87282 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com>

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[XS] Change in coreboot[main]: soc/amd/*/i2c: add missing iomap.h include
by Felix Held (Code Review) 11 Apr '25

11 Apr '25

Attention is currently required from: Martin L Roth. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/87281?usp=email ) Change subject: soc/amd/*/i2c: add missing iomap.h include ...................................................................... soc/amd/*/i2c: add missing iomap.h include APU_I2C*_BASE are efined in the soc's iomap.h, so include it. Change-Id: Id7b1674914a045699d6df53b20e35028c3936f67 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/cezanne/i2c.c M src/soc/amd/genoa_poc/i2c.c M src/soc/amd/glinda/i2c.c M src/soc/amd/mendocino/i2c.c M src/soc/amd/phoenix/i2c.c 5 files changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/87281/1 diff --git a/src/soc/amd/cezanne/i2c.c b/src/soc/amd/cezanne/i2c.c index b8654ef..81aa739 100644 --- a/src/soc/amd/cezanne/i2c.c +++ b/src/soc/amd/cezanne/i2c.c @@ -3,6 +3,7 @@ #include <amdblocks/i2c.h> #include <console/console.h> #include <soc/i2c.h> +#include <soc/iomap.h> #include <soc/southbridge.h> #include <static.h> #include "chip.h" diff --git a/src/soc/amd/genoa_poc/i2c.c b/src/soc/amd/genoa_poc/i2c.c index 6436e3d..60767a9 100644 --- a/src/soc/amd/genoa_poc/i2c.c +++ b/src/soc/amd/genoa_poc/i2c.c @@ -2,6 +2,7 @@ #include <amdblocks/i2c.h> #include <soc/i2c.h> +#include <soc/iomap.h> #include <soc/southbridge.h> #include <static.h> #include "chip.h" diff --git a/src/soc/amd/glinda/i2c.c b/src/soc/amd/glinda/i2c.c index ab45ff5..aaafbc5 100644 --- a/src/soc/amd/glinda/i2c.c +++ b/src/soc/amd/glinda/i2c.c @@ -5,6 +5,7 @@ #include <amdblocks/i2c.h> #include <console/console.h> #include <soc/i2c.h> +#include <soc/iomap.h> #include <soc/southbridge.h> #include <static.h> #include "chip.h" diff --git a/src/soc/amd/mendocino/i2c.c b/src/soc/amd/mendocino/i2c.c index 92433a7..da9d3fb 100644 --- a/src/soc/amd/mendocino/i2c.c +++ b/src/soc/amd/mendocino/i2c.c @@ -3,6 +3,7 @@ #include <amdblocks/i2c.h> #include <console/console.h> #include <soc/i2c.h> +#include <soc/iomap.h> #include <soc/southbridge.h> #include <static.h> #include "chip.h" diff --git a/src/soc/amd/phoenix/i2c.c b/src/soc/amd/phoenix/i2c.c index e069c23..a2b3067 100644 --- a/src/soc/amd/phoenix/i2c.c +++ b/src/soc/amd/phoenix/i2c.c @@ -3,6 +3,7 @@ #include <amdblocks/i2c.h> #include <console/console.h> #include <soc/i2c.h> +#include <soc/iomap.h> #include <soc/southbridge.h> #include <static.h> #include "chip.h" -- To view, visit https://review.coreboot.org/c/coreboot/+/87281?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id7b1674914a045699d6df53b20e35028c3936f67 Gerrit-Change-Number: 87281 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com>

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[M] Change in coreboot[main]: soc/amd: report I3C controller MMIO to resource allocator
by Felix Held (Code Review) 11 Apr '25

11 Apr '25

Attention is currently required from: Ana Carolina Cabral, Felix Held, Martin L Roth, Maximilian Brune, Patrick Rudolph. Hello Ana Carolina Cabral, Martin L Roth, Maximilian Brune, Patrick Rudolph, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/87277?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Code-Review+2 by Maximilian Brune, Verified+1 by build bot (Jenkins) The change is no longer submittable: Code-Review and Verified are unsatisfied now. Change subject: soc/amd: report I3C controller MMIO to resource allocator ...................................................................... soc/amd: report I3C controller MMIO to resource allocator Add minimal common AMD I3C controller code that reports the MMIO region used by the different I3C controllers to the resource allocator. For this to work, select the introduced SOC_AMD_COMMON_BLOCK_I3C Kconfig option and add the 'soc_amd_i3c_mmio_ops' device operations to the I3C device devicetree entries on all SoCs that include I3C controllers. Change-Id: Iebf709d2548f2535b2a2a03a4f6da9531559c238 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/common/block/i2c/Kconfig M src/soc/amd/common/block/i2c/Makefile.mk A src/soc/amd/common/block/i2c/i3c.c M src/soc/amd/genoa_poc/Kconfig M src/soc/amd/genoa_poc/chipset.cb M src/soc/amd/glinda/Kconfig M src/soc/amd/glinda/chipset.cb M src/soc/amd/mendocino/Kconfig M src/soc/amd/mendocino/chipset_mendocino.cb M src/soc/amd/mendocino/chipset_rembrandt.cb M src/soc/amd/phoenix/Kconfig M src/soc/amd/phoenix/chipset_fsp.cb M src/soc/amd/phoenix/chipset_opensil.cb 13 files changed, 47 insertions(+), 24 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/87277/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/87277?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iebf709d2548f2535b2a2a03a4f6da9531559c238 Gerrit-Change-Number: 87277 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Ana Carolina Cabral <ana.cpmelo95(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Ana Carolina Cabral <ana.cpmelo95(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>

1 0

[M] Change in coreboot[main]: soc/amd: add functions to retrieve I3C controller info
by Felix Held (Code Review) 11 Apr '25

11 Apr '25

Attention is currently required from: Martin L Roth. Hello Martin L Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/87280?usp=email to look at the new patch set (#2). Change subject: soc/amd: add functions to retrieve I3C controller info ...................................................................... soc/amd: add functions to retrieve I3C controller info Similarly to how things are done for the I2C controller configuration, implement the 'soc_get_i3c_ctrlr_info' function in all SoCs that have I3C controllers. This function returns the contents of the SoC's 'i3c_ctrlr' array containing the base addresses and ACPI names of the I3C controllers. This function will eventually be called by the common I3C code which will be implemented in future patches. Change-Id: Ib23fd896925770f49e567324bc8d12ac4c0944bd Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/common/block/include/amdblocks/i2c.h M src/soc/amd/genoa_poc/Makefile.mk A src/soc/amd/genoa_poc/i3c.c M src/soc/amd/genoa_poc/include/soc/iomap.h M src/soc/amd/glinda/Makefile.mk A src/soc/amd/glinda/i3c.c M src/soc/amd/glinda/include/soc/iomap.h M src/soc/amd/mendocino/Makefile.mk A src/soc/amd/mendocino/i3c.c M src/soc/amd/mendocino/include/soc/iomap.h M src/soc/amd/phoenix/Makefile.mk A src/soc/amd/phoenix/i3c.c M src/soc/amd/phoenix/include/soc/iomap.h 13 files changed, 88 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/87280/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/87280?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib23fd896925770f49e567324bc8d12ac4c0944bd Gerrit-Change-Number: 87280 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com>

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