coreboot-gerrit February 2025

coreboot-gerrit@coreboot.org

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[L] Change in coreboot[main]: mb/google/nissa/var/meliks: Copy pirrha’s overridetree as initial one
by Kapil Porwal (Code Review) 19 Feb '25

19 Feb '25

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Nick Vaccaro, Paul Menzel, SH Kim, Subrata Banik. Kapil Porwal has posted comments on this change by SH Kim. ( https://review.coreboot.org/c/coreboot/+/86377?usp=email ) Change subject: mb/google/nissa/var/meliks: Copy pirrha’s overridetree as initial one ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86377?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifd6dfbeca7276dbacd72f9145ed7119566c8faef Gerrit-Change-Number: 86377 Gerrit-PatchSet: 6 Gerrit-Owner: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Thu, 20 Feb 2025 04:19:21 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[L] Change in coreboot[main]: mb/google/nissa/var/meliks: Copy pirrha’s overridetree as initial one
by Kapil Porwal (Code Review) 19 Feb '25

19 Feb '25

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Nick Vaccaro, Paul Menzel, SH Kim, Subrata Banik. Kapil Porwal has posted comments on this change by SH Kim. ( https://review.coreboot.org/c/coreboot/+/86377?usp=email ) Change subject: mb/google/nissa/var/meliks: Copy pirrha’s overridetree as initial one ...................................................................... Patch Set 6: (1 comment) File src/mainboard/google/brya/variants/meliks/overridetree.cb: https://review.coreboot.org/c/coreboot/+/86377/comment/f6fdd547_474e7e14?us… : PS5, Line 271: 200 > This value was from Bugzzy since Meliks uses the same touch screen IC as Bugzzy. […] Acknowledged -- To view, visit https://review.coreboot.org/c/coreboot/+/86377?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifd6dfbeca7276dbacd72f9145ed7119566c8faef Gerrit-Change-Number: 86377 Gerrit-PatchSet: 6 Gerrit-Owner: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Thu, 20 Feb 2025 04:18:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Comment-In-Reply-To: Kapil Porwal <kapilporwal(a)google.com>

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[S] Change in coreboot[main]: soc/intel/pantherlake: Display Sign-of-Life during memory training
by Subrata Banik (Code Review) 19 Feb '25

19 Feb '25

Attention is currently required from: Alok Agarwal, Anil Kumar K, Intel coreboot Reviewers, Jayvik Desai, Julius Werner, Jérémy Compostella, Kapil Porwal, Paul Menzel, Pranava Y N, Vikrant L Jadeja. Subrata Banik has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/85454?usp=email ) Change subject: soc/intel/pantherlake: Display Sign-of-Life during memory training ...................................................................... Patch Set 21: Code-Review+2 (1 comment) File src/soc/intel/pantherlake/romstage/fsp_params.c: https://review.coreboot.org/c/coreboot/+/85454/comment/a9bb8a97_02cd1abc?us… : PS21, Line 387: m_cfg->VgaMessage = (efi_uintn_t)ux_locales_get_text(UX_LOCALE_MSG_MEMORY_TRAINING); > Would https://review.coreboot.org/c/coreboot/+/86532 be acceptable ? I'm planning to take step approach here by implementing https://review.coreboot.org/c/coreboot/+/86509/1 and then move the SoC UX into basecode. Now we would have two kinds of UX implementation (for ADL using libgfxinit and MTL onwards using uGOP). Note, we need some special handling like https://review.coreboot.org/c/coreboot/+/86509/1/src/soc/intel/pantherlake/… to avoid overlapping text message due to low-battery w/ MRC update in pipeline At this moment, I would prefer to land the SoC changes as is and take the refactoring with upcoming CLs. let me you @julius has any concerns -- To view, visit https://review.coreboot.org/c/coreboot/+/85454?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I993eb0d59cd01fa62f35a77f84e262e389efb367 Gerrit-Change-Number: 85454 Gerrit-PatchSet: 21 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Alok Agarwal <alok.agarwal(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Attention: Alok Agarwal <alok.agarwal(a)intel.com> Gerrit-Comment-Date: Thu, 20 Feb 2025 04:02:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org>

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[S] Change in blobs[main]: soc/mediatek/mt8196: Update DRAM blob to 16174.34.0
by Jarried Lin (Code Review) 19 Feb '25

19 Feb '25

Jarried Lin has uploaded this change for review. ( https://review.coreboot.org/c/blobs/+/86534?usp=email ) Change subject: soc/mediatek/mt8196: Update DRAM blob to 16174.34.0 ...................................................................... soc/mediatek/mt8196: Update DRAM blob to 16174.34.0 Update dram.elf includes: - Add EMI clock pre setting and post setting. BRANCH=rauru BUG=b:378592077 TEST=Build pass, Bootup pass. Change-Id: I08d6fb61d8ceec56e3d5b8db5da1ac47291eeb85 Signed-off-by: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com> --- M soc/mediatek/mt8196/dram.elf M soc/mediatek/mt8196/dram.elf.md5 M soc/mediatek/mt8196/dram_release_notes.txt 3 files changed, 9 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/blobs refs/changes/34/86534/1 diff --git a/soc/mediatek/mt8196/dram.elf b/soc/mediatek/mt8196/dram.elf index a39b8f9..cd3dc83 100644 --- a/soc/mediatek/mt8196/dram.elf +++ b/soc/mediatek/mt8196/dram.elf Binary files differ diff --git a/soc/mediatek/mt8196/dram.elf.md5 b/soc/mediatek/mt8196/dram.elf.md5 index c62a77b..aa78653 100644 --- a/soc/mediatek/mt8196/dram.elf.md5 +++ b/soc/mediatek/mt8196/dram.elf.md5 @@ -1 +1 @@ -eb5a6b2b584df19a461297b35ca69b1a *dram.elf +ee9a89634430162b3d10e1a16f191bc7 *dram.elf diff --git a/soc/mediatek/mt8196/dram_release_notes.txt b/soc/mediatek/mt8196/dram_release_notes.txt index 9cb9afb..ec16e64 100644 --- a/soc/mediatek/mt8196/dram_release_notes.txt +++ b/soc/mediatek/mt8196/dram_release_notes.txt @@ -12,3 +12,11 @@ - CL:*7518650 mt8196: SLC: Port SLC driver - CL:*7842174 mtk-dramk/mt8196: Sync to MediaTek's preloader version 20241121 + +# 16174.34.0 + +1. An official build from ChromeOS version 16174.34.0. + +2. Included changes: + +- CL:*8030082 mt8196: EMI: Add EMI clock pre setting and post setting -- To view, visit https://review.coreboot.org/c/blobs/+/86534?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: blobs Gerrit-Branch: main Gerrit-Change-Id: I08d6fb61d8ceec56e3d5b8db5da1ac47291eeb85 Gerrit-Change-Number: 86534 Gerrit-PatchSet: 1 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com>

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[S] Change in coreboot[main]: soc/mediatek/mt8196: Adjust and save HW protect temperature to SRAM
by Jarried Lin (Code Review) 19 Feb '25

19 Feb '25

Attention is currently required from: Hung-Te Lin, Yidi Lin, Yu-Ping Wu. Hello Hung-Te Lin, Yidi Lin, Yu-Ping Wu, Zhaoqing Jiu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86533?usp=email to look at the new patch set (#2). Change subject: soc/mediatek/mt8196: Adjust and save HW protect temperature to SRAM ...................................................................... soc/mediatek/mt8196: Adjust and save HW protect temperature to SRAM Adjust thermal HW protect temperature and save HW protect temperature to SRAM. BRANCH=rauru BUG=b:389026545 TEST=Boot up and check temperature in coreboot log: [INFO ] [LVTS_MSR] ts0 msr_all=141d0, msr_temp=16848, temp=41086 [INFO ] lvts_tscpu_thermal_read_tc_temp order 0 ts_name 0 temp 41086 rg_temp 41073(42059) [INFO ] [LVTS_MSR] ts1 msr_all=141e3, msr_temp=16867, temp=41540 [INFO ] lvts_tscpu_thermal_read_tc_temp order 1 ts_name 1 temp 41540 rg_temp 41526(42523) [INFO ] [LVTS_MSR] ts2 msr_all=14199, msr_temp=16793, temp=39772[0m [INFO ] lvts_tscpu_thermal_read_tc_temp order 2 ts_name 2 temp 39772 rg_temp 39760(40715) [INFO ] [LVTS_MSR] ts3 msr_all=141c2, msr_temp=16834, temp=40751 [INFO ] lvts_tscpu_thermal_read_tc_temp order 3 ts_name 3 temp 40751 rg_temp 40739(41717) [INFO ] [LVTS_MSR] ts4 msr_all=141d0, msr_temp=16848, temp=41086 [INFO ] lvts_tscpu_thermal_read_tc_temp order 0 ts_name 4 temp 41086 rg_temp 41073(42059) [INFO ] [LVTS_MSR] ts5 msr_all=141b3, msr_temp=16819, temp=40393 [INFO ] lvts_tscpu_thermal_read_tc_temp order 1 ts_name 5 temp 40393 rg_temp 40380(41350) [INFO ] [LVTS_MSR] ts6 msr_all=14194, msr_temp=16788, temp=39652 [INFO ] lvts_tscpu_thermal_read_tc_temp order 2 ts_name 6 temp 39652 rg_temp 39641(40593) [INFO ] [LVTS_MSR] ts7 msr_all=14186, msr_temp=16774, temp=39318 [INFO ] lvts_tscpu_thermal_read_tc_temp order 3 ts_name 7 temp 39318 rg_temp 39307(40251) Signed-off-by: Zhaoqing Jiu <zhaoqing.jiu(a)mediatek.corp-partner.google.com> Change-Id: Ied0a7e710e77a4e74372590374f9342c5edc9122 --- M src/soc/mediatek/mt8196/include/soc/thermal.h M src/soc/mediatek/mt8196/include/soc/thermal_internal.h M src/soc/mediatek/mt8196/thermal.c M src/soc/mediatek/mt8196/thermal_sram.c 4 files changed, 36 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/86533/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86533?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ied0a7e710e77a4e74372590374f9342c5edc9122 Gerrit-Change-Number: 86533 Gerrit-PatchSet: 2 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-CC: Zhaoqing Jiu <zhaoqing.jiu(a)mediatek.corp-partner.google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com>

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[S] Change in coreboot[main]: soc/mediatek/mt8196: Adjust and save HW protect temperature to SRAM
by Jarried Lin (Code Review) 19 Feb '25

19 Feb '25

Attention is currently required from: Zhaoqing Jiu. Hello Zhaoqing Jiu, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/86533?usp=email to review the following change. Change subject: soc/mediatek/mt8196: Adjust and save HW protect temperature to SRAM ...................................................................... soc/mediatek/mt8196: Adjust and save HW protect temperature to SRAM 1. Adjust thermal HW protect temperature. 2. Save HW protect temperature to sram. BRANCH=rauru BUG=b:389026545 TEST=Boot up and check temperature in coreboot log: [INFO ] [LVTS_MSR] ts0 msr_all=141d0, msr_temp=16848, temp=41086 [INFO ] lvts_tscpu_thermal_read_tc_temp order 0 ts_name 0 temp 41086 rg_temp 41073(42059) [INFO ] [LVTS_MSR] ts1 msr_all=141e3, msr_temp=16867, temp=41540 [INFO ] lvts_tscpu_thermal_read_tc_temp order 1 ts_name 1 temp 41540 rg_temp 41526(42523) [INFO ] [LVTS_MSR] ts2 msr_all=14199, msr_temp=16793, temp=39772[0m [INFO ] lvts_tscpu_thermal_read_tc_temp order 2 ts_name 2 temp 39772 rg_temp 39760(40715) [INFO ] [LVTS_MSR] ts3 msr_all=141c2, msr_temp=16834, temp=40751 [INFO ] lvts_tscpu_thermal_read_tc_temp order 3 ts_name 3 temp 40751 rg_temp 40739(41717) [INFO ] [LVTS_MSR] ts4 msr_all=141d0, msr_temp=16848, temp=41086 [INFO ] lvts_tscpu_thermal_read_tc_temp order 0 ts_name 4 temp 41086 rg_temp 41073(42059) [INFO ] [LVTS_MSR] ts5 msr_all=141b3, msr_temp=16819, temp=40393 [INFO ] lvts_tscpu_thermal_read_tc_temp order 1 ts_name 5 temp 40393 rg_temp 40380(41350) [INFO ] [LVTS_MSR] ts6 msr_all=14194, msr_temp=16788, temp=39652 [INFO ] lvts_tscpu_thermal_read_tc_temp order 2 ts_name 6 temp 39652 rg_temp 39641(40593) [INFO ] [LVTS_MSR] ts7 msr_all=14186, msr_temp=16774, temp=39318 [INFO ] lvts_tscpu_thermal_read_tc_temp order 3 ts_name 7 temp 39318 rg_temp 39307(40251) Signed-off-by: Zhaoqing Jiu <zhaoqing.jiu(a)mediatek.corp-partner.google.com> Change-Id: Ied0a7e710e77a4e74372590374f9342c5edc9122 --- M src/soc/mediatek/mt8196/include/soc/thermal.h M src/soc/mediatek/mt8196/include/soc/thermal_internal.h M src/soc/mediatek/mt8196/thermal.c M src/soc/mediatek/mt8196/thermal_sram.c 4 files changed, 36 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/86533/1 diff --git a/src/soc/mediatek/mt8196/include/soc/thermal.h b/src/soc/mediatek/mt8196/include/soc/thermal.h index 6d2b523..b47e75f 100644 --- a/src/soc/mediatek/mt8196/include/soc/thermal.h +++ b/src/soc/mediatek/mt8196/include/soc/thermal.h @@ -5,5 +5,7 @@ void thermal_sram_init(void); void thermal_init(void); +void thermal_write_reboot_temp_sram(int); +void thermal_write_reboot_msr_sram(int, int); #endif /* SOC_MEDIATEK_MT8196_THERMAL_H */ diff --git a/src/soc/mediatek/mt8196/include/soc/thermal_internal.h b/src/soc/mediatek/mt8196/include/soc/thermal_internal.h index b584117..55c300d 100644 --- a/src/soc/mediatek/mt8196/include/soc/thermal_internal.h +++ b/src/soc/mediatek/mt8196/include/soc/thermal_internal.h @@ -171,8 +171,8 @@ #define AP_RST_SET (INFRACFG_AO_SEC_BASE + 0xf30) #define AP_RST_CLR (INFRACFG_AO_SEC_BASE + 0xf34) -#define LVTS_COF_T_SLP_GLD 358830 -#define LVTS_COF_COUNT_R_GLD 34389 +#define LVTS_COF_T_SLP_GLD 391460 +#define LVTS_COF_COUNT_R_GLD 34412 #define LVTS_COF_T_CONST_OFS 0 #define DEFAULT_EFUSE_GOLDEN_TEMP 60 diff --git a/src/soc/mediatek/mt8196/thermal.c b/src/soc/mediatek/mt8196/thermal.c index 001cd06..be7fece 100644 --- a/src/soc/mediatek/mt8196/thermal.c +++ b/src/soc/mediatek/mt8196/thermal.c @@ -575,12 +575,14 @@ write32p(AP_RST_CLR, BIT(11)); } -static void lvts_set_tc_trigger_hw_protect(const struct lvts_thermal_controller *tc) +static void lvts_set_tc_trigger_hw_protect(unsigned int tc_num) { int d_index, i; uint32_t raw_high; uint16_t raw; enum lvts_sensor ts_name; + int tc_index = 0xFF; + const struct lvts_thermal_controller *tc = &lvts_tscpu_g_tc[tc_num]; if (tc->dominator_ts_idx < tc->ts_number) { d_index = tc->dominator_ts_idx; @@ -601,6 +603,16 @@ raw = lvts_temp_to_raw(tc->reboot_temperature, ts_name); raw_high = MAX(raw_high, raw); } + if (tc_num == LVTS_AP_CONTROLLER0) + tc_index = 0; + else if (tc_num == LVTS_AP_CONTROLLER1) + tc_index = 1; + + if (tc_index != 0xff) { + thermal_write_reboot_msr_sram(tc_index, raw_high); + if (tc_index == 0) + thermal_write_reboot_temp_sram(tc->reboot_temperature); + } setbits32(&tc->regs->lvtsprotctl_0, 0x3FFF); /* disable trigger SPM interrupt */ @@ -623,11 +635,10 @@ printk(BIOS_INFO, "===== %s begin ======\n", __func__); for (i = 0; i < ARRAY_SIZE(lvts_tscpu_g_tc); i++) { - const struct lvts_thermal_controller *tc = &lvts_tscpu_g_tc[i]; - if (tc->ctrl_on_off == CTRL_OFF) + if ((&lvts_tscpu_g_tc[i])->ctrl_on_off == CTRL_OFF) continue; - lvts_set_tc_trigger_hw_protect(tc); + lvts_set_tc_trigger_hw_protect(i); } } diff --git a/src/soc/mediatek/mt8196/thermal_sram.c b/src/soc/mediatek/mt8196/thermal_sram.c index 5509792..23500cb 100644 --- a/src/soc/mediatek/mt8196/thermal_sram.c +++ b/src/soc/mediatek/mt8196/thermal_sram.c @@ -7,6 +7,9 @@ /* SRAM for Thermal */ #define THERMAL_SRAM_BASE (_mcufw_reserved + 0x1000) #define THERMAL_SRAM_LEN 0x400 +#define THERMAL_REBOOT_TEMP_SRAM_OFFSET 0x39c +#define THERMAL_REBOOT_MSR_SRAM_OFFSET 0x340 +#define THERMAL_REBOOT_MSR_SRAM_LEN (6 * 4) static void thermal_cls_sram(void) { @@ -59,3 +62,17 @@ thermal_stat_cls_sram(); thermal_gpu_stat_cls_sram(); } + +void thermal_write_reboot_temp_sram(int value) +{ + write32(THERMAL_SRAM_BASE + THERMAL_REBOOT_TEMP_SRAM_OFFSET, value); +} + +void thermal_write_reboot_msr_sram(int idx, int value) +{ + unsigned int offset = 0; + if ((idx * 4) < THERMAL_REBOOT_MSR_SRAM_LEN) { + offset = THERMAL_REBOOT_MSR_SRAM_OFFSET + idx * 4; + write32(THERMAL_SRAM_BASE + offset, value); + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/86533?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ied0a7e710e77a4e74372590374f9342c5edc9122 Gerrit-Change-Number: 86533 Gerrit-PatchSet: 1 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Zhaoqing Jiu <zhaoqing.jiu(a)mediatek.corp-partner.google.com> Gerrit-Attention: Zhaoqing Jiu <zhaoqing.jiu(a)mediatek.corp-partner.google.com>

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[XS] Change in coreboot[main]: soc/intel/common/gpio: Add macro for interrupt GPI with driver mode
by Kyoung Il Kim (Code Review) 19 Feb '25

19 Feb '25

Attention is currently required from: Intel coreboot Reviewers, Kyoung Il Kim. Kyoung Il Kim has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/86414?usp=email ) Change subject: soc/intel/common/gpio: Add macro for interrupt GPI with driver mode ...................................................................... Patch Set 3: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/86414?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibc1ed3089c24302bc7eb02318714b8ec464fad01 Gerrit-Change-Number: 86414 Gerrit-PatchSet: 3 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Kyoung Il Kim <kyoung.il.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Kyoung Il Kim <kyoung.il.kim(a)intel.com> Gerrit-Comment-Date: Thu, 20 Feb 2025 01:27:59 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: mb/google/skyrim/var/frostflow: Set SYSTEM_TYPE_CONVERTIBLE
by Felix Singer (Code Review) 19 Feb '25

19 Feb '25

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86468?usp=email ) Change subject: mb/google/skyrim/var/frostflow: Set SYSTEM_TYPE_CONVERTIBLE ...................................................................... mb/google/skyrim/var/frostflow: Set SYSTEM_TYPE_CONVERTIBLE Frostflow is a 2-in-1 device, this sets the SMBIOS enclosure type properly. Change-Id: I6c3306270cbc80bb55fb536a1fc51a5546287649 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86468 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> --- M src/mainboard/google/skyrim/Kconfig 1 file changed, 2 insertions(+), 1 deletion(-) Approvals: Felix Singer: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/google/skyrim/Kconfig b/src/mainboard/google/skyrim/Kconfig index dc28fbc..756db5f 100644 --- a/src/mainboard/google/skyrim/Kconfig +++ b/src/mainboard/google/skyrim/Kconfig @@ -11,6 +11,7 @@ select DRIVERS_GENESYSLOGIC_GL9755 select FEATURE_TABLET_MODE_DPTC select SOC_AMD_COMMON_BLOCK_ACPI_DPTC + select SYSTEM_TYPE_CONVERTIBLE config BOARD_GOOGLE_MARKARTH select BOARD_GOOGLE_BASEBOARD_SKYRIM @@ -67,7 +68,7 @@ select SOC_AMD_COMMON_BLOCK_I2C3_TPM_SHARED_WITH_PSP select SOC_AMD_COMMON_BLOCK_USE_ESPI select SOC_AMD_GFX_CACHE_VBIOS_IN_FMAP if CHROMEOS && RUN_FSP_GOP - select SYSTEM_TYPE_LAPTOP + select SYSTEM_TYPE_LAPTOP if !SYSTEM_TYPE_CONVERTIBLE select TPM_GOOGLE_TI50 config DEVICETREE -- To view, visit https://review.coreboot.org/c/coreboot/+/86468?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6c3306270cbc80bb55fb536a1fc51a5546287649 Gerrit-Change-Number: 86468 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: mb/google/glados/var/cave: Set SYSTEM_TYPE_CONVERTIBLE
by Felix Singer (Code Review) 19 Feb '25

19 Feb '25

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86467?usp=email ) Change subject: mb/google/glados/var/cave: Set SYSTEM_TYPE_CONVERTIBLE ...................................................................... mb/google/glados/var/cave: Set SYSTEM_TYPE_CONVERTIBLE Cave is a 2-in-1 device, this sets the SMBIOS enclosure type properly. Change-Id: I8f2ec82c97676aa315c18286b5e2eb94d46004ec Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86467 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Reviewed-by: Andy Ebrahiem <ahmet.ebrahiem(a)9elements.com> --- M src/mainboard/google/glados/Kconfig 1 file changed, 2 insertions(+), 1 deletion(-) Approvals: Felix Singer: Looks good to me, approved build bot (Jenkins): Verified Andy Ebrahiem: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/glados/Kconfig b/src/mainboard/google/glados/Kconfig index 57d54d0..287d9383 100644 --- a/src/mainboard/google/glados/Kconfig +++ b/src/mainboard/google/glados/Kconfig @@ -20,7 +20,7 @@ select MEMORY_MAPPED_TPM select MAINBOARD_HAS_TPM1 select SOC_INTEL_SKYLAKE - select SYSTEM_TYPE_LAPTOP + select SYSTEM_TYPE_LAPTOP if !SYSTEM_TYPE_CONVERTIBLE config BOARD_GOOGLE_ASUKA select BOARD_GOOGLE_BASEBOARD_GLADOS @@ -43,6 +43,7 @@ select INTEL_GMA_HAVE_VBT select MAINBOARD_NO_FSP_GOP select NHLT_MAX98357 if INCLUDE_NHLT_BLOBS + select SYSTEM_TYPE_CONVERTIBLE config BOARD_GOOGLE_CHELL select BOARD_GOOGLE_BASEBOARD_GLADOS -- To view, visit https://review.coreboot.org/c/coreboot/+/86467?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8f2ec82c97676aa315c18286b5e2eb94d46004ec Gerrit-Change-Number: 86467 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Andy Ebrahiem <ahmet.ebrahiem(a)9elements.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: mb/google/rambi: Set system type for ninja/sumo variants
by Felix Singer (Code Review) 19 Feb '25

19 Feb '25

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86462?usp=email ) Change subject: mb/google/rambi: Set system type for ninja/sumo variants ...................................................................... mb/google/rambi: Set system type for ninja/sumo variants Set these to minipc and all-in-one respectively now that these system types exist, so that the SMBIOS enclosure type is correctly set vs defaulting to desktop. Change-Id: I661401dcd7fe348a07e34ace309c0a8b7e0f00eb Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86462 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> --- M src/mainboard/google/rambi/Kconfig 1 file changed, 2 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Felix Singer: Looks good to me, approved diff --git a/src/mainboard/google/rambi/Kconfig b/src/mainboard/google/rambi/Kconfig index 65339e0..750eba1 100644 --- a/src/mainboard/google/rambi/Kconfig +++ b/src/mainboard/google/rambi/Kconfig @@ -63,6 +63,7 @@ config BOARD_GOOGLE_NINJA select BOARD_GOOGLE_BASEBOARD_RAMBI select INTEL_GMA_HAVE_VBT + select SYSTEM_TYPE_MINIPC config BOARD_GOOGLE_ORCO select BOARD_GOOGLE_BASEBOARD_RAMBI @@ -86,6 +87,7 @@ config BOARD_GOOGLE_SUMO select BOARD_GOOGLE_BASEBOARD_RAMBI select INTEL_GMA_HAVE_VBT + select SYSTEM_TYPE_ALL_IN_ONE config BOARD_GOOGLE_SWANKY select BOARD_GOOGLE_BASEBOARD_RAMBI -- To view, visit https://review.coreboot.org/c/coreboot/+/86462?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I661401dcd7fe348a07e34ace309c0a8b7e0f00eb Gerrit-Change-Number: 86462 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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