coreboot-gerrit February 2025

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[main]: mb/google/nissa/var/dirks: Update ddi_ports_config
by Eric Lai (Code Review) 20 Feb '25

20 Feb '25

Attention is currently required from: David Wu, Dinesh Gehlot, Ivy Jian, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik. Eric Lai has posted comments on this change by Ivy Jian. ( https://review.coreboot.org/c/coreboot/+/86537?usp=email ) Change subject: mb/google/nissa/var/dirks: Update ddi_ports_config ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86537?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I67e9fcf4a3caa303ec8d873507a7533389c095ae Gerrit-Change-Number: 86537 Gerrit-PatchSet: 1 Gerrit-Owner: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Thu, 20 Feb 2025 08:37:33 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: arch/x86/acpi_bert: Add spinlock
by Patrick Rudolph (Code Review) 20 Feb '25

20 Feb '25

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86539?usp=email ) Change subject: arch/x86/acpi_bert: Add spinlock ...................................................................... arch/x86/acpi_bert: Add spinlock The code may be called in parallel from MPinit. Add a spinlock to protect critical functions allocating and checking if enough space is available. Prevents using the same region for multiple entries and prevents overallocation and possibly corrupting CBMEM. TEST: Booted on amd/birman+ generating ACPI BERT tables. Change-Id: Iab484149ef00797e1846441fb93407fe05ac8abb Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/arch/x86/acpi_bert_storage.c 1 file changed, 23 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/86539/1 diff --git a/src/arch/x86/acpi_bert_storage.c b/src/arch/x86/acpi_bert_storage.c index 62c0441..ce45984 100644 --- a/src/arch/x86/acpi_bert_storage.c +++ b/src/arch/x86/acpi_bert_storage.c @@ -9,6 +9,7 @@ #include <acpi/acpi.h> #include <arch/bert_storage.h> #include <string.h> +#include <smp/spinlock.h> #include <types.h> /* BERT region management: Allow the chipset to determine the specific @@ -26,12 +27,20 @@ static size_t bert_region_size; static size_t bert_region_used; +DECLARE_SPIN_LOCK(acpi_bert_lock) + /* Calculate the remaining space in the BERT region. This knowledge may help * the caller prioritize the information to store. */ size_t bert_storage_remaining(void) { - return bert_region_broken ? 0 : bert_region_size - bert_region_used; + size_t ret; + + spin_lock(&acpi_bert_lock); + ret = bert_region_broken ? 0 : bert_region_size - bert_region_used; + spin_unlock(&acpi_bert_lock); + + return ret; } bool bert_errors_present(void) @@ -48,23 +57,33 @@ } /* No metadata, etc. with our region, so this is easy */ + spin_lock(&acpi_bert_lock); *start = bert_region_base; *size = bert_region_used; + spin_unlock(&acpi_bert_lock); } static void *bert_allocate_storage(size_t size) { size_t alloc; + void *ret = NULL; + + spin_lock(&acpi_bert_lock); if (bert_region_broken) - return NULL; + goto out; if (bert_region_used + size > bert_region_size) - return NULL; + goto out; alloc = bert_region_used; bert_region_used += size; - return (void *)((u8 *)bert_region_base + alloc); + ret = (void *)((u8 *)bert_region_base + alloc); + +out: + spin_unlock(&acpi_bert_lock); + + return ret; } /* Generic Error Status: Each Status represents a unique error event within -- To view, visit https://review.coreboot.org/c/coreboot/+/86539?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iab484149ef00797e1846441fb93407fe05ac8abb Gerrit-Change-Number: 86539 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com>

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[L] Change in coreboot[main]: soc/mediatek/mt8189: Add GPIO driver
by Vince Liu (Code Review) 19 Feb '25

19 Feb '25

Vince Liu has posted comments on this change by Vince Liu. ( https://review.coreboot.org/c/coreboot/+/85667?usp=email ) Change subject: soc/mediatek/mt8189: Add GPIO driver ...................................................................... Patch Set 2: (1 comment) File src/soc/mediatek/mt8189/gpio.c: https://review.coreboot.org/c/coreboot/+/85667/comment/96903a31_9fb298a2?us… : PS2, Line 264: if (raw_id >= ARRAY_SIZE(gpio_driving_info)) > Vince, could you upload another patch similar to CB:74063 to reduce the bootblock size? Updated in https://review.coreboot.org/c/coreboot/+/86538 -- To view, visit https://review.coreboot.org/c/coreboot/+/85667?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia87fe0975add95fcfad16d55586559c7f912a624 Gerrit-Change-Number: 85667 Gerrit-PatchSet: 2 Gerrit-Owner: Vince Liu <vince-wl.liu(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Thu, 20 Feb 2025 07:56:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com>

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[S] Change in coreboot[main]: soc/mediatek/mt8189: Reduce bootblock size by separating SPI NOR GPIOs
by Vince Liu (Code Review) 19 Feb '25

19 Feb '25

Attention is currently required from: Hung-Te Lin, Yidi Lin. Vince Liu has posted comments on this change by Vince Liu. ( https://review.coreboot.org/c/coreboot/+/86538?usp=email ) Change subject: soc/mediatek/mt8189: Reduce bootblock size by separating SPI NOR GPIOs ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/86538/comment/8b4f9014_9d3a68dd?us… : PS1, Line 10: To optimize the code size, separate the SPI NOR GPIO driving information. > line too long Done -- To view, visit https://review.coreboot.org/c/coreboot/+/86538?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If7e8e5c7db59b5f181db14f6e66df2f333dbb6d4 Gerrit-Change-Number: 86538 Gerrit-PatchSet: 2 Gerrit-Owner: Vince Liu <vince-wl.liu(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Thu, 20 Feb 2025 07:53:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com>

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[S] Change in coreboot[main]: soc/mediatek/mt8189: Reduce bootblock size by separating SPI NOR GPIOs
by Vince Liu (Code Review) 19 Feb '25

19 Feb '25

Attention is currently required from: Hung-Te Lin, Vince Liu, Yidi Lin. Hello Hung-Te Lin, Yidi Lin, Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86538?usp=email to look at the new patch set (#2). Change subject: soc/mediatek/mt8189: Reduce bootblock size by separating SPI NOR GPIOs ...................................................................... soc/mediatek/mt8189: Reduce bootblock size by separating SPI NOR GPIOs In the bootblock stage, only SPI NOR related GPIOs are used. To optimize the code size, separate the SPI NOR GPIO driving information. This modification reduces the bootblock code size by 1KB. BUG=b:379008996 BRANCH=none TEST=booted successfully Signed-off-by: Vince Liu <vince-wl.liu(a)mediatek.corp-partner.google.com> Change-Id: If7e8e5c7db59b5f181db14f6e66df2f333dbb6d4 --- M src/soc/mediatek/mt8189/gpio.c 1 file changed, 37 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/86538/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86538?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If7e8e5c7db59b5f181db14f6e66df2f333dbb6d4 Gerrit-Change-Number: 86538 Gerrit-PatchSet: 2 Gerrit-Owner: Vince Liu <vince-wl.liu(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Vince Liu <vince-wl.liu(a)mediatek.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com>

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[XS] Change in blobs[main]: soc/mediatek/mt8196: Update MCUPM firmware to v1.2
by Yu-Ping Wu (Code Review) 19 Feb '25

19 Feb '25

Attention is currently required from: Jarried Lin, Yidi Lin, agogo. Yu-Ping Wu has posted comments on this change by agogo. ( https://review.coreboot.org/c/blobs/+/86511?usp=email ) Change subject: soc/mediatek/mt8196: Update MCUPM firmware to v1.2 ...................................................................... Patch Set 3: Verified+1 -- To view, visit https://review.coreboot.org/c/blobs/+/86511?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: blobs Gerrit-Branch: main Gerrit-Change-Id: I81e745a7290c31fe15240102df0a78dfaadf54e7 Gerrit-Change-Number: 86511 Gerrit-PatchSet: 3 Gerrit-Owner: agogo <agogo.huang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: agogo <agogo.huang(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Thu, 20 Feb 2025 07:50:33 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in blobs[main]: soc/mediatek/mt8196: Update MCUPM firmware to v1.2
by Yu-Ping Wu (Code Review) 19 Feb '25

19 Feb '25

Attention is currently required from: Jarried Lin, Yidi Lin, agogo. Yu-Ping Wu has posted comments on this change by agogo. ( https://review.coreboot.org/c/blobs/+/86511?usp=email ) Change subject: soc/mediatek/mt8196: Update MCUPM firmware to v1.2 ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/blobs/+/86511?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: blobs Gerrit-Branch: main Gerrit-Change-Id: I81e745a7290c31fe15240102df0a78dfaadf54e7 Gerrit-Change-Number: 86511 Gerrit-PatchSet: 3 Gerrit-Owner: agogo <agogo.huang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: agogo <agogo.huang(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Thu, 20 Feb 2025 07:50:30 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: soc/mediatek/mt8189: Reduce bootblock size by separating SPI NOR GPIOs
by Yu-Ping Wu (Code Review) 19 Feb '25

19 Feb '25

Attention is currently required from: Hung-Te Lin, Vince Liu, Yidi Lin. Yu-Ping Wu has posted comments on this change by Vince Liu. ( https://review.coreboot.org/c/coreboot/+/86538?usp=email ) Change subject: soc/mediatek/mt8189: Reduce bootblock size by separating SPI NOR GPIOs ...................................................................... Patch Set 1: Code-Review+2 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/86538/comment/a59b8f7f_3b562fc6?us… : PS1, Line 10: To optimize the code size, separate the SPI NOR GPIO driving information. line too long -- To view, visit https://review.coreboot.org/c/coreboot/+/86538?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If7e8e5c7db59b5f181db14f6e66df2f333dbb6d4 Gerrit-Change-Number: 86538 Gerrit-PatchSet: 1 Gerrit-Owner: Vince Liu <vince-wl.liu(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Vince Liu <vince-wl.liu(a)mediatek.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Thu, 20 Feb 2025 07:49:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[XS] Change in blobs[main]: soc/mediatek/mt8196: Update MCUPM firmware to v1.2
by agogo (Code Review) 19 Feb '25

19 Feb '25

Attention is currently required from: Jarried Lin, Yidi Lin, Yu-Ping Wu. agogo has posted comments on this change by agogo. ( https://review.coreboot.org/c/blobs/+/86511?usp=email ) Change subject: soc/mediatek/mt8196: Update MCUPM firmware to v1.2 ...................................................................... Patch Set 3: (5 comments) Commit Message: https://review.coreboot.org/c/blobs/+/86511/comment/04771c56_5d06b05e?usp=e… : PS1, Line 9: Update coef for mcu-lvts reboot temp setting. > Please update the commit message Done https://review.coreboot.org/c/blobs/+/86511/comment/2e778a64_13dd9b0d?usp=e… : PS1, Line 11: TEST=NA : BUG=b:317009620 > BRANCH=rauru Done File soc/mediatek/mt8196/mcupm_release_notes.txt: https://review.coreboot.org/c/blobs/+/86511/comment/5100dbdf_17e92855?usp=e… : PS1, Line 12: coef > coefficient Done https://review.coreboot.org/c/blobs/+/86511/comment/0d905cf9_4f7a8760?usp=e… : PS1, Line 12: mcu-lvts > MCU-LVTS Done https://review.coreboot.org/c/blobs/+/86511/comment/5885f4e9_dacfb7a8?usp=e… : PS1, Line 12: temp > temperature Done -- To view, visit https://review.coreboot.org/c/blobs/+/86511?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: blobs Gerrit-Branch: main Gerrit-Change-Id: I81e745a7290c31fe15240102df0a78dfaadf54e7 Gerrit-Change-Number: 86511 Gerrit-PatchSet: 3 Gerrit-Owner: agogo <agogo.huang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Thu, 20 Feb 2025 07:49:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com>

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[S] Change in coreboot[main]: soc/mediatek/mt8189: Reduce bootblock size by separating SPI NOR GPIOs
by Vince Liu (Code Review) 19 Feb '25

19 Feb '25

Vince Liu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86538?usp=email ) Change subject: soc/mediatek/mt8189: Reduce bootblock size by separating SPI NOR GPIOs ...................................................................... soc/mediatek/mt8189: Reduce bootblock size by separating SPI NOR GPIOs In the bootblock stage, only SPI NOR related GPIOs are used. To optimize the code size, separate the SPI NOR GPIO driving information. This modification reduces the bootblock code size by 1KB. BUG=b:379008996 BRANCH=none TEST=booted successfully Signed-off-by: Vince Liu <vince-wl.liu(a)mediatek.corp-partner.google.com> Change-Id: If7e8e5c7db59b5f181db14f6e66df2f333dbb6d4 --- M src/soc/mediatek/mt8189/gpio.c 1 file changed, 37 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/86538/1 diff --git a/src/soc/mediatek/mt8189/gpio.c b/src/soc/mediatek/mt8189/gpio.c index 27179c3..dde8d14 100644 --- a/src/soc/mediatek/mt8189/gpio.c +++ b/src/soc/mediatek/mt8189/gpio.c @@ -8,6 +8,26 @@ #include <device/mmio.h> #include <gpio.h> +#define SPI_NOR_GPIO_BASE 150 + +enum { + SPI_NOR_CK = 0, + SPI_NOR_CS = 1, + SPI_NOR_IO0 = 2, + SPI_NOR_IO1 = 3, + SPI_NOR_IO2 = 4, + SPI_NOR_IO3 = 5, +}; + +static const struct gpio_drv_info bootblock_gpio_driving_info[] = { + [SPI_NOR_CK] = { 0x10, 12, 3, }, + [SPI_NOR_CS] = { 0x10, 27, 3, }, + [SPI_NOR_IO0] = { 0x10, 15, 3, }, + [SPI_NOR_IO1] = { 0x10, 18, 3, }, + [SPI_NOR_IO2] = { 0x10, 21, 3, }, + [SPI_NOR_IO3] = { 0x10, 24, 3, }, +}; + static const struct gpio_drv_info gpio_driving_info[] = { [0] = { 0x10, 15, 3, }, [1] = { 0x10, 9, 3, }, @@ -261,14 +281,26 @@ const struct gpio_drv_info *get_gpio_driving_info(uint32_t raw_id) { - if (raw_id >= ARRAY_SIZE(gpio_driving_info)) - return NULL; - return &gpio_driving_info[raw_id]; + if (ENV_BOOTBLOCK) { + uint32_t id = raw_id - SPI_NOR_GPIO_BASE; + + if (id >= ARRAY_SIZE(bootblock_gpio_driving_info)) + return NULL; + return &bootblock_gpio_driving_info[id]; + } else { + if (raw_id >= ARRAY_SIZE(gpio_driving_info)) + return NULL; + return &gpio_driving_info[raw_id]; + } } const struct gpio_drv_info *get_gpio_driving_adv_info(uint32_t raw_id) { - if (raw_id >= ARRAY_SIZE(gpio_driving_adv_info)) + if (ENV_BOOTBLOCK) { return NULL; - return &gpio_driving_adv_info[raw_id]; + } else { + if (raw_id >= ARRAY_SIZE(gpio_driving_adv_info)) + return NULL; + return &gpio_driving_adv_info[raw_id]; + } } -- To view, visit https://review.coreboot.org/c/coreboot/+/86538?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If7e8e5c7db59b5f181db14f6e66df2f333dbb6d4 Gerrit-Change-Number: 86538 Gerrit-PatchSet: 1 Gerrit-Owner: Vince Liu <vince-wl.liu(a)mediatek.com>

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coreboot-gerrit February 2025