coreboot-gerrit February 2025

coreboot-gerrit@coreboot.org

1 participants
2886 discussions

[S] Change in blobs[main]: soc/mediatek/mt8196: Update DRAM blob to 16174.34.0
by Yidi Lin (Code Review) 19 Feb '25

19 Feb '25

Attention is currently required from: Jarried Lin, Yu-Ping Wu. Yidi Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/blobs/+/86534?usp=email ) Change subject: soc/mediatek/mt8196: Update DRAM blob to 16174.34.0 ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/blobs/+/86534?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: blobs Gerrit-Branch: main Gerrit-Change-Id: I08d6fb61d8ceec56e3d5b8db5da1ac47291eeb85 Gerrit-Change-Number: 86534 Gerrit-PatchSet: 1 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Thu, 20 Feb 2025 06:30:26 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

1 0

[M] Change in coreboot[main]: drivers/intel/fsp2_0: Add early low-battery shutdown during memory init
by Karthik Ramasubramanian (Code Review) 19 Feb '25

19 Feb '25

Attention is currently required from: Andrey Petrov, Intel coreboot Reviewers, Julius Werner, Ronak Kanabar, Subrata Banik. Karthik Ramasubramanian has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/86452?usp=email ) Change subject: drivers/intel/fsp2_0: Add early low-battery shutdown during memory init ...................................................................... Patch Set 6: (1 comment) File src/drivers/intel/fsp2_0/memory_init.c: https://review.coreboot.org/c/coreboot/+/86452/comment/84dc3ced_2fc8ae13?us… : PS6, Line 351: platform_display_early_shutdown_notification(NULL); I am wondering if ux.h can be moved from soc/intel/${soc}/romstage/ into either src/drivers/intel/ux/ux.h or src/vendorcode/intel/ux/ux.h. It can export the following APIs: bool ux_inform_user_of_update_operation(const char *name, void *arg); bool ux_inform_user_of_poweroff_operation(const char *name, void *arg, bool *defer_poweroff); Then ux_libgfxinit.c and ux_ugop.c can be added. ux_libgfxinit.c re-uses the code as is from soc/intel/alderlake/romstage/ux.c. arg is unused in this driver. ux_ugop.c gathers all the common codes for meteorlake, pantherlake and uses arg as fspm_upd. At most one of them gets enabled depending on the SoC. With that this part can be simplified as: ``` if (CONFIG(PLATFORM_HAS_EARLY_LOW_BATTERY_INDICATOR)) { ux_inform_user_of_poweroff_operation("low-battery-shutdown", fspm_upd, defer_shutdown); if (!defer_shutdown) do_low_battery_poweroff(); } ``` That way we don't need platform_display_early_shutdown_notification hook. This will also address Julius's comment here: https://review.coreboot.org/c/coreboot/+/85454/comment/3280809d_e258c525/ I am suggesting this since it is getting harder to wrap up the flow with too many if(CONFIG(...)) checks and platform_specific hooks. -- To view, visit https://review.coreboot.org/c/coreboot/+/86452?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia135b238d1e16722c2ca8d3b461e83b4ce513adf Gerrit-Change-Number: 86452 Gerrit-PatchSet: 6 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Comment-Date: Thu, 20 Feb 2025 06:23:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

1 0

[XS] Change in coreboot[main]: mb/google/brya: Do not select HAVE_ACPI_RESUME
by Eric Lai (Code Review) 19 Feb '25

19 Feb '25

Attention is currently required from: Dinesh Gehlot, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Paul Menzel. Eric Lai has posted comments on this change by Dinesh Gehlot. ( https://review.coreboot.org/c/coreboot/+/86422?usp=email ) Change subject: mb/google/brya: Do not select HAVE_ACPI_RESUME ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86422?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic0dce9c7779333ca079001e3763e843a4aad9a81 Gerrit-Change-Number: 86422 Gerrit-PatchSet: 3 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Thu, 20 Feb 2025 06:06:24 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

1 0

[L] Change in coreboot[main]: mb/google/nissa/var/meliks: Copy pirrha’s overridetree as initial one
by SH Kim (Code Review) 19 Feb '25

19 Feb '25

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Paul Menzel, Subrata Banik. SH Kim has posted comments on this change by SH Kim. ( https://review.coreboot.org/c/coreboot/+/86377?usp=email ) Change subject: mb/google/nissa/var/meliks: Copy pirrha’s overridetree as initial one ...................................................................... Patch Set 6: (1 comment) File src/mainboard/google/brya/variants/meliks/overridetree.cb: https://review.coreboot.org/c/coreboot/+/86377/comment/560efdf5_a79701f6?us… : PS5, Line 269: probed > Done Actually meliks uses a panel-built-in touch screen. This touch screen IC needs some delay after panel power up, so it may not be detected in coreboot phase. Can we keep the `probed` for this special IC? -- To view, visit https://review.coreboot.org/c/coreboot/+/86377?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifd6dfbeca7276dbacd72f9145ed7119566c8faef Gerrit-Change-Number: 86377 Gerrit-PatchSet: 6 Gerrit-Owner: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Thu, 20 Feb 2025 05:53:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Comment-In-Reply-To: Kapil Porwal <kapilporwal(a)google.com>

1 0

[M] Change in coreboot[main]: soc/intel/common: Refactor FSP-M early Sign-of-Life (SoL) settings
by Subrata Banik (Code Review) 19 Feb '25

19 Feb '25

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Intel coreboot Reviewers, Jakub "Kuba" Czapiga, Jayvik Desai, Jérémy Compostella, Kapil Porwal, Pranava Y N, Tarun. Subrata Banik has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/86532?usp=email ) Change subject: soc/intel/common: Refactor FSP-M early Sign-of-Life (SoL) settings ...................................................................... Patch Set 6: (1 comment) Patchset: PS6: we are having discussion at https://review.coreboot.org/c/coreboot/+/85454/comment/3280809d_e258c525/ where I'm suggesting to avoid doing common code approach based on FSP-UPD names which can be volatile where names can be changed in future or add/delete UPDs are also possible. -- To view, visit https://review.coreboot.org/c/coreboot/+/86532?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I03506fbc49ea5b86ce65fe2afbf692b6708a87c5 Gerrit-Change-Number: 86532 Gerrit-PatchSet: 6 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jakub "Kuba" Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub "Kuba" Czapiga <czapiga(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Thu, 20 Feb 2025 05:17:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

1 0

[S] Change in coreboot[main]: soc/intel/pantherlake: Display Sign-of-Life during memory training
by Subrata Banik (Code Review) 19 Feb '25

19 Feb '25

Attention is currently required from: Alok Agarwal, Anil Kumar K, Intel coreboot Reviewers, Jayvik Desai, Julius Werner, Jérémy Compostella, Kapil Porwal, Paul Menzel, Pranava Y N, Vikrant L Jadeja. Subrata Banik has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/85454?usp=email ) Change subject: soc/intel/pantherlake: Display Sign-of-Life during memory training ...................................................................... Patch Set 21: (1 comment) File src/soc/intel/pantherlake/romstage/fsp_params.c: https://review.coreboot.org/c/coreboot/+/85454/comment/4e552442_343b3a26?us… : PS21, Line 387: m_cfg->VgaMessage = (efi_uintn_t)ux_locales_get_text(UX_LOCALE_MSG_MEMORY_TRAINING); > I have considered your point, and I agree with you that there is a slight leap of faith in the proposed refactoring of the code. The Firmware Support Package (FSP) engineers are not going to guarantee that there won't be any changes in the upcoming generations. However, I would argue that: > > 1. `VbtSize` and `LidStatus` have been in existence for some time (since the Alder Lake generation, and possibly even earlier, in System-on-Chips (SoCs) not supported by coreboot). > 2. `VbtPtr`, `VgaInitControl`, and `VgaMessage` have already persisted through several generations (Meteor Lake and Panther Lake, but also Lunar Lake, and as far as I know, Wildcat Lake). > > I do not think it is particularly detrimental to provide a common function at this time and see how long we can continue to use it. Independent of how long we can go this route and then pull back, I'd recommend not to pursue this approach, as it relies on FSP UPD names. In the past, we have done this as well, but the common code principle discourages common things based on FSP UPD names, which can change without notice. I don't see any added value to trying to combine MTL/PTL FSP UPDs with the assumption that it will stay common. How about adding more eSOL UPDs in the future, like Battery Status, which won't be present inside a prior generation but we assume is added in the NVL timeline? We should disregard any need to common things based on FSP UPDs. FSP UPDs are meant to be SoC local, and trying to generalize these are simply overdoing it. -- To view, visit https://review.coreboot.org/c/coreboot/+/85454?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I993eb0d59cd01fa62f35a77f84e262e389efb367 Gerrit-Change-Number: 85454 Gerrit-PatchSet: 21 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Alok Agarwal <alok.agarwal(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Attention: Alok Agarwal <alok.agarwal(a)intel.com> Gerrit-Comment-Date: Thu, 20 Feb 2025 05:15:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org>

1 0

[S] Change in coreboot[main]: soc/intel/pantherlake: Display Sign-of-Life during memory training
by Jérémy Compostella (Code Review) 19 Feb '25

19 Feb '25

Attention is currently required from: Alok Agarwal, Anil Kumar K, Intel coreboot Reviewers, Jayvik Desai, Julius Werner, Kapil Porwal, Paul Menzel, Pranava Y N, Subrata Banik, Vikrant L Jadeja. Jérémy Compostella has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/85454?usp=email ) Change subject: soc/intel/pantherlake: Display Sign-of-Life during memory training ...................................................................... Patch Set 21: (1 comment) File src/soc/intel/pantherlake/romstage/fsp_params.c: https://review.coreboot.org/c/coreboot/+/85454/comment/eaa0c36d_40e83ad7?us… : PS21, Line 387: m_cfg->VgaMessage = (efi_uintn_t)ux_locales_get_text(UX_LOCALE_MSG_MEMORY_TRAINING); > > > Would https://review.coreboot.org/c/coreboot/+/86532 be acceptable ? […] I have considered your point, and I agree with you that there is a slight leap of faith in the proposed refactoring of the code. The Firmware Support Package (FSP) engineers are not going to guarantee that there won't be any changes in the upcoming generations. However, I would argue that: 1. `VbtSize` and `LidStatus` have been in existence for some time (since the Alder Lake generation, and possibly even earlier, in System-on-Chips (SoCs) not supported by coreboot). 2. `VbtPtr`, `VgaInitControl`, and `VgaMessage` have already persisted through several generations (Meteor Lake and Panther Lake, but also Lunar Lake, and as far as I know, Wildcat Lake). I do not think it is particularly detrimental to provide a common function at this time and see how long we can continue to use it. -- To view, visit https://review.coreboot.org/c/coreboot/+/85454?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I993eb0d59cd01fa62f35a77f84e262e389efb367 Gerrit-Change-Number: 85454 Gerrit-PatchSet: 21 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Alok Agarwal <alok.agarwal(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Attention: Alok Agarwal <alok.agarwal(a)intel.com> Gerrit-Comment-Date: Thu, 20 Feb 2025 04:52:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org>

1 0

[S] Change in coreboot[main]: soc/intel/pantherlake: Display Sign-of-Life during memory training
by Subrata Banik (Code Review) 19 Feb '25

19 Feb '25

Attention is currently required from: Alok Agarwal, Anil Kumar K, Intel coreboot Reviewers, Jayvik Desai, Julius Werner, Jérémy Compostella, Kapil Porwal, Paul Menzel, Pranava Y N, Vikrant L Jadeja. Subrata Banik has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/85454?usp=email ) Change subject: soc/intel/pantherlake: Display Sign-of-Life during memory training ...................................................................... Patch Set 21: (1 comment) File src/soc/intel/pantherlake/romstage/fsp_params.c: https://review.coreboot.org/c/coreboot/+/85454/comment/9a968aef_41f61910?us… : PS21, Line 387: m_cfg->VgaMessage = (efi_uintn_t)ux_locales_get_text(UX_LOCALE_MSG_MEMORY_TRAINING); > > Would https://review.coreboot.org/c/coreboot/+/86532 be acceptable ? > > > I'm planning to take step approach here by implementing https://review.coreboot.org/c/coreboot/+/86509/1 and then move the SoC UX into basecode. Now we would have two kinds of UX implementation (for ADL using libgfxinit and MTL onwards using uGOP). > > Note, we need some special handling like https://review.coreboot.org/c/coreboot/+/86509/1/src/soc/intel/pantherlake/… to avoid overlapping text message due to low-battery w/ MRC update in pipeline > > At this moment, I would prefer to land the SoC changes as is and take the refactoring with upcoming CLs. let me you @julius has any concerns Additionally, moving common things based on FSP-M UPD names is a terrible idea because there's no guarantee these names will stay the same across future SoC generations. Any change in the UPD name would prevent us from using this common layer of code. The FSP team can't guarantee they'll keep using the same UPD names. I would strongly recommend to keep UPDs inside SoC layer and use helper implementation like UX.c/.h to allow sharing the code across different use case like low-battery, updates etc. ``` m_cfg->VgaInitControl = vga_init_control; m_cfg->VbtPtr = (efi_uintn_t)vbt; m_cfg->VbtSize = vbt_size; m_cfg->LidStatus = CONFIG(VBOOT_LID_SWITCH) ? get_lid_switch() : CONFIG(RUN_FSP_GOP); m_cfg->VgaMessage = (efi_uintn_t)ux_locales_get_text(UX_LOCALE_MSG_MEMORY_TRAINING); } ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/85454?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I993eb0d59cd01fa62f35a77f84e262e389efb367 Gerrit-Change-Number: 85454 Gerrit-PatchSet: 21 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Alok Agarwal <alok.agarwal(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Attention: Alok Agarwal <alok.agarwal(a)intel.com> Gerrit-Comment-Date: Thu, 20 Feb 2025 04:41:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org>

1 0

[XS] Change in coreboot[main]: soc/intel/common/gpio: Add macro for interrupt GPI with driver mode
by Jérémy Compostella (Code Review) 19 Feb '25

19 Feb '25

Attention is currently required from: Cliff Huang, Intel coreboot Reviewers, Kyoung Il Kim. Jérémy Compostella has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/86414?usp=email ) Change subject: soc/intel/common/gpio: Add macro for interrupt GPI with driver mode ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: It seems that this is only used by [[https://review.coreboot.org/c/coreboot/+/85200]]. I would recommend moving that change list (CL) right before it. The reason is that anticipating a need and landing it before full approval is risky. Sometimes, as you go through the review process, the need disappears, and something unnecessary gets added to the codebase. -- To view, visit https://review.coreboot.org/c/coreboot/+/86414?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibc1ed3089c24302bc7eb02318714b8ec464fad01 Gerrit-Change-Number: 86414 Gerrit-PatchSet: 3 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Kyoung Il Kim <kyoung.il.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Kyoung Il Kim <kyoung.il.kim(a)intel.com> Gerrit-Comment-Date: Thu, 20 Feb 2025 04:40:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

1 0

[S] Change in coreboot[main]: mb/google/nissa/var/guren: Generate SPD ID for supported memory parts
by Brian Hsu (Code Review) 19 Feb '25

19 Feb '25

Brian Hsu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86535?usp=email ) Change subject: mb/google/nissa/var/guren: Generate SPD ID for supported memory parts ...................................................................... mb/google/nissa/var/guren: Generate SPD ID for supported memory parts Add supported memory parts in mem_parts_used list, and generate SPD ID for these parts. DRAM Part Name ID to assign K3KL8L80CM-MGCT 0 (0000) K3KL6L60GM-MGCT 1 (0001) H58G56AK6BX069 2 (0010) H9JCNNNBK3MLYR-N6E 3 (0011) H58G66AK6BX070 4 (0100) K3KL9L90CM-MGCT 5 (0101) K3LKBKB0BM-MGCP 2 (0010) BUG=b:397149037 BRANCH=firmware-nissa-15217.B TEST=Run command "go run ./util/spd_tools/src/part_id_gen/\ part_id_gen.go ADL lp5 \ src/mainboard/google/brya/variants/guren/memory/ \ src/mainboard/google/brya/variants/guren/memory/\ mem_parts_used.txt" Change-Id: Ibc8626ea51e1143706b8c627f21d33c3ade6a232 Signed-off-by: Brian Hsu <Brian_Hsu(a)pegatron.corp-partner.google.com> --- M src/mainboard/google/brya/variants/guren/memory/Makefile.mk M src/mainboard/google/brya/variants/guren/memory/dram_id.generated.txt M src/mainboard/google/brya/variants/guren/memory/mem_parts_used.txt 3 files changed, 28 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/86535/1 diff --git a/src/mainboard/google/brya/variants/guren/memory/Makefile.mk b/src/mainboard/google/brya/variants/guren/memory/Makefile.mk index eace2e4..943dfba 100644 --- a/src/mainboard/google/brya/variants/guren/memory/Makefile.mk +++ b/src/mainboard/google/brya/variants/guren/memory/Makefile.mk @@ -1,5 +1,12 @@ # SPDX-License-Identifier: GPL-2.0-or-later # This is an auto-generated file. Do not edit!! -# Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. +# Generated by: +# /tmp/go-build776947141/b001/exe/part_id_gen ADL lp5 src/mainboard/google/brya/variants/guren/memory/ src/mainboard/google/brya/variants/guren/memory/mem_parts_used.txt -SPD_SOURCES = placeholder +SPD_SOURCES = +SPD_SOURCES += spd/lp5/set-0/spd-7.hex # ID = 0(0b0000) Parts = K3KL8L80CM-MGCT +SPD_SOURCES += spd/lp5/set-0/spd-9.hex # ID = 1(0b0001) Parts = K3KL6L60GM-MGCT +SPD_SOURCES += spd/lp5/set-0/spd-3.hex # ID = 2(0b0010) Parts = H58G56AK6BX069, K3LKBKB0BM-MGCP +SPD_SOURCES += spd/lp5/set-0/spd-1.hex # ID = 3(0b0011) Parts = H9JCNNNBK3MLYR-N6E +SPD_SOURCES += spd/lp5/set-0/spd-6.hex # ID = 4(0b0100) Parts = H58G66AK6BX070 +SPD_SOURCES += spd/lp5/set-0/spd-8.hex # ID = 5(0b0101) Parts = K3KL9L90CM-MGCT diff --git a/src/mainboard/google/brya/variants/guren/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/guren/memory/dram_id.generated.txt index fa24790..62cd085 100644 --- a/src/mainboard/google/brya/variants/guren/memory/dram_id.generated.txt +++ b/src/mainboard/google/brya/variants/guren/memory/dram_id.generated.txt @@ -1 +1,13 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Generated by: +# /tmp/go-build776947141/b001/exe/part_id_gen ADL lp5 src/mainboard/google/brya/variants/guren/memory/ src/mainboard/google/brya/variants/guren/memory/mem_parts_used.txt + DRAM Part Name ID to assign +K3KL8L80CM-MGCT 0 (0000) +K3KL6L60GM-MGCT 1 (0001) +H58G56AK6BX069 2 (0010) +H9JCNNNBK3MLYR-N6E 3 (0011) +H58G66AK6BX070 4 (0100) +K3KL9L90CM-MGCT 5 (0101) +K3LKBKB0BM-MGCP 2 (0010) diff --git a/src/mainboard/google/brya/variants/guren/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/guren/memory/mem_parts_used.txt index 2499005..a7e8120 100644 --- a/src/mainboard/google/brya/variants/guren/memory/mem_parts_used.txt +++ b/src/mainboard/google/brya/variants/guren/memory/mem_parts_used.txt @@ -9,3 +9,10 @@ # See util/spd_tools/README.md for more details and instructions. # Part Name +K3KL8L80CM-MGCT +K3KL6L60GM-MGCT +H58G56AK6BX069 +H9JCNNNBK3MLYR-N6E +H58G66AK6BX070 +K3KL9L90CM-MGCT +K3LKBKB0BM-MGCP -- To view, visit https://review.coreboot.org/c/coreboot/+/86535?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibc8626ea51e1143706b8c627f21d33c3ade6a232 Gerrit-Change-Number: 86535 Gerrit-PatchSet: 1 Gerrit-Owner: Brian Hsu <brian_hsu(a)pegatron.corp-partner.google.com>

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit February 2025