coreboot-gerrit February 2025

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[M] Change in coreboot[main]: soc/intel/common: Refactor FSP-M early Sign-of-Life (SoL) settings
by Jérémy Compostella (Code Review) 19 Feb '25

19 Feb '25

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Intel coreboot Reviewers, Jakub "Kuba" Czapiga, Jayvik Desai, Kapil Porwal, Pranava Y N, Subrata Banik, Tarun. Hello Dinesh Gehlot, Eran Mitrani, Intel coreboot Reviewers, Jakub "Kuba" Czapiga, Jayvik Desai, Kapil Porwal, Pranava Y N, Subrata Banik, Tarun, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86532?usp=email to look at the new patch set (#6). Change subject: soc/intel/common: Refactor FSP-M early Sign-of-Life (SoL) settings ...................................................................... soc/intel/common: Refactor FSP-M early Sign-of-Life (SoL) settings This commit centralizes the configuration of the Firmware Support Package for Memory (FSP-M) early Sign-of-Life (SoL) into a common function to reduce code duplication and enhance maintainability. This refactoring aims to improve code readability and reduce potential bugs by having a single source of truth for SoL configuration across different platforms. Since the Updateable Product Data (UPD) definitions for VGAInitControl differ between Meteor Lake and Panther Lake, and because the list of currently supported uses also varies between the two, the decision-making process is still being conducted within the SoC (System on Chip)-specific codebase. TEST=FSP-M early SoL functionality was verified on Panther Lake platform. Change-Id: I03506fbc49ea5b86ce65fe2afbf692b6708a87c5 Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> --- M src/soc/intel/common/Makefile.mk A src/soc/intel/common/fsp_esol.c A src/soc/intel/common/fsp_esol.h M src/soc/intel/meteorlake/romstage/fsp_params.c M src/soc/intel/pantherlake/romstage/fsp_params.c 5 files changed, 54 insertions(+), 41 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/86532/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/86532?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I03506fbc49ea5b86ce65fe2afbf692b6708a87c5 Gerrit-Change-Number: 86532 Gerrit-PatchSet: 6 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jakub "Kuba" Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jakub "Kuba" Czapiga <czapiga(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com>

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[M] Change in coreboot[main]: soc/intel/common: Refactor FSP-M early Sign-of-Life (SoL) settings
by Jérémy Compostella (Code Review) 19 Feb '25

19 Feb '25

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Intel coreboot Reviewers, Jakub "Kuba" Czapiga, Jayvik Desai, Kapil Porwal, Pranava Y N, Subrata Banik, Tarun. Hello Dinesh Gehlot, Eran Mitrani, Intel coreboot Reviewers, Jakub "Kuba" Czapiga, Jayvik Desai, Kapil Porwal, Pranava Y N, Subrata Banik, Tarun, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86532?usp=email to look at the new patch set (#5). Change subject: soc/intel/common: Refactor FSP-M early Sign-of-Life (SoL) settings ...................................................................... soc/intel/common: Refactor FSP-M early Sign-of-Life (SoL) settings This commit centralizes the configuration of the Firmware Support Package for Memory (FSP-M) early Sign-of-Life (SoL) into a common function to reduce code duplication and enhance maintainability. This refactoring aims to improve code readability and reduce potential bugs by having a single source of truth for SoL configuration across different platforms. Since the Updateable Product Data (UPD) definitions for VGAInitControl differ between Meteor Lake and Panther Lake, and because the list of currently supported uses also varies between the two, the decision-making process is still being conducted within the SoC (System on Chip)-specific codebase. TEST=FSP-M early SoL functionality was verified on Panther Lake platform. Change-Id: I03506fbc49ea5b86ce65fe2afbf692b6708a87c5 Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> --- M src/soc/intel/common/Makefile.mk A src/soc/intel/common/fsp_esol.c A src/soc/intel/common/fsp_esol.h M src/soc/intel/meteorlake/romstage/fsp_params.c M src/soc/intel/pantherlake/romstage/fsp_params.c 5 files changed, 54 insertions(+), 41 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/86532/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/86532?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I03506fbc49ea5b86ce65fe2afbf692b6708a87c5 Gerrit-Change-Number: 86532 Gerrit-PatchSet: 5 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jakub "Kuba" Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jakub "Kuba" Czapiga <czapiga(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com>

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[M] Change in coreboot[main]: soc/intel/common: Refactor FSP-M early Sign-of-Life (SoL) settings
by Jérémy Compostella (Code Review) 19 Feb '25

19 Feb '25

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Intel coreboot Reviewers, Jakub "Kuba" Czapiga, Jayvik Desai, Kapil Porwal, Pranava Y N, Subrata Banik, Tarun. Hello Dinesh Gehlot, Eran Mitrani, Intel coreboot Reviewers, Jakub "Kuba" Czapiga, Jayvik Desai, Kapil Porwal, Pranava Y N, Subrata Banik, Tarun, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86532?usp=email to look at the new patch set (#4). Change subject: soc/intel/common: Refactor FSP-M early Sign-of-Life (SoL) settings ...................................................................... soc/intel/common: Refactor FSP-M early Sign-of-Life (SoL) settings This commit centralizes the configuration of the Firmware Support Package for Memory (FSP-M) early Sign-of-Life (SoL) into a common function to reduce code duplication and enhance maintainability. This refactoring aims to improve code readability and reduce potential bugs by having a single source of truth for SoL configuration across different platforms. Since the Updateable Product Data (UPD) definitions for VGAInitControl differ between Meteor Lake and Panther Lake, and because the list of currently supported uses also varies between the two, the decision-making process is still being conducted within the SoC (System on Chip)-specific codebase. TEST=FSP-M early SoL functionality was verified on Panther Lake platform. Change-Id: I03506fbc49ea5b86ce65fe2afbf692b6708a87c5 Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> --- M src/soc/intel/common/Makefile.mk A src/soc/intel/common/fsp_esol.c A src/soc/intel/common/fsp_esol.h M src/soc/intel/meteorlake/romstage/fsp_params.c M src/soc/intel/pantherlake/romstage/fsp_params.c 5 files changed, 46 insertions(+), 41 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/86532/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/86532?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I03506fbc49ea5b86ce65fe2afbf692b6708a87c5 Gerrit-Change-Number: 86532 Gerrit-PatchSet: 4 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jakub "Kuba" Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jakub "Kuba" Czapiga <czapiga(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com>

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[M] Change in coreboot[main]: soc/intel/common: Refactor FSP-M early Sign-of-Life (SoL) settings
by Jérémy Compostella (Code Review) 19 Feb '25

19 Feb '25

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Intel coreboot Reviewers, Jakub "Kuba" Czapiga, Jayvik Desai, Kapil Porwal, Pranava Y N, Subrata Banik, Tarun. Hello Dinesh Gehlot, Eran Mitrani, Intel coreboot Reviewers, Jakub "Kuba" Czapiga, Jayvik Desai, Kapil Porwal, Pranava Y N, Subrata Banik, Tarun, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86532?usp=email to look at the new patch set (#3). Change subject: soc/intel/common: Refactor FSP-M early Sign-of-Life (SoL) settings ...................................................................... soc/intel/common: Refactor FSP-M early Sign-of-Life (SoL) settings This commit centralizes the configuration of the Firmware Support Package for Memory (FSP-M) early Sign-of-Life (SoL) into a common function to reduce code duplication and enhance maintainability. This refactoring aims to improve code readability and reduce potential bugs by having a single source of truth for SoL configuration across different platforms. Since the Updateable Product Data (UPD) definitions for VGAInitControl differ between Meteor Lake and Panther Lake, and because the list of currently supported uses also varies between the two, the decision-making process is still being conducted within the SoC (System on Chip)-specific codebase. TEST=FSP-M early SoL functionality was verified on Panther Lake platform. Change-Id: I03506fbc49ea5b86ce65fe2afbf692b6708a87c5 Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> --- M src/soc/intel/common/Makefile.mk A src/soc/intel/common/fsp_esol.c A src/soc/intel/common/fsp_esol.h M src/soc/intel/meteorlake/romstage/fsp_params.c M src/soc/intel/pantherlake/romstage/fsp_params.c 5 files changed, 46 insertions(+), 39 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/86532/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/86532?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I03506fbc49ea5b86ce65fe2afbf692b6708a87c5 Gerrit-Change-Number: 86532 Gerrit-PatchSet: 3 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jakub "Kuba" Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jakub "Kuba" Czapiga <czapiga(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com>

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[M] Change in coreboot[main]: soc/intel/common: Refactor FSP-M early Sign-of-Life (SoL) settings
by Jérémy Compostella (Code Review) 19 Feb '25

19 Feb '25

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Intel coreboot Reviewers, Jakub "Kuba" Czapiga, Jayvik Desai, Kapil Porwal, Pranava Y N, Subrata Banik, Tarun. Hello Dinesh Gehlot, Eran Mitrani, Intel coreboot Reviewers, Jakub "Kuba" Czapiga, Jayvik Desai, Kapil Porwal, Pranava Y N, Subrata Banik, Tarun, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86532?usp=email to look at the new patch set (#2). Change subject: soc/intel/common: Refactor FSP-M early Sign-of-Life (SoL) settings ...................................................................... soc/intel/common: Refactor FSP-M early Sign-of-Life (SoL) settings This commit centralizes the configuration of the Firmware Support Package for Memory (FSP-M) early Sign-of-Life (SoL) into a common function to reduce code duplication and enhance maintainability. This refactoring aims to improve code readability and reduce potential bugs by having a single source of truth for SoL configuration across different platforms. Since the Updateable Product Data (UPD) definitions for VGAInitControl differ between Meteor Lake and Panther Lake, and because the list of currently supported uses also varies between the two, the decision-making process is still being conducted within the SoC (System on Chip)-specific codebase. TEST=FSP-M early SoL functionality was verified on Panther Lake platform. Change-Id: I03506fbc49ea5b86ce65fe2afbf692b6708a87c5 Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> --- M src/soc/intel/common/Makefile.mk A src/soc/intel/common/fsp_esol.c A src/soc/intel/common/fsp_esol.h M src/soc/intel/meteorlake/romstage/fsp_params.c M src/soc/intel/pantherlake/romstage/fsp_params.c 5 files changed, 45 insertions(+), 38 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/86532/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86532?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I03506fbc49ea5b86ce65fe2afbf692b6708a87c5 Gerrit-Change-Number: 86532 Gerrit-PatchSet: 2 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jakub "Kuba" Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jakub "Kuba" Czapiga <czapiga(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com>

1 0

[M] Change in coreboot[main]: soc/intel/common: Refactor FSP-M early Sign-of-Life (SoL) settings
by Jérémy Compostella (Code Review) 19 Feb '25

19 Feb '25

Jérémy Compostella has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86532?usp=email ) Change subject: soc/intel/common: Refactor FSP-M early Sign-of-Life (SoL) settings ...................................................................... soc/intel/common: Refactor FSP-M early Sign-of-Life (SoL) settings This commit centralizes the configuration of the Firmware Support Package for Memory (FSP-M) early Sign-of-Life (SoL) into a common function to reduce code duplication and enhance maintainability. This refactoring aims to improve code readability and reduce potential bugs by having a single source of truth for SoL configuration across different platforms. Since the Updateable Product Data (UPD) definitions for VGAInitControl differ between Meteor Lake and Panther Lake, and because the list of currently supported uses also varies between the two, the decision-making process is still being conducted within the SoC (System on Chip)-specific codebase. TEST=FSP-M early SoL functionality was verified on Pantherlake platform. Change-Id: I03506fbc49ea5b86ce65fe2afbf692b6708a87c5 Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> --- M src/soc/intel/common/Makefile.mk A src/soc/intel/common/fsp_esol.c A src/soc/intel/common/fsp_esol.h M src/soc/intel/meteorlake/romstage/fsp_params.c M src/soc/intel/pantherlake/romstage/fsp_params.c 5 files changed, 45 insertions(+), 38 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/86532/1 diff --git a/src/soc/intel/common/Makefile.mk b/src/soc/intel/common/Makefile.mk index b273ed7..241ba4f 100644 --- a/src/soc/intel/common/Makefile.mk +++ b/src/soc/intel/common/Makefile.mk @@ -11,6 +11,7 @@ romstage-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c romstage-$(CONFIG_MMA) += mma.c +romstage-$(CONFIG_FSP_UGOP_EARLY_SIGN_OF_LIFE) += fsp_esol.c romstage-y += smbios.c postcar-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c diff --git a/src/soc/intel/common/fsp_esol.c b/src/soc/intel/common/fsp_esol.c new file mode 100644 index 0000000..b5338b9 --- /dev/null +++ b/src/soc/intel/common/fsp_esol.c @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <bootmode.h> +#include <cbfs.h> +#include <console/console.h> +#include <fsp/util.h> +#include <soc/intel/common/fsp_esol.h> +#include <ux_locales.h> + +void fsp_set_esol_params(uint32_t vga_init_control, FSP_M_CONFIG *m_cfg) +{ + void *vbt; + size_t vbt_size; + + vbt = cbfs_map("vbt.bin", &vbt_size); + if (!vbt) { + printk(BIOS_ERR, "Could not load vbt.bin\n"); + return; + } + + printk(BIOS_INFO, "Enabling FSP-M Sign-of-Life\n"); + + m_cfg->VgaInitControl = vga_init_control; + m_cfg->VbtPtr = (efi_uintn_t)vbt; + m_cfg->VbtSize = vbt_size; + m_cfg->LidStatus = CONFIG(VBOOT_LID_SWITCH) ? get_lid_switch() : CONFIG(RUN_FSP_GOP); + m_cfg->VgaMessage = (efi_uintn_t)ux_locales_get_text(UX_LOCALE_MSG_MEMORY_TRAINING); + +} diff --git a/src/soc/intel/common/fsp_esol.h b/src/soc/intel/common/fsp_esol.h new file mode 100644 index 0000000..992142b --- /dev/null +++ b/src/soc/intel/common/fsp_esol.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef _INTEL_COMMON_FSP_ESOL_H_ +#define _INTEL_COMMON_FSP_ESOL_H_ + +void fsp_set_esol_params(uint32_t vga_init_control, FSP_M_CONFIG *m_cfg); + +#endif /* _INTEL_COMMON_FSP_ESOL_H_ */ diff --git a/src/soc/intel/meteorlake/romstage/fsp_params.c b/src/soc/intel/meteorlake/romstage/fsp_params.c index dd9d2b5..bcd384f 100644 --- a/src/soc/intel/meteorlake/romstage/fsp_params.c +++ b/src/soc/intel/meteorlake/romstage/fsp_params.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <assert.h> -#include <bootmode.h> #include <console/console.h> #include <cpu/intel/common/common.h> #include <cpu/intel/cpu_ids.h> @@ -19,6 +18,7 @@ #include <option.h> #include <soc/cpu.h> #include <soc/gpio_soc_defs.h> +#include <soc/intel/common/fsp_esol.h> #include <soc/iomap.h> #include <soc/msr.h> #include <soc/pci_devs.h> @@ -28,7 +28,6 @@ #include <soc/soc_info.h> #include <static.h> #include <string.h> -#include <ux_locales.h> #define FSP_CLK_NOTUSED 0xFF #define FSP_CLK_LAN 0x70 @@ -460,24 +459,8 @@ elog_add_event_byte(ELOG_TYPE_FW_EARLY_SOL, ELOG_FW_EARLY_SOL_CSE_SYNC); } - if (!vga_init_control) - return; - - const char *text = ux_locales_get_text(UX_LOCALE_MSG_MEMORY_TRAINING); - - vbt = cbfs_map("vbt.bin", &vbt_size); - if (!vbt) { - printk(BIOS_ERR, "Could not load vbt.bin\n"); - return; - } - - printk(BIOS_INFO, "Enabling FSP-M Sign-of-Life\n"); - - m_cfg->VgaInitControl = vga_init_control; - m_cfg->VbtPtr = (efi_uintn_t)vbt; - m_cfg->VbtSize = vbt_size; - m_cfg->LidStatus = CONFIG(VBOOT_LID_SWITCH) ? get_lid_switch() : CONFIG(RUN_FSP_GOP); - m_cfg->VgaMessage = (efi_uintn_t)text; + if (vga_init_control) + fsp_set_esol_params(vga_init_control, m_cfg); } void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) diff --git a/src/soc/intel/pantherlake/romstage/fsp_params.c b/src/soc/intel/pantherlake/romstage/fsp_params.c index 9691b10..d375185 100644 --- a/src/soc/intel/pantherlake/romstage/fsp_params.c +++ b/src/soc/intel/pantherlake/romstage/fsp_params.c @@ -8,12 +8,12 @@ #include <fsp/fsp_debug_event.h> #include <fsp/util.h> #include <intelblocks/cpulib.h> +#include <soc/intel/common/fsp_esol.h> #include <soc/iomap.h> #include <soc/msr.h> #include <soc/pcie.h> #include <soc/romstage.h> #include <static.h> -#include <ux_locales.h> #define FSP_CLK_NOTUSED 0xff #define FSP_CLK_LAN 0x70 @@ -369,29 +369,15 @@ { FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; FSPM_ARCHx_UPD *arch_upd = &mupd->FspmArchUpd; - void *vbt; - size_t vbt_size; if (arch_upd->NvsBufferPtr) return; - /* To enhance the user experience, let's display on-screen guidance during memory - training, acknowledging that the process may require patience. */ - - vbt = cbfs_map("vbt.bin", &vbt_size); - if (!vbt) { - printk(BIOS_ERR, "Could not load vbt.bin\n"); - return; - } - - printk(BIOS_INFO, "Enabling FSP-M Sign-of-Life\n"); elog_add_event_byte(ELOG_TYPE_FW_EARLY_SOL, ELOG_FW_EARLY_SOL_MRC); - m_cfg->VgaInitControl = 1; - m_cfg->VbtPtr = (efi_uintn_t)vbt; - m_cfg->VbtSize = vbt_size; - m_cfg->LidStatus = CONFIG(VBOOT_LID_SWITCH) ? get_lid_switch() : CONFIG(RUN_FSP_GOP); - m_cfg->VgaMessage = (efi_uintn_t)ux_locales_get_text(UX_LOCALE_MSG_MEMORY_TRAINING); + /* To enhance the user experience, let's display on-screen guidance during memory + training, acknowledging that the process may require patience. */ + fsp_set_esol_params(1, m_cfg); } void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) -- To view, visit https://review.coreboot.org/c/coreboot/+/86532?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I03506fbc49ea5b86ce65fe2afbf692b6708a87c5 Gerrit-Change-Number: 86532 Gerrit-PatchSet: 1 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com>

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[L] Change in coreboot[main]: drivers/intel/touch: Add Intel Touch Controller driver
by Cliff Huang (Code Review) 19 Feb '25

19 Feb '25

Attention is currently required from: Bora Guvendik, Intel coreboot Reviewers, Jérémy Compostella, Kyoung Il Kim, Paul Menzel, Subrata Banik. Hello Bora Guvendik, Intel coreboot Reviewers, Jérémy Compostella, Kyoung Il Kim, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85198?usp=email to look at the new patch set (#17). Change subject: drivers/intel/touch: Add Intel Touch Controller driver ...................................................................... drivers/intel/touch: Add Intel Touch Controller driver THC is a special interface supporting HID-i2c/HID-SPI protocols and touch devices. This driver publishes data into the Secondary System Descriptor Table (SSDT). This driver generates the following ACPI objects: - Device Specific Method (_DSM) - Current Resource Settings (_CRS) - Power resource with Status (_STA), _ON, and _OFF methods - Device Specific Data (_DSD) for THC-I2C - Device Reset (_RST) for THC-SPI Template device configuration for the following supported devices: - Wacom: SPI touchscreen only - Elan: both SPI and I2C touchscreen - Hynitron: I2C touchpad only The configuration is spitted into device, SoC, and MB specific. - SoC-specific: Implement soc_get_thc_hidi2c_info and soc_get_thc_hidspi_info functions for SoC-specific configurations. Theses can be placed in the SoC's chip.c. - device-specific: This driver provides the device-specific configuration for the supported devices; otherwise, require information via the device tree for unsupported/generic devices. - MB-specific: The MB-specific, such as LTR values and speed, needs to be provided in the device tree. BUG=none TEST=Select the DRIVERS_INTEL_TOUCH option on a motherboard with the necessary configurations, and verify that the THC ACPI tables are generated in the SSDT. Signed-off-by: Cliff Huang <cliff.huang(a)intel.com> Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> Change-Id: Ibcd2a75a41460dee67aebdc61ee9e85fa98b71bf --- A src/drivers/intel/touch/Kconfig A src/drivers/intel/touch/Makefile.mk A src/drivers/intel/touch/chip.h A src/drivers/intel/touch/elan.h A src/drivers/intel/touch/hynitron.h A src/drivers/intel/touch/touch.c A src/drivers/intel/touch/wacom.h 7 files changed, 930 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/85198/17 -- To view, visit https://review.coreboot.org/c/coreboot/+/85198?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibcd2a75a41460dee67aebdc61ee9e85fa98b71bf Gerrit-Change-Number: 85198 Gerrit-PatchSet: 17 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kyoung Il Kim <kyoung.il.kim(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kyoung Il Kim <kyoung.il.kim(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org>

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[S] Change in coreboot[main]: soc/intel/pantherlake: Display Sign-of-Life during memory training
by Julius Werner (Code Review) 19 Feb '25

19 Feb '25

Attention is currently required from: Alok Agarwal, Anil Kumar K, Intel coreboot Reviewers, Jayvik Desai, Jérémy Compostella, Kapil Porwal, Paul Menzel, Pranava Y N, Vikrant L Jadeja. Julius Werner has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/85454?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: soc/intel/pantherlake: Display Sign-of-Life during memory training ...................................................................... Patch Set 21: (1 comment) File src/soc/intel/pantherlake/romstage/fsp_params.c: https://review.coreboot.org/c/coreboot/+/85454/comment/3280809d_e258c525?us… : PS21, Line 387: m_cfg->VgaMessage = (efi_uintn_t)ux_locales_get_text(UX_LOCALE_MSG_MEMORY_TRAINING); A lot of this looks the same as the Meteorlake version. Aren't there common parts you could factor out? -- To view, visit https://review.coreboot.org/c/coreboot/+/85454?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I993eb0d59cd01fa62f35a77f84e262e389efb367 Gerrit-Change-Number: 85454 Gerrit-PatchSet: 21 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Alok Agarwal <alok.agarwal(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Attention: Alok Agarwal <alok.agarwal(a)intel.com> Gerrit-Comment-Date: Wed, 19 Feb 2025 22:14:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in blobs[main]: soc/mediatek/mt8196: Update MCUPM firmware to v1.2
by Yu-Ping Wu (Code Review) 19 Feb '25

19 Feb '25

Attention is currently required from: Jarried Lin, agogo. Yu-Ping Wu has posted comments on this change by agogo. ( https://review.coreboot.org/c/blobs/+/86511?usp=email ) Change subject: soc/mediatek/mt8196: Update MCUPM firmware to v1.2 ...................................................................... Patch Set 1: Verified+1 (1 comment) Patchset: PS1: Checked md5sum and version string. -- To view, visit https://review.coreboot.org/c/blobs/+/86511?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: blobs Gerrit-Branch: main Gerrit-Change-Id: I81e745a7290c31fe15240102df0a78dfaadf54e7 Gerrit-Change-Number: 86511 Gerrit-PatchSet: 1 Gerrit-Owner: agogo <agogo.huang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: agogo <agogo.huang(a)mediatek.corp-partner.google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Wed, 19 Feb 2025 22:09:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: mb/google/brya/var/agah: Separate the AGAH DPTF OEM variant
by Boris Mittelberg (Code Review) 19 Feb '25

19 Feb '25

Attention is currently required from: Caveh Jalali, Dinesh Gehlot, Eric Lai, Ivy Jian, Jayvik Desai, John Su, Kapil Porwal, Nick Vaccaro, Paul Menzel, Subrata Banik, Tony Huang, Wisley Chen. Boris Mittelberg has posted comments on this change by John Su. ( https://review.coreboot.org/c/coreboot/+/86493?usp=email ) Change subject: mb/google/brya/var/agah: Separate the AGAH DPTF OEM variant ...................................................................... Patch Set 4: (1 comment) File src/ec/google/chromeec/acpi/ec.asl: https://review.coreboot.org/c/coreboot/+/86493/comment/630be5a6_7139863a?us… : PS4, Line 383: #ifdef DPTF_ENABLE_OEM_VARIABLES : Local0 = ToInteger(EOVD) & EC_OEM_VARIABLE_DATA_MASK : \_SB.DPTF.ODUP(0, Local0) : Local0 = \_SB.DPTF.ODGT(0) : \_SB.DPTF.ODVP() : Notify (\_SB.DPTF, INT3400_ODVP_CHANGED) : #endif I think it should be OK to just remove this entire block, as agah is not supported anymore (agah EC code was removed in 2023) -- To view, visit https://review.coreboot.org/c/coreboot/+/86493?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2929eaa65a518b06f32e33cc31ae4a01bcfb77e8 Gerrit-Change-Number: 86493 Gerrit-PatchSet: 4 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-CC: Jamie Chen <jamie_chen(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Wed, 19 Feb 2025 21:20:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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