coreboot-gerrit February 2025

coreboot-gerrit@coreboot.org

1 participants
2886 discussions

[XS] Change in coreboot[main]: mb/google/fatcat/var/francka: Decrease trace length of USB-A phy to s...
by John Su (Code Review) 07 Feb '25

07 Feb '25

John Su has posted comments on this change by Amanda Hwang. ( https://review.coreboot.org/c/coreboot/+/86285?usp=email ) Change subject: mb/google/fatcat/var/francka: Decrease trace length of USB-A phy to short ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86285?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I140b8a2047768d3aeb0d5919aad998bd9dcd099f Gerrit-Change-Number: 86285 Gerrit-PatchSet: 4 Gerrit-Owner: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Reviewer: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Fri, 07 Feb 2025 08:49:33 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

1 0

[XS] Change in coreboot[main]: mb/google/rauru: Reorder PCIe reset in romstage
by Jarried Lin (Code Review) 07 Feb '25

07 Feb '25

Jarried Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86311?usp=email ) Change subject: mb/google/rauru: Reorder PCIe reset in romstage ...................................................................... mb/google/rauru: Reorder PCIe reset in romstage Reorder the PCIe reset before mtk_dram_init to overlap the de-assert time with the DRAM initialization process. BRANCH=rauru TEST=Build pass BUG=b:391333055 Change-Id: I24b254ff3a3cbe6d9a60a8e6afea2c621e0a07e2 Signed-off-by: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com> --- M src/mainboard/google/rauru/romstage.c 1 file changed, 2 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/86311/1 diff --git a/src/mainboard/google/rauru/romstage.c b/src/mainboard/google/rauru/romstage.c index 7860dfd..584af61 100644 --- a/src/mainboard/google/rauru/romstage.c +++ b/src/mainboard/google/rauru/romstage.c @@ -47,11 +47,10 @@ clk_buf_init(); if (CONFIG(RTC)) rtc_boot(); + if (CONFIG(PCI)) + mtk_pcie_deassert_perst(); mtk_dram_init(); modem_power_down(); dvfs_init(); thermal_init(); - - if (CONFIG(PCI)) - mtk_pcie_deassert_perst(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/86311?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I24b254ff3a3cbe6d9a60a8e6afea2c621e0a07e2 Gerrit-Change-Number: 86311 Gerrit-PatchSet: 1 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com>

1 0

[XS] Change in coreboot[main]: mb/google/fatcat/var/francka: Decrease trace length of USB-A phy to s...
by Subrata Banik (Code Review) 07 Feb '25

07 Feb '25

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86285?usp=email ) Change subject: mb/google/fatcat/var/francka: Decrease trace length of USB-A phy to short ...................................................................... mb/google/fatcat/var/francka: Decrease trace length of USB-A phy to short To resolve the issue of not being able to boot from USB on Francka, the USB PHY settings need to be modified. BUG=b:394206896 TEST=Build and test Type-A port function works fine Change-Id: I140b8a2047768d3aeb0d5919aad998bd9dcd099f Signed-off-by: Amanda Huang <amanda_hwang(a)compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86285 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Ian Feng <ian_feng(a)compal.corp-partner.google.com> --- M src/mainboard/google/fatcat/variants/francka/overridetree.cb 1 file changed, 2 insertions(+), 2 deletions(-) Approvals: Ian Feng: Looks good to me, approved Subrata Banik: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/google/fatcat/variants/francka/overridetree.cb b/src/mainboard/google/fatcat/variants/francka/overridetree.cb index 9d2dd2f..dc76b85 100644 --- a/src/mainboard/google/fatcat/variants/francka/overridetree.cb +++ b/src/mainboard/google/fatcat/variants/francka/overridetree.cb @@ -28,9 +28,9 @@ register "max_dram_speed_mts" = "7467" - register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" # Type-A Port A0 + register "usb2_ports[1]" = "USB2_PORT_SHORT(OC0)" # Type-A Port A0 register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C0 - register "usb2_ports[4]" = "USB2_PORT_MID(OC0)" # Type-A Port A1 + register "usb2_ports[4]" = "USB2_PORT_SHORT(OC0)" # Type-A Port A1 register "usb2_ports[5]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C1 register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # USB HUB (USB2 Camera) register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # CNVi BT or discrete BT -- To view, visit https://review.coreboot.org/c/coreboot/+/86285?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I140b8a2047768d3aeb0d5919aad998bd9dcd099f Gerrit-Change-Number: 86285 Gerrit-PatchSet: 4 Gerrit-Owner: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Reviewer: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

1 0

[S] Change in coreboot[main]: soc/intel/cmn/blk: Remove boot partition check for forced cse sync
by Dinesh Gehlot (Code Review) 07 Feb '25

07 Feb '25

Attention is currently required from: Intel coreboot Reviewers, Martin L Roth. Hello Intel coreboot Reviewers, Martin L Roth, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86153?usp=email to look at the new patch set (#8). Change subject: soc/intel/cmn/blk: Remove boot partition check for forced cse sync ...................................................................... soc/intel/cmn/blk: Remove boot partition check for forced cse sync This patch enhances the forced CSE sync mechanism by eliminating the boot partition check for RO. It utilizes the current CSE mechanism to determine if the system has undergone a cold boot. Please note, this is a proof of concept to address forced CSE sync constraint in the presence of a pre-CPU reset. The change is currently WIP and the final implementation might vary. BUG=b:380220737 TEST=Verified forced CSE sync on google/rex. Change-Id: If1e4180cb5fec3990fdee2b0e412173b1c8c6ded Signed-off-by: Dinesh Gehlot <digehlot(a)google.com> --- M src/soc/intel/common/block/cse/cse_lite.c M src/soc/intel/common/block/include/intelblocks/cse.h 2 files changed, 27 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/86153/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/86153?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If1e4180cb5fec3990fdee2b0e412173b1c8c6ded Gerrit-Change-Number: 86153 Gerrit-PatchSet: 8 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com>

1 0

[XS] Change in coreboot[main]: soc/intel/cmn/blk: Remove boot partition check for forced cse sync
by Dinesh Gehlot (Code Review) 07 Feb '25

07 Feb '25

Attention is currently required from: Intel coreboot Reviewers, Martin L Roth. Hello Intel coreboot Reviewers, Martin L Roth, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86153?usp=email to look at the new patch set (#7). Change subject: soc/intel/cmn/blk: Remove boot partition check for forced cse sync ...................................................................... soc/intel/cmn/blk: Remove boot partition check for forced cse sync This patch enhances the forced CSE sync mechanism by eliminating the boot partition check for RO. It utilizes the current CSE mechanism to determine if the system has undergone a cold boot. Please note, this is a proof of concept to address forced CSE sync constraint in the presence of a pre-CPU reset. The change is currently WIP and the final implementation might vary. BUG=b:380220737 TEST=Verified forced CSE sync on google/rex. Change-Id: If1e4180cb5fec3990fdee2b0e412173b1c8c6ded Signed-off-by: Dinesh Gehlot <digehlot(a)google.com> --- M src/soc/intel/common/block/cse/cse_lite.c M src/soc/intel/common/block/include/intelblocks/cse.h 2 files changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/86153/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/86153?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If1e4180cb5fec3990fdee2b0e412173b1c8c6ded Gerrit-Change-Number: 86153 Gerrit-PatchSet: 7 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com>

1 0

[S] Change in coreboot[main]: [only for test]Switch to C23
by Elyes Haouas (Code Review) 07 Feb '25

07 Feb '25

Elyes Haouas has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/86012?usp=email ) Change subject: [only for test]Switch to C23 ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/86012?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: abandon Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib4b2184e5c57143b11e3cc433d09d74a83028420 Gerrit-Change-Number: 86012 Gerrit-PatchSet: 3 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Jakub "Kuba" Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Maximilian Brune <maximilian.brune(a)9elements.com>

1 0

[M] Change in coreboot[main]: [This Must Fail]Upgrade GCC to 15-20250202 Snapshot
by Elyes Haouas (Code Review) 07 Feb '25

07 Feb '25

Elyes Haouas has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/86100?usp=email ) Change subject: [This Must Fail]Upgrade GCC to 15-20250202 Snapshot ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/86100?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: abandon Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5e6c3745eebeb6ded494c153010283b761498184 Gerrit-Change-Number: 86100 Gerrit-PatchSet: 5 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maximilian Brune <maximilian.brune(a)9elements.com>

1 0

[XS] Change in coreboot[main]: soc/intel/cmn/blk: Remove boot partition check for forced cse sync
by Dinesh Gehlot (Code Review) 07 Feb '25

07 Feb '25

Attention is currently required from: Intel coreboot Reviewers, Martin L Roth. Hello Intel coreboot Reviewers, Martin L Roth, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86153?usp=email to look at the new patch set (#6). Change subject: soc/intel/cmn/blk: Remove boot partition check for forced cse sync ...................................................................... soc/intel/cmn/blk: Remove boot partition check for forced cse sync This patch enhances the forced CSE sync mechanism by eliminating the boot partition check for RO. It utilizes the current CSE mechanism to determine if the system has undergone a cold boot. Please note, this is a proof of concept to address forced CSE sync constraint in the presence of a pre-CPU reset. The change is currently WIP and the final implementation might vary. BUG=b:380220737 TEST=Verified forced CSE sync on google/rex. Change-Id: If1e4180cb5fec3990fdee2b0e412173b1c8c6ded Signed-off-by: Dinesh Gehlot <digehlot(a)google.com> --- M src/soc/intel/common/block/cse/cse_lite.c M src/soc/intel/common/block/include/intelblocks/cse.h 2 files changed, 7 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/86153/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/86153?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If1e4180cb5fec3990fdee2b0e412173b1c8c6ded Gerrit-Change-Number: 86153 Gerrit-PatchSet: 6 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com>

1 0

[XS] Change in coreboot[main]: lib: Add low battery UX locale message
by Subrata Banik (Code Review) 07 Feb '25

07 Feb '25

Attention is currently required from: Jérémy Compostella, Karthik Ramasubramanian, Subrata Banik. Hello Jérémy Compostella, Karthik Ramasubramanian, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86284?usp=email to look at the new patch set (#5). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: lib: Add low battery UX locale message ...................................................................... lib: Add low battery UX locale message This commit adds a new UX locale message to display a warning when the battery is critically low. The message informs the user about the low battery and indicates that the system is shutting down. This change ensures that users are notified before the system unexpectedly shuts down due to low battery. BUG=b:339673254 TEST=Built and booted google/brox. Change-Id: I75c7a0d4d439901098c7f17a1dc90355307116ac Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/include/ux_locales.h M src/lib/ux_locales.c 2 files changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/86284/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/86284?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I75c7a0d4d439901098c7f17a1dc90355307116ac Gerrit-Change-Number: 86284 Gerrit-PatchSet: 5 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com>

1 0

[XS] Change in coreboot[main]: soc/intel/alderlake: Display low battery message on screen
by Subrata Banik (Code Review) 07 Feb '25

07 Feb '25

Attention is currently required from: Dinesh Gehlot, Intel coreboot Reviewers, Jayvik Desai, Julius Werner, Jérémy Compostella, Kapil Porwal, Karthik Ramasubramanian, Nick Vaccaro. Hello Dinesh Gehlot, Intel coreboot Reviewers, Jayvik Desai, Julius Werner, Jérémy Compostella, Kapil Porwal, Karthik Ramasubramanian, Nick Vaccaro, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86224?usp=email to look at the new patch set (#8). The following approvals got outdated and were removed: Code-Review+2 by Julius Werner, Verified+1 by build bot (Jenkins) The change is no longer submittable: Code-Review and Verified are unsatisfied now. Change subject: soc/intel/alderlake: Display low battery message on screen ...................................................................... soc/intel/alderlake: Display low battery message on screen This commit adds a function ux_inform_user_of_poweroff_operation to display a message on the screen when the system is powering off due to critically low battery. The message is centered on the screen and displays a localized string "Battery critically low. Shutting down.". If no localized string is found, a default English message is displayed. This implementation relies on CHROMEOS_ENABLE_ESOL Kconfig which is used to render text message for early sign-of-life. BUG=b:339673254 TEST=Able to capture the eventlog for low battery boot event. Change-Id: I3b24d2c89ade8cc62b7e47c487d52d47b7f3376d Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/soc/intel/alderlake/romstage/ux.c M src/soc/intel/alderlake/romstage/ux.h 2 files changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/86224/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/86224?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3b24d2c89ade8cc62b7e47c487d52d47b7f3376d Gerrit-Change-Number: 86224 Gerrit-PatchSet: 8 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com>

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit February 2025