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Change subject: soc/mediatek/mt8196: Set the driving strength of SPMI-P to maximum
......................................................................
Patch Set 3: Code-Review+2
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/86341/comment/231268c7_fef3ac12?us… :
PS3, Line 10: a hardware solution is also required.
a hardware solution of external pull-down is also required.
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Change subject: soc/mediatek/mt8196: Remove tvdpll3 disable/enable
......................................................................
soc/mediatek/mt8196: Remove tvdpll3 disable/enable
The enable operation cause tvdpll3 cannot be disabled during suspend,
so we remove it.
tvdpll3 can be enabled/disabled according to its downstream clock
demand automatically.
BRANCH=rauru
BUG=b:377628718
TEST=Bootup OK and Suspend/Resume OK, with MMinfra kernel/vcp patch,
mminfra can be turned off to reduce power consumption.
Signed-off-by: Guangjie Song <guangjie.song(a)mediatek.com>
Change-Id: Ib9c72a1602c1f76dc94cca5c4a61a542a853560b
---
M src/soc/mediatek/mt8196/pll.c
1 file changed, 0 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/86343/1
diff --git a/src/soc/mediatek/mt8196/pll.c b/src/soc/mediatek/mt8196/pll.c
index 59a9b09..2007197 100644
--- a/src/soc/mediatek/mt8196/pll.c
+++ b/src/soc/mediatek/mt8196/pll.c
@@ -1572,11 +1572,7 @@
{
const struct pll *pll = &plls[CLK_APMIXED2_TVDPLL3];
- clrbits32(pll->reg, MT8196_PLL_EN);
pll_set_rate(pll, freq);
- setbits32(pll->reg, MT8196_PLL_EN);
-
- udelay(PLL_EN_DELAY);
}
void mt_pll_edp_mux_set_sel(u32 sel)
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Change subject: soc/mediatek/mt8196: Set the driving strength of SPMI-P to maximum
......................................................................
soc/mediatek/mt8196: Set the driving strength of SPMI-P to maximum
To fix the SPMI-P glitch, the driving strength of SPMI-P needs to be set
to maximum. Additionally, a hardware solution is also required.
BRANCH=rauru
TEST=Build passed and booted successfully. The platform remained idle
for approximately 20 hours without hang.
BUG=b:383634290
Signed-off-by: Lu Tang <lu.tang(a)mediatek.corp-partner.google.com>
Change-Id: I131fd04c0313c7ed64bbd123f61d9a6849c8def4
---
M src/soc/mediatek/mt8196/pmif_spmi.c
1 file changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/86341/3
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Change subject: soc/mediatek/mt8196: Set the driving strength of SPMI-P to maximum
......................................................................
soc/mediatek/mt8196: Set the driving strength of SPMI-P to maximum
To fix the SPMI-P glitch, the driving strength of SPMI-P needs to be set
to maximum. Additionally, a hardware solution is also required.
BRANCH=rauru
TEST=Build pass and boot ok
BUG=b:383634290
Signed-off-by: Lu Tang <lu.tang(a)mediatek.corp-partner.google.com>
Change-Id: I131fd04c0313c7ed64bbd123f61d9a6849c8def4
---
M src/soc/mediatek/mt8196/pmif_spmi.c
1 file changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/86341/2
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Change subject: soc/intel/cmn/pmc: Add support for early power off
......................................................................
Patch Set 3: Code-Review+1
(1 comment)
Patchset:
PS2:
> > AIUI, the problem here is that the PCH doesn't want to power off in early stages, so the workaroun […]
Ack
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Change subject: soc/intel/cmn/pmc: Add support for early power off
......................................................................
Patch Set 3:
(2 comments)
Patchset:
PS2:
> AIUI, the problem here is that the PCH doesn't want to power off in early stages, so the workaround is to tell the EC (in this case, chromeec) to power off the platform instead
Based on my understanding, Intel chipset design doesn't support early power-off (before memory init or even before silicon init) therefore, we need an alternative to power off which doesn't rely on chipset registers.
Commit Message:
https://review.coreboot.org/c/coreboot/+/86336/comment/f886c8c7_17bf1f62?us… :
PS2, Line 10: alongwith
> nit: along with
Acknowledged
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Change subject: soc/intel/cmn/pmc: Add support for early power off
......................................................................
soc/intel/cmn/pmc: Add support for early power off
This commit adds support for early power off on Intel platforms
along with existing PMC based implementation to support power off
at later stage (like ramsatge).
A new function, `platform_do_early_poweroff`, is added to the
pmclib to handle platform-specific early power off procedures.
This function is called before memory initialization (in romstage or
earlier).
A weak default implementation is provided which prints an error message
and halts the system if EC_GOOGLE_CHROMEEC Kconfig not present.
Otherwise call into `google_chromeec_do_early_poweroff` to power off
the platform.
BUG=b:339673254
TEST=Able to build and boot google/brox.
Change-Id: I39f516640b3f75ab4c6a09826922289c0533f79b
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
---
M src/soc/intel/common/block/include/intelblocks/pmclib.h
M src/soc/intel/common/block/pmc/pmclib.c
2 files changed, 39 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/86336/3
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Jarried Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86341?usp=email )
Change subject: soc/mediatek/mt8196: Set the driving strength of SPMI-P to maximum
......................................................................
soc/mediatek/mt8196: Set the driving strength of SPMI-P to maximum
To fix the SPMI-P glitch, the driving strength of SPMI-P needs to be set
to maximum. Additionally, a hardware solution is also required.
TEST=Build pass and boot ok
BUG=b:383634290
Signed-off-by: Lu Tang <lu.tang(a)mediatek.corp-partner.google.com>
Change-Id: I131fd04c0313c7ed64bbd123f61d9a6849c8def4
---
M src/soc/mediatek/mt8196/pmif_spmi.c
1 file changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/86341/1
diff --git a/src/soc/mediatek/mt8196/pmif_spmi.c b/src/soc/mediatek/mt8196/pmif_spmi.c
index c4a984f..bec3374 100644
--- a/src/soc/mediatek/mt8196/pmif_spmi.c
+++ b/src/soc/mediatek/mt8196/pmif_spmi.c
@@ -166,8 +166,8 @@
gpio_set_driving(GPIO(SPMI_M_SCL), GPIO_DRV_10_MA);
gpio_set_driving(GPIO(SPMI_M_SDA), GPIO_DRV_10_MA);
/* SPMI_P 14mA */
- gpio_set_driving(GPIO(SPMI_P_SCL), GPIO_DRV_14_MA);
- gpio_set_driving(GPIO(SPMI_P_SDA), GPIO_DRV_14_MA);
+ gpio_set_driving(GPIO(SPMI_P_SCL), GPIO_DRV_16_MA);
+ gpio_set_driving(GPIO(SPMI_P_SDA), GPIO_DRV_16_MA);
/* SPMI-P set Pull-Down mode */
gpio_set_pull(GPIO(SPMI_P_SCL), GPIO_PULL_ENABLE, GPIO_PULL_DOWN);
gpio_set_pull(GPIO(SPMI_P_SDA), GPIO_PULL_ENABLE, GPIO_PULL_DOWN);
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Change subject: soc/intel/cmn/pmc: Add support for early power off
......................................................................
Patch Set 2: Code-Review+1
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