coreboot-gerrit February 2025

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[XS] Change in coreboot[main]: soc/mediatek/mt8196: Set the driving strength of SPMI-P to maximum
by Yidi Lin (Code Review) 10 Feb '25

10 Feb '25

Attention is currently required from: Hung-Te Lin, Jarried Lin, Yu-Ping Wu. Yidi Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/86341?usp=email ) Change subject: soc/mediatek/mt8196: Set the driving strength of SPMI-P to maximum ...................................................................... Patch Set 3: Code-Review+2 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/86341/comment/231268c7_fef3ac12?us… : PS3, Line 10: a hardware solution is also required. a hardware solution of external pull-down is also required. -- To view, visit https://review.coreboot.org/c/coreboot/+/86341?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I131fd04c0313c7ed64bbd123f61d9a6849c8def4 Gerrit-Change-Number: 86341 Gerrit-PatchSet: 3 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Mon, 10 Feb 2025 07:46:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: soc/mediatek/mt8196: Remove tvdpll3 disable/enable
by Jarried Lin (Code Review) 10 Feb '25

10 Feb '25

Attention is currently required from: Hung-Te Lin, Yidi Lin, Yu-Ping Wu. Jarried Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86343?usp=email ) Change subject: soc/mediatek/mt8196: Remove tvdpll3 disable/enable ...................................................................... soc/mediatek/mt8196: Remove tvdpll3 disable/enable The enable operation cause tvdpll3 cannot be disabled during suspend, so we remove it. tvdpll3 can be enabled/disabled according to its downstream clock demand automatically. BRANCH=rauru BUG=b:377628718 TEST=Bootup OK and Suspend/Resume OK, with MMinfra kernel/vcp patch, mminfra can be turned off to reduce power consumption. Signed-off-by: Guangjie Song <guangjie.song(a)mediatek.com> Change-Id: Ib9c72a1602c1f76dc94cca5c4a61a542a853560b --- M src/soc/mediatek/mt8196/pll.c 1 file changed, 0 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/86343/1 diff --git a/src/soc/mediatek/mt8196/pll.c b/src/soc/mediatek/mt8196/pll.c index 59a9b09..2007197 100644 --- a/src/soc/mediatek/mt8196/pll.c +++ b/src/soc/mediatek/mt8196/pll.c @@ -1572,11 +1572,7 @@ { const struct pll *pll = &plls[CLK_APMIXED2_TVDPLL3]; - clrbits32(pll->reg, MT8196_PLL_EN); pll_set_rate(pll, freq); - setbits32(pll->reg, MT8196_PLL_EN); - - udelay(PLL_EN_DELAY); } void mt_pll_edp_mux_set_sel(u32 sel) -- To view, visit https://review.coreboot.org/c/coreboot/+/86343?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib9c72a1602c1f76dc94cca5c4a61a542a853560b Gerrit-Change-Number: 86343 Gerrit-PatchSet: 1 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com>

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[XS] Change in coreboot[main]: soc/mediatek/mt8196: Correct MMinfra vote register
by Jarried Lin (Code Review) 10 Feb '25

10 Feb '25

Jarried Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86342?usp=email ) Change subject: soc/mediatek/mt8196: Correct MMinfra vote register ...................................................................... soc/mediatek/mt8196: Correct MMinfra vote register Correct MMinfra vote register to fix MMinfra power off fail during suspend. BRANCH=rauru BUG=b:377628718 TEST=Bootup OK and Suspend/Resume OK, with MMinfra kernel/vcp patch, mminfra can be turned off to reduce power consumption. Signed-off-by: Guangjie Song <guangjie.song(a)mediatek.com> Change-Id: I7c23c3c53c68b0de85d8b6189b685de7f8398e8b --- M src/soc/mediatek/mt8196/mtcmos.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/86342/1 diff --git a/src/soc/mediatek/mt8196/mtcmos.c b/src/soc/mediatek/mt8196/mtcmos.c index 367e74b..e274be8 100644 --- a/src/soc/mediatek/mt8196/mtcmos.c +++ b/src/soc/mediatek/mt8196/mtcmos.c @@ -42,8 +42,8 @@ #define MMVOTE_MTCMOS_1_CLR ((void *)(MMVOTE_BASE + 0x0224)) #define MMVOTE_MTCMOS_1_DONE ((void *)(MMVOTE_BASE + 0x142C)) #define MMVOTE_MTCMOS_1_PM_ACK ((void *)(MMVOTE_BASE + 0x5518)) -#define MMINFRA_MTCMOS_1_SET ((void *)(MMVOTE_BASE + 0x43220)) -#define MMINFRA_MTCMOS_1_CLR ((void *)(MMVOTE_BASE + 0x43224)) +#define MMINFRA_MTCMOS_1_SET ((void *)(MMVOTE_BASE + 0x20220)) +#define MMINFRA_MTCMOS_1_CLR ((void *)(MMVOTE_BASE + 0x20224)) #define DISP_VDISP_AO_CONFIG_CG 0x3E800108 #define DISP_DPC_DISP0_MTCMOS_CFG 0x3E8F0500 -- To view, visit https://review.coreboot.org/c/coreboot/+/86342?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7c23c3c53c68b0de85d8b6189b685de7f8398e8b Gerrit-Change-Number: 86342 Gerrit-PatchSet: 1 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com>

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[XS] Change in coreboot[main]: soc/mediatek/mt8196: Set the driving strength of SPMI-P to maximum
by Jarried Lin (Code Review) 10 Feb '25

10 Feb '25

Attention is currently required from: Hung-Te Lin, Yidi Lin, Yu-Ping Wu. Hello Hung-Te Lin, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86341?usp=email to look at the new patch set (#3). Change subject: soc/mediatek/mt8196: Set the driving strength of SPMI-P to maximum ...................................................................... soc/mediatek/mt8196: Set the driving strength of SPMI-P to maximum To fix the SPMI-P glitch, the driving strength of SPMI-P needs to be set to maximum. Additionally, a hardware solution is also required. BRANCH=rauru TEST=Build passed and booted successfully. The platform remained idle for approximately 20 hours without hang. BUG=b:383634290 Signed-off-by: Lu Tang <lu.tang(a)mediatek.corp-partner.google.com> Change-Id: I131fd04c0313c7ed64bbd123f61d9a6849c8def4 --- M src/soc/mediatek/mt8196/pmif_spmi.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/86341/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/86341?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I131fd04c0313c7ed64bbd123f61d9a6849c8def4 Gerrit-Change-Number: 86341 Gerrit-PatchSet: 3 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com>

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[XS] Change in coreboot[main]: soc/mediatek/mt8196: Set the driving strength of SPMI-P to maximum
by Jarried Lin (Code Review) 09 Feb '25

09 Feb '25

Attention is currently required from: Hung-Te Lin, Yidi Lin, Yu-Ping Wu. Hello Hung-Te Lin, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86341?usp=email to look at the new patch set (#2). Change subject: soc/mediatek/mt8196: Set the driving strength of SPMI-P to maximum ...................................................................... soc/mediatek/mt8196: Set the driving strength of SPMI-P to maximum To fix the SPMI-P glitch, the driving strength of SPMI-P needs to be set to maximum. Additionally, a hardware solution is also required. BRANCH=rauru TEST=Build pass and boot ok BUG=b:383634290 Signed-off-by: Lu Tang <lu.tang(a)mediatek.corp-partner.google.com> Change-Id: I131fd04c0313c7ed64bbd123f61d9a6849c8def4 --- M src/soc/mediatek/mt8196/pmif_spmi.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/86341/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86341?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I131fd04c0313c7ed64bbd123f61d9a6849c8def4 Gerrit-Change-Number: 86341 Gerrit-PatchSet: 2 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com>

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[S] Change in coreboot[main]: soc/intel/cmn/pmc: Add support for early power off
by Angel Pons (Code Review) 09 Feb '25

09 Feb '25

Attention is currently required from: Intel coreboot Reviewers, Julius Werner, Karthik Ramasubramanian, Subrata Banik. Angel Pons has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/86336?usp=email ) Change subject: soc/intel/cmn/pmc: Add support for early power off ...................................................................... Patch Set 3: Code-Review+1 (1 comment) Patchset: PS2: > > AIUI, the problem here is that the PCH doesn't want to power off in early stages, so the workaroun […] Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/86336?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I39f516640b3f75ab4c6a09826922289c0533f79b Gerrit-Change-Number: 86336 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Mon, 10 Feb 2025 05:28:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com>

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[S] Change in coreboot[main]: soc/intel/cmn/pmc: Add support for early power off
by Subrata Banik (Code Review) 09 Feb '25

09 Feb '25

Attention is currently required from: Angel Pons, Intel coreboot Reviewers, Julius Werner, Karthik Ramasubramanian. Subrata Banik has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/86336?usp=email ) Change subject: soc/intel/cmn/pmc: Add support for early power off ...................................................................... Patch Set 3: (2 comments) Patchset: PS2: > AIUI, the problem here is that the PCH doesn't want to power off in early stages, so the workaround is to tell the EC (in this case, chromeec) to power off the platform instead Based on my understanding, Intel chipset design doesn't support early power-off (before memory init or even before silicon init) therefore, we need an alternative to power off which doesn't rely on chipset registers. Commit Message: https://review.coreboot.org/c/coreboot/+/86336/comment/f886c8c7_17bf1f62?us… : PS2, Line 10: alongwith > nit: along with Acknowledged -- To view, visit https://review.coreboot.org/c/coreboot/+/86336?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I39f516640b3f75ab4c6a09826922289c0533f79b Gerrit-Change-Number: 86336 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Mon, 10 Feb 2025 05:21:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com>

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[S] Change in coreboot[main]: soc/intel/cmn/pmc: Add support for early power off
by Subrata Banik (Code Review) 09 Feb '25

09 Feb '25

Attention is currently required from: Intel coreboot Reviewers, Julius Werner, Karthik Ramasubramanian, Subrata Banik. Hello Angel Pons, Intel coreboot Reviewers, Julius Werner, Karthik Ramasubramanian, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86336?usp=email to look at the new patch set (#3). Change subject: soc/intel/cmn/pmc: Add support for early power off ...................................................................... soc/intel/cmn/pmc: Add support for early power off This commit adds support for early power off on Intel platforms along with existing PMC based implementation to support power off at later stage (like ramsatge). A new function, `platform_do_early_poweroff`, is added to the pmclib to handle platform-specific early power off procedures. This function is called before memory initialization (in romstage or earlier). A weak default implementation is provided which prints an error message and halts the system if EC_GOOGLE_CHROMEEC Kconfig not present. Otherwise call into `google_chromeec_do_early_poweroff` to power off the platform. BUG=b:339673254 TEST=Able to build and boot google/brox. Change-Id: I39f516640b3f75ab4c6a09826922289c0533f79b Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/soc/intel/common/block/include/intelblocks/pmclib.h M src/soc/intel/common/block/pmc/pmclib.c 2 files changed, 39 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/86336/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/86336?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I39f516640b3f75ab4c6a09826922289c0533f79b Gerrit-Change-Number: 86336 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com>

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[XS] Change in coreboot[main]: soc/mediatek/mt8196: Set the driving strength of SPMI-P to maximum
by Jarried Lin (Code Review) 09 Feb '25

09 Feb '25

Jarried Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86341?usp=email ) Change subject: soc/mediatek/mt8196: Set the driving strength of SPMI-P to maximum ...................................................................... soc/mediatek/mt8196: Set the driving strength of SPMI-P to maximum To fix the SPMI-P glitch, the driving strength of SPMI-P needs to be set to maximum. Additionally, a hardware solution is also required. TEST=Build pass and boot ok BUG=b:383634290 Signed-off-by: Lu Tang <lu.tang(a)mediatek.corp-partner.google.com> Change-Id: I131fd04c0313c7ed64bbd123f61d9a6849c8def4 --- M src/soc/mediatek/mt8196/pmif_spmi.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/86341/1 diff --git a/src/soc/mediatek/mt8196/pmif_spmi.c b/src/soc/mediatek/mt8196/pmif_spmi.c index c4a984f..bec3374 100644 --- a/src/soc/mediatek/mt8196/pmif_spmi.c +++ b/src/soc/mediatek/mt8196/pmif_spmi.c @@ -166,8 +166,8 @@ gpio_set_driving(GPIO(SPMI_M_SCL), GPIO_DRV_10_MA); gpio_set_driving(GPIO(SPMI_M_SDA), GPIO_DRV_10_MA); /* SPMI_P 14mA */ - gpio_set_driving(GPIO(SPMI_P_SCL), GPIO_DRV_14_MA); - gpio_set_driving(GPIO(SPMI_P_SDA), GPIO_DRV_14_MA); + gpio_set_driving(GPIO(SPMI_P_SCL), GPIO_DRV_16_MA); + gpio_set_driving(GPIO(SPMI_P_SDA), GPIO_DRV_16_MA); /* SPMI-P set Pull-Down mode */ gpio_set_pull(GPIO(SPMI_P_SCL), GPIO_PULL_ENABLE, GPIO_PULL_DOWN); gpio_set_pull(GPIO(SPMI_P_SDA), GPIO_PULL_ENABLE, GPIO_PULL_DOWN); -- To view, visit https://review.coreboot.org/c/coreboot/+/86341?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I131fd04c0313c7ed64bbd123f61d9a6849c8def4 Gerrit-Change-Number: 86341 Gerrit-PatchSet: 1 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com>

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[S] Change in coreboot[main]: soc/intel/cmn/pmc: Add support for early power off
by Angel Pons (Code Review) 09 Feb '25

09 Feb '25

Attention is currently required from: Intel coreboot Reviewers, Julius Werner, Karthik Ramasubramanian, Subrata Banik. Angel Pons has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/86336?usp=email ) Change subject: soc/intel/cmn/pmc: Add support for early power off ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/86336?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I39f516640b3f75ab4c6a09826922289c0533f79b Gerrit-Change-Number: 86336 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Mon, 10 Feb 2025 05:18:28 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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coreboot-gerrit February 2025