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Change subject: soc/mediatek/mt8196: Set the driving strength of SPMI-P to maximum
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Patch Set 4: Code-Review+2
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Change subject: mb/novacustom: add V5x0TU board (Meteor Lake)
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Patch Set 26: Code-Review+2
(1 comment)
File src/mainboard/novacustom/mtl-h/Kconfig:
https://review.coreboot.org/c/coreboot/+/82673/comment/9d9a0895_2a48a122?us… :
PS26, Line 22: select SOC_INTEL_METEORLAKE_U_H
> Only binaries for IoT are available in the FSP repo still, and that FSP does not work well on this p […]
Acknowledged
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Change subject: mb/novacustom: add V5x0TU board (Meteor Lake)
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Patch Set 26:
(1 comment)
File src/mainboard/novacustom/mtl-h/Kconfig:
https://review.coreboot.org/c/coreboot/+/82673/comment/87ceaf8f_4eafe972?us… :
PS26, Line 22: select SOC_INTEL_METEORLAKE_U_H
> Does it work with public FSP binaries? If yes, then probably `ADD_FSP_BINARIES` should be added.
Only binaries for IoT are available in the FSP repo still, and that FSP does not work well on this platform. It has been a while since I tested it but there were S0ix issues among others
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Change subject: mb/novacustom: add V5x0TU board (Meteor Lake)
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Patch Set 26:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/82673/comment/5f648c62_d050f6e3?us… :
PS21, Line 17: - DDR5 SODIMM in slot RAM2
> RAM1 slot works, but needs CB:52731 and CB:82733
Acknowledged
File src/mainboard/novacustom/mtl-h/Kconfig:
https://review.coreboot.org/c/coreboot/+/82673/comment/6f60a455_117bb716?us… :
PS26, Line 22: select SOC_INTEL_METEORLAKE_U_H
Does it work with public FSP binaries? If yes, then probably `ADD_FSP_BINARIES` should be added.
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Hello Intel coreboot Reviewers, Kapil Porwal, Pranava Y N, Subrata Banik, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Change subject: soc/intel/ptl: Disable FSP_UGOP_EARLY_SIGN_OF_LIFE for pantherlake
......................................................................
soc/intel/ptl: Disable FSP_UGOP_EARLY_SIGN_OF_LIFE for pantherlake
This patch disables eSOL Kconfig until the feature is ready in PTL
FSP-uGOP binary.
TEST=Able to build and boot google/fatcat to OS.
Change-Id: I99dd516816995b6cdfdcec618c06c7dbe061718a
Signed-off-by: Jayvik Desai <jayvik(a)google.com>
---
M src/soc/intel/pantherlake/Kconfig
1 file changed, 0 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/86314/3
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Change subject: mb/google/fatcat: Add power limits for additional PTL-H variants
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Patch Set 1: Code-Review+2
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Change subject: soc/mediatek/mt8196: Correct MMinfra vote register
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Patch Set 2:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/86342/comment/65bb8a5c_74626f04?us… :
PS1, Line 9: fail
> failure
Done
https://review.coreboot.org/c/coreboot/+/86342/comment/1920fe68_9402ce2c?us… :
PS1, Line 15: reduce power consumption.
> do we have a delta ?
Done
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Change subject: soc/mediatek/mt8196: Set the driving strength of SPMI-P to maximum
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Patch Set 4:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/86341/comment/09ca8551_8af96633?us… :
PS3, Line 10: a hardware solution is also required.
> a hardware solution of external pull-down is also required.
Done
https://review.coreboot.org/c/coreboot/+/86341/comment/e637a889_ae64aebf?us… :
PS3, Line 10: maximum
> a maximum value of 16mA
Done
File src/soc/mediatek/mt8196/pmif_spmi.c:
https://review.coreboot.org/c/coreboot/+/86341/comment/1dcbd165_f6999779?us… :
PS3, Line 168: 14
> 16
Done
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