coreboot-gerrit January 2025

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[M] Change in coreboot[main]: libpayload: Unify selfboot() implementations
by Julius Werner (Code Review) 24 Jan '25

24 Jan '25

Julius Werner has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86142?usp=email ) Change subject: libpayload: Unify selfboot() implementations ...................................................................... libpayload: Unify selfboot() implementations selfboot() doesn't really need to be architecture dependent. All architectures are essentially doing the same thing with a normal function call, only x86_32 needs an extra attribute. arm64 and x86 also previously haven't been passing the coreboot table pointer, even though they should. This patch fixes that. Change-Id: If14040e38d968b5eea31cd6cd25efb1845a7b081 Signed-off-by: Julius Werner <jwerner(a)chromium.org> --- M payloads/libpayload/arch/arm/Makefile.mk M payloads/libpayload/arch/arm64/Makefile.mk D payloads/libpayload/arch/arm64/selfboot.c M payloads/libpayload/arch/x86/Makefile.mk D payloads/libpayload/arch/x86/selfboot.c M payloads/libpayload/libc/Makefile.mk R payloads/libpayload/libc/selfboot.c 7 files changed, 8 insertions(+), 78 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/86142/1 diff --git a/payloads/libpayload/arch/arm/Makefile.mk b/payloads/libpayload/arch/arm/Makefile.mk index 47c271b..3308135 100644 --- a/payloads/libpayload/arch/arm/Makefile.mk +++ b/payloads/libpayload/arch/arm/Makefile.mk @@ -39,7 +39,6 @@ libc-y += virtual.c libc-y += exception_asm.S exception.c libc-y += cache.c cpu.S -libc-y += selfboot.c # Will fall back to default_memXXX() in libc/memory.c if GPL not allowed. libc-$(CONFIG_LP_GPL) += memcpy.S memset.S memmove.S diff --git a/payloads/libpayload/arch/arm64/Makefile.mk b/payloads/libpayload/arch/arm64/Makefile.mk index d6cc51e..a4fda1d 100644 --- a/payloads/libpayload/arch/arm64/Makefile.mk +++ b/payloads/libpayload/arch/arm64/Makefile.mk @@ -36,7 +36,6 @@ libc-y += memcpy.S memset.S memmove.S libc-y += exception_asm.S exception.c libc-y += cache.c cpu.S -libc-y += selfboot.c libc-y += mmu.c libgdb-y += gdb.c diff --git a/payloads/libpayload/arch/arm64/selfboot.c b/payloads/libpayload/arch/arm64/selfboot.c deleted file mode 100644 index 5c3e445..0000000 --- a/payloads/libpayload/arch/arm64/selfboot.c +++ /dev/null @@ -1,34 +0,0 @@ -/* - * Copyright 2014 Google Inc. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#include <libpayload.h> - -void selfboot(void *entry) -{ - void (*entry_func)(void) = entry; - entry_func(); -} diff --git a/payloads/libpayload/arch/x86/Makefile.mk b/payloads/libpayload/arch/x86/Makefile.mk index 35e69cb..b2aaacc 100644 --- a/payloads/libpayload/arch/x86/Makefile.mk +++ b/payloads/libpayload/arch/x86/Makefile.mk @@ -40,7 +40,7 @@ libc-y += main.c sysinfo.c libc-y += timer.c coreboot.c util.S libc-y += virtual.c -libc-y += selfboot.c cache.c +libc-y += cache.c libc-y += exception.c libc-y += delay.c libc-$(CONFIG_LP_ARCH_X86_32) += exec.c diff --git a/payloads/libpayload/arch/x86/selfboot.c b/payloads/libpayload/arch/x86/selfboot.c deleted file mode 100644 index 5c3e445..0000000 --- a/payloads/libpayload/arch/x86/selfboot.c +++ /dev/null @@ -1,34 +0,0 @@ -/* - * Copyright 2014 Google Inc. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#include <libpayload.h> - -void selfboot(void *entry) -{ - void (*entry_func)(void) = entry; - entry_func(); -} diff --git a/payloads/libpayload/libc/Makefile.mk b/payloads/libpayload/libc/Makefile.mk index 3d070eb..063118a 100644 --- a/payloads/libpayload/libc/Makefile.mk +++ b/payloads/libpayload/libc/Makefile.mk @@ -38,6 +38,7 @@ libc-$(CONFIG_LP_LIBC) += coreboot.c libc-$(CONFIG_LP_LIBC) += fmap.c libc-$(CONFIG_LP_LIBC) += fpmath.c +libc-$(CONFIG_LP_LIBC) += selfboot.c ifeq ($(CONFIG_LP_VBOOT_LIB),y) libc-$(CONFIG_LP_LIBC) += lp_vboot.c diff --git a/payloads/libpayload/arch/arm/selfboot.c b/payloads/libpayload/libc/selfboot.c similarity index 89% rename from payloads/libpayload/arch/arm/selfboot.c rename to payloads/libpayload/libc/selfboot.c index 70cc79e..3e226b4 100644 --- a/payloads/libpayload/arch/arm/selfboot.c +++ b/payloads/libpayload/libc/selfboot.c @@ -1,5 +1,5 @@ /* - * Copyright 2014 Google Inc. + * Copyright 2025 Google LLC * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -31,10 +31,9 @@ void selfboot(void *entry) { - __asm__ __volatile__( - "mov r0, %[cb_header_ptr]\n" - "bx %[entry]\n" - :: [cb_header_ptr]"r"(cb_header_ptr), [entry]"r"(entry) - : "r0" - ); +#if CONFIG(LP_ARCH_X86_32) + __attribute__((__regparm__(0))) +#endif + void (*entry_func)(void *arg) = entry; + entry_func(cb_header_ptr); } -- To view, visit https://review.coreboot.org/c/coreboot/+/86142?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If14040e38d968b5eea31cd6cd25efb1845a7b081 Gerrit-Change-Number: 86142 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org>

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[XS] Change in coreboot[main]: soc/intel/alderlake: Fix incorrect reporting of S0ix
by Jérémy Compostella (Code Review) 24 Jan '25

24 Jan '25

Attention is currently required from: Dinesh Gehlot, Intel coreboot Reviewers, Jayvik Desai, Kapil Porwal, Matt DeVillier, Nick Vaccaro, Paul Menzel, Sean Rhodes. Jérémy Compostella has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/86089?usp=email ) Change subject: soc/intel/alderlake: Fix incorrect reporting of S0ix ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: > Just in case I'm missing something, why just those two? I found only four occurrences of this function. You are taking care of one. We are left with meteorlake, pantherlake and tigerlake. Those three would be better. -- To view, visit https://review.coreboot.org/c/coreboot/+/86089?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia31fbfd0b9795990b0ca98220bb002bf2c3857b2 Gerrit-Change-Number: 86089 Gerrit-PatchSet: 3 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Fri, 24 Jan 2025 00:22:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sean Rhodes <sean(a)starlabs.systems> Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com>

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[XS] Change in coreboot[main]: lib/crc_byte: Parenthesize buffer address in CRC macro
by Matt DeVillier (Code Review) 24 Jan '25

24 Jan '25

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86099?usp=email ) Change subject: lib/crc_byte: Parenthesize buffer address in CRC macro ...................................................................... lib/crc_byte: Parenthesize buffer address in CRC macro This change fixes CRC calculations in cases where an expression calculating the address using pointer arithmetic is passed into the macro. Change-Id: I55bbd2f208a94068ea3b3b3ae97b1683434c3007 Signed-off-by: Filip Brozovic <fbrozovic(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86099 Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- M src/include/crc_byte.h 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: Julius Werner: Looks good to me, approved Matt DeVillier: Looks good to me, approved Angel Pons: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/include/crc_byte.h b/src/include/crc_byte.h index 85b7221..972b89a 100644 --- a/src/include/crc_byte.h +++ b/src/include/crc_byte.h @@ -35,7 +35,7 @@ uint32_t crc32_byte(uint32_t prev_crc, uint8_t data); #define CRC(buf, size, crc_func) ({ \ - const uint8_t *_crc_local_buf = (const uint8_t *)buf; \ + const uint8_t *_crc_local_buf = (const uint8_t *)(buf); \ size_t _crc_local_size = size; \ __typeof__(crc_func(0, 0)) _crc_local_result = 0; \ while (_crc_local_size--) { \ -- To view, visit https://review.coreboot.org/c/coreboot/+/86099?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I55bbd2f208a94068ea3b3b3ae97b1683434c3007 Gerrit-Change-Number: 86099 Gerrit-PatchSet: 3 Gerrit-Owner: Filip Brozovic <fbrozovic(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: soc/intel/common: Add Panther Lake DTT support
by Jamie Ryu (Code Review) 23 Jan '25

23 Jan '25

Attention is currently required from: Deepika Punyamurtula, Intel coreboot Reviewers, Jérémy Compostella. Jamie Ryu has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/86118?usp=email ) Change subject: soc/intel/common: Add Panther Lake DTT support ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86118?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia8dbe86efdf341a629de037d37750b79395ec3e8 Gerrit-Change-Number: 86118 Gerrit-PatchSet: 5 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Deepika Punyamurtula <deepika.punyamurtula(a)intel.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Deepika Punyamurtula <deepika.punyamurtula(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Comment-Date: Thu, 23 Jan 2025 21:57:56 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: drivers/intel/dptf: Suppress unnecessary static function
by Jamie Ryu (Code Review) 23 Jan '25

23 Jan '25

Attention is currently required from: Deepika Punyamurtula, Intel coreboot Reviewers, Jérémy Compostella. Jamie Ryu has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/86130?usp=email ) Change subject: drivers/intel/dptf: Suppress unnecessary static function ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86130?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0b9d150bab8486cb7e437d5e2b3caa880e14f886 Gerrit-Change-Number: 86130 Gerrit-PatchSet: 1 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Deepika Punyamurtula <deepika.punyamurtula(a)intel.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Deepika Punyamurtula <deepika.punyamurtula(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Comment-Date: Thu, 23 Jan 2025 21:56:16 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: drivers/intel/dptf: Suppress unnecessary static function
by Bora Guvendik (Code Review) 23 Jan '25

23 Jan '25

Attention is currently required from: Deepika Punyamurtula, Intel coreboot Reviewers, Jérémy Compostella. Bora Guvendik has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/86130?usp=email ) Change subject: drivers/intel/dptf: Suppress unnecessary static function ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86130?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0b9d150bab8486cb7e437d5e2b3caa880e14f886 Gerrit-Change-Number: 86130 Gerrit-PatchSet: 1 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Deepika Punyamurtula <deepika.punyamurtula(a)intel.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Deepika Punyamurtula <deepika.punyamurtula(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Comment-Date: Thu, 23 Jan 2025 21:56:00 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: soc/intel/common: Add Panther Lake DTT support
by Bora Guvendik (Code Review) 23 Jan '25

23 Jan '25

Attention is currently required from: Deepika Punyamurtula, Intel coreboot Reviewers, Jérémy Compostella. Bora Guvendik has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/86118?usp=email ) Change subject: soc/intel/common: Add Panther Lake DTT support ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86118?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia8dbe86efdf341a629de037d37750b79395ec3e8 Gerrit-Change-Number: 86118 Gerrit-PatchSet: 5 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Deepika Punyamurtula <deepika.punyamurtula(a)intel.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Deepika Punyamurtula <deepika.punyamurtula(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Comment-Date: Thu, 23 Jan 2025 21:54:30 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: MAINTAINERS: Add Matt as a maintainer for Star Labs
by Matt DeVillier (Code Review) 23 Jan '25

23 Jan '25

Attention is currently required from: Sean Rhodes. Matt DeVillier has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/86141?usp=email ) Change subject: MAINTAINERS: Add Matt as a maintainer for Star Labs ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86141?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I47f51645e4f8dd8e8da8e527fd498af570a857e4 Gerrit-Change-Number: 86141 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Comment-Date: Thu, 23 Jan 2025 21:14:54 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: cbfstool: Add hash to more than one region
by Julius Werner (Code Review) 23 Jan '25

23 Jan '25

Attention is currently required from: Bao Zheng, Felix Held, Marshall Dawson, Zheng Bao. Julius Werner has posted comments on this change by Bao Zheng. ( https://review.coreboot.org/c/coreboot/+/85468?usp=email ) Change subject: cbfstool: Add hash to more than one region ...................................................................... Patch Set 14: (1 comment) Patchset: PS1: > For the AB recovery, we are trying to make a duplicated copy of all the modules which is needed for […] Okay but how exactly does this differ from vboot with VBOOT_STARTS_BEFORE_BOOTBLOCK? Don't get hung up on the fact that one of the slots is called "RO", that's just naming convention. Just think of vboot's "RO" as the equivalent to your "A" slot, and vboot's "RW_A" as the equivalent to your "B" slot. (vboot's "RW_B" can be disabled in Kconfig.) It's still two slots in either case. With vboot on AMD platforms, romstage, ramstage, bootblock and payload are also duplicated across both slots. Only the PSP stage (verstage) is shared between the two slots. Does that differ from your solution? If even the first stage exists twice, then how does the SoC decide where to boot from? And even if that exists, maybe it would be possible to expand vboot in a way that supports that rather than building a completely separate system next to it? -- To view, visit https://review.coreboot.org/c/coreboot/+/85468?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8f9a5baa2699468380b942b3bdc104cab78adf5f Gerrit-Change-Number: 85468 Gerrit-PatchSet: 14 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 23 Jan 2025 21:11:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Bao Zheng <fishbaozi(a)gmail.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org>

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[XS] Change in coreboot[main]: mb/starlabs/byte_adl: Correct MODEM_CLKREQ configuration
by Sean Rhodes (Code Review) 23 Jan '25

23 Jan '25

Sean Rhodes has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/86136?usp=email ) Change subject: mb/starlabs/byte_adl: Correct MODEM_CLKREQ configuration ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/86136?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If9db29df2a0da71885556a75abcb1da1508a9308 Gerrit-Change-Number: 86136 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Comment-Date: Thu, 23 Jan 2025 21:09:20 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

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