coreboot-gerrit January 2025

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[S] Change in coreboot[main]: mb/asus/p8z77-v_lx2: Change super I/O chip to nct5535d
by Keith Hui (Code Review) 03 Jan '25

03 Jan '25

Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85835?usp=email ) Change subject: mb/asus/p8z77-v_lx2: Change super I/O chip to nct5535d ...................................................................... mb/asus/p8z77-v_lx2: Change super I/O chip to nct5535d Boardview indicates this board uses the smaller superio/nuvoton/nct5535d. Cut devices not present or remaining off from overridetree. Builds, but not function tested. Change-Id: Ie68f6f5b1be67ddabc8afee1dbd2db3c8b4f180b Signed-off-by: Keith Hui <buurin(a)gmail.com> --- M src/mainboard/asus/p8x7x-series/Kconfig M src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/overridetree.cb 2 files changed, 2 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/85835/1 diff --git a/src/mainboard/asus/p8x7x-series/Kconfig b/src/mainboard/asus/p8x7x-series/Kconfig index da3d10b..c3fb90c 100644 --- a/src/mainboard/asus/p8x7x-series/Kconfig +++ b/src/mainboard/asus/p8x7x-series/Kconfig @@ -38,7 +38,7 @@ select BOARD_ASUS_P8X7X_SERIES select BOARD_ROMSIZE_KB_8192 select REALTEK_8168_RESET - select SUPERIO_NUVOTON_NCT6779D + select SUPERIO_NUVOTON_NCT5535D select USE_NATIVE_RAMINIT select POWER_LED_USES_GPIO8 diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/overridetree.cb b/src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/overridetree.cb index 66bc5bb..66bc619 100644 --- a/src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/overridetree.cb +++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/overridetree.cb @@ -33,33 +33,23 @@ device ref pcie_rp8 on end # PCIEX1_2 device ref lpc on - chip superio/nuvoton/nct6779d - device pnp 2e.1 off end # Parallel + chip superio/nuvoton/nct5535d device pnp 2e.2 on # UART A io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 2e.3 off end # UART B, IR device pnp 2e.5 on # Keyboard io 0x60 = 0x0060 io 0x62 = 0x0064 irq 0x70 = 1 irq 0x72 = 12 end - device pnp 2e.6 off end # CIR device pnp 2e.7 off end # GPIO6-8 device pnp 2e.8 off end # WDT1, GPIO0, GPIO1 - device pnp 2e.108 off end # GPIO0 device pnp 2e.9 off end # GPIO8 - device pnp 2e.109 off end # GPIO1 device pnp 2e.209 on # GPIO2 irq 0xe0 = 0xff end - device pnp 2e.309 off end # GPIO3 - device pnp 2e.409 off end # GPIO4 - device pnp 2e.509 off end # GPIO5 - device pnp 2e.609 off end # GPIO6 - device pnp 2e.709 off end # GPIO7 device pnp 2e.a on end # ACPI device pnp 2e.b on # H/W Monitor, FP LED io 0x60 = 0x0290 -- To view, visit https://review.coreboot.org/c/coreboot/+/85835?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie68f6f5b1be67ddabc8afee1dbd2db3c8b4f180b Gerrit-Change-Number: 85835 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com>

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[L] Change in coreboot[main]: superio/nuvoton: Add NCT5535D
by Keith Hui (Code Review) 03 Jan '25

03 Jan '25

Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85834?usp=email ) Change subject: superio/nuvoton: Add NCT5535D ...................................................................... superio/nuvoton: Add NCT5535D NCT5535D is a 64-pin LPC super I/O chip found on many Asus P8x7x series mainboards with no publicly available datasheet. However, based on mb/asus/p8z77-v_lx2, this chip can probably be driven like a NCT6779D, on which this is based. Devices not present on this chip compared to NCT6779D are parallel port, serial port B, GPIOs 0,1,3,6. p8z77-v_lx2 still builds once modified for this chip, but is not tested further. Change-Id: I3fe0dd6fc3010a50b781ca7c5c39ea73b91978a5 Signed-off-by: Keith Hui <buurin(a)gmail.com> --- A src/superio/nuvoton/nct5535d/Kconfig A src/superio/nuvoton/nct5535d/Makefile.mk A src/superio/nuvoton/nct5535d/acpi/superio.asl A src/superio/nuvoton/nct5535d/nct5535d.h A src/superio/nuvoton/nct5535d/superio.c 5 files changed, 304 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/85834/1 diff --git a/src/superio/nuvoton/nct5535d/Kconfig b/src/superio/nuvoton/nct5535d/Kconfig new file mode 100644 index 0000000..3dc2286 --- /dev/null +++ b/src/superio/nuvoton/nct5535d/Kconfig @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0-only + +config SUPERIO_NUVOTON_NCT5535D + bool + select SUPERIO_NUVOTON_COMMON_PRE_RAM + select HAVE_POWER_STATE_AFTER_FAILURE diff --git a/src/superio/nuvoton/nct5535d/Makefile.mk b/src/superio/nuvoton/nct5535d/Makefile.mk new file mode 100644 index 0000000..1b48a19 --- /dev/null +++ b/src/superio/nuvoton/nct5535d/Makefile.mk @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +ramstage-$(CONFIG_SUPERIO_NUVOTON_NCT5535D) += superio.c diff --git a/src/superio/nuvoton/nct5535d/acpi/superio.asl b/src/superio/nuvoton/nct5535d/acpi/superio.asl new file mode 100644 index 0000000..8da1f01 --- /dev/null +++ b/src/superio/nuvoton/nct5535d/acpi/superio.asl @@ -0,0 +1,180 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * Include this file into a mainboard's DSDT _SB device tree and it will + * expose the NCT5535D SuperIO and some of its functionality. + * + * It allows the change of IO ports, IRQs and DMA settings on logical + * devices, disabling and reenabling logical devices. + * + * LDN State + * 0x2 SP1 Implemented, untested + * 0x5 KBC Implemented, untested + * 0x8 GPIO Implemented, untested + * 0xb HWM Implemented, untested + * + * Controllable through preprocessor defines: + * SUPERIO_DEV Device identifier for this SIO (e.g. SIO0) + * SUPERIO_PNP_BASE I/O address of the first PnP configuration register + * NCT5535D_SHOW_SP1 If defined, Serial Port 1 will be exposed. + * NCT5535D_SHOW_KBC If defined, the Keyboard Controller will be exposed. + * NCT5535D_SHOW_GPIO If defined, GPIO support will be exposed. + * NCT5535D_SHOW_HWM If defined, the Environment Controller will be exposed. + */ + +#undef SUPERIO_CHIP_NAME +#define SUPERIO_CHIP_NAME NCT5535D +#include <superio/acpi/pnp.asl> + +#undef PNP_DEFAULT_PSC +#define PNP_DEFAULT_PSC Return (0) /* no power management */ + +#define ENABLE_KEYBOARD_WAKEUP SKWK +#define POWER_LOSS_CONTROL SPWL + +Device(SUPERIO_DEV) { + Name (_HID, EisaId("PNP0A05")) + Name (_STR, Unicode("Nuvoton NCT5535D Super I/O")) + Name (_UID, SUPERIO_UID(SUPERIO_DEV,)) + + /* SuperIO configuration ports */ + OperationRegion (CREG, SystemIO, SUPERIO_PNP_BASE, 0x02) + Field (CREG, ByteAcc, NoLock, Preserve) + { + PNP_ADDR_REG, 8, + PNP_DATA_REG, 8, + } + IndexField (PNP_ADDR_REG, PNP_DATA_REG, ByteAcc, NoLock, Preserve) + { + Offset (0x07), + PNP_LOGICAL_DEVICE, 8, /* Logical device selector */ + + Offset (0x30), + PNP_DEVICE_ACTIVE, 1, /* Logical device activation */ + ACT1, 1, /* Logical device activation */ + ACT2, 1, /* Logical device activation */ + ACT3, 1, /* Logical device activation */ + ACT4, 1, /* Logical device activation */ + ACT5, 1, /* Logical device activation */ + ACT6, 1, /* Logical device activation */ + ACT7, 1, /* Logical device activation */ + + Offset (0x60), + PNP_IO0_HIGH_BYTE, 8, /* First I/O port base - high byte */ + PNP_IO0_LOW_BYTE, 8, /* First I/O port base - low byte */ + Offset (0x62), + PNP_IO1_HIGH_BYTE, 8, /* Second I/O port base - high byte */ + PNP_IO1_LOW_BYTE, 8, /* Second I/O port base - low byte */ + Offset (0x64), + PNP_IO2_HIGH_BYTE, 8, /* Third I/O port base - high byte */ + PNP_IO2_LOW_BYTE, 8, /* Third I/O port base - low byte */ + + Offset (0x70), + PNP_IRQ0, 8, /* First IRQ */ + Offset (0x72), + PNP_IRQ1, 8, /* Second IRQ */ + Offset (0x74), + PNP_DMA0, 8, /* DRQ */ + Offset (0xe0), /* Config register 0xe0 etc. */ + ,6, + ENABLE_KEYBOARD_WAKEUP, 1, + Offset (0xe4), + ,5, + POWER_LOSS_CONTROL, 2, + } + + Method (_CRS) + { + /* Announce the used I/O ports to the OS */ + Return (ResourceTemplate () { + IO (Decode16, SUPERIO_PNP_BASE, SUPERIO_PNP_BASE, 0x01, 0x02) + }) + } + + Method (SIOS, 1, NotSerialized) + { + if (Arg0 == 5) + { + } + Else + { + } + } + + Method (SIOW, 1, NotSerialized) + { + } + + #undef PNP_ENTER_MAGIC_1ST + #undef PNP_ENTER_MAGIC_2ND + #undef PNP_ENTER_MAGIC_3RD + #undef PNP_ENTER_MAGIC_4TH + #undef PNP_EXIT_MAGIC_1ST + #undef PNP_EXIT_SPECIAL_REG + #undef PNP_EXIT_SPECIAL_VAL + #define PNP_ENTER_MAGIC_1ST 0x87 + #define PNP_ENTER_MAGIC_2ND 0x87 + #define PNP_EXIT_MAGIC_1ST 0xaa + #include <superio/acpi/pnp_config.asl> + +#ifdef NCT5535D_SHOW_SP1 + #undef SUPERIO_UART_LDN + #undef SUPERIO_UART_DDN + #undef SUPERIO_UART_PM_REG + #undef SUPERIO_UART_PM_VAL + #undef SUPERIO_UART_PM_LDN + #define SUPERIO_UART_LDN 2 + #include <superio/acpi/pnp_uart.asl> +#endif + +#ifdef NCT5535D_SHOW_KBC + #undef SUPERIO_KBC_LDN + #undef SUPERIO_KBC_PS2M + #undef SUPERIO_KBC_PS2LDN + #define SUPERIO_KBC_LDN 5 + #define SUPERIO_KBC_PS2M + #include <superio/acpi/pnp_kbc.asl> +#endif + +#ifdef NCT5535D_SHOW_HWM + #undef SUPERIO_PNP_HID + #undef SUPERIO_PNP_LDN + #undef SUPERIO_PNP_DDN + #undef SUPERIO_PNP_NO_DIS + #undef SUPERIO_PNP_PM_REG + #undef SUPERIO_PNP_PM_VAL + #undef SUPERIO_PNP_PM_LDN + #undef SUPERIO_PNP_IO0 + #undef SUPERIO_PNP_IO1 + #undef SUPERIO_PNP_IO2 + #undef SUPERIO_PNP_IRQ0 + #undef SUPERIO_PNP_IRQ1 + #undef SUPERIO_PNP_DMA + #define SUPERIO_PNP_LDN 11 + #define SUPERIO_PNP_IO0 0x08, 0x08 + #define SUPERIO_PNP_IO1 0x08, 0x08 + #define SUPERIO_PNP_IRQ0 + #include <superio/acpi/pnp_generic.asl> +#endif + +#ifdef NCT5535D_SHOW_GPIO + #undef SUPERIO_PNP_HID + #undef SUPERIO_PNP_LDN + #undef SUPERIO_PNP_DDN + #undef SUPERIO_PNP_NO_DIS + #undef SUPERIO_PNP_PM_REG + #undef SUPERIO_PNP_PM_VAL + #undef SUPERIO_PNP_PM_LDN + #undef SUPERIO_PNP_IO0 + #undef SUPERIO_PNP_IO1 + #undef SUPERIO_PNP_IO2 + #undef SUPERIO_PNP_IRQ0 + #undef SUPERIO_PNP_IRQ1 + #undef SUPERIO_PNP_DMA + #undef PNP_DEVICE_ACTIVE + #define PNP_DEVICE_ACTIVE ACT3 + #define SUPERIO_PNP_LDN 8 + #define SUPERIO_PNP_IO0 0x08, 0x08 + #include <superio/acpi/pnp_generic.asl> +#endif +} diff --git a/src/superio/nuvoton/nct5535d/nct5535d.h b/src/superio/nuvoton/nct5535d/nct5535d.h new file mode 100644 index 0000000..9dbbee4 --- /dev/null +++ b/src/superio/nuvoton/nct5535d/nct5535d.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef SUPERIO_NUVOTON_NCT5535D_H +#define SUPERIO_NUVOTON_NCT5535D_H + +/* Logical Device Numbers (LDN). */ +#define NCT5535D_SP1 0x02 /* UART */ +#define NCT5535D_KBC 0x05 /* PS/2 keyboard and mouse */ +#define NCT5535D_CIR 0x06 /* Consumer IR */ +#define NCT5535D_GPIO678_V 0x07 /* GPIO 6/7/8 */ +#define NCT5535D_WDT1_GPIO01_V 0x08 /* WDT1, GPIO 0/1 */ +#define NCT5535D_GPIO12345678_V 0x09 /* GPIO 2/5/8 */ +#define NCT5535D_ACPI 0x0A /* ACPI */ +#define NCT5535D_HWM_FPLED 0x0B /* Hardware monitor & front LED */ +#define NCT5535D_WDT1 0x0D /* Watchdog timer 1 */ +#define NCT5535D_CIRWKUP 0x0E /* CIR wakeup */ +#define NCT5535D_GPIO_PP_OD 0x0F /* GPIO Push-Pull/Open drain select */ +#define NCT5535D_PRT80 0x14 /* Port 80 UART */ +#define NCT5535D_DSLP 0x16 /* Deep sleep */ + +/* virtual LDN for GPIO */ + +#define NCT5535D_GPIOBASE ((3 << 8) | NCT5535D_WDT1_GPIO01_V) + +#define NCT5535D_GPIO2 ((2 << 8) | NCT5535D_GPIO12345678_V) +#define NCT5535D_GPIO4 ((4 << 8) | NCT5535D_GPIO12345678_V) +#define NCT5535D_GPIO5 ((5 << 8) | NCT5535D_GPIO12345678_V) +#define NCT5535D_GPIO7 ((7 << 8) | NCT5535D_GPIO12345678_V) +#define NCT5535D_GPIO8 ((0 << 8) | NCT5535D_GPIO12345678_V) + +#endif /* SUPERIO_NUVOTON_NCT5535D_H */ diff --git a/src/superio/nuvoton/nct5535d/superio.c b/src/superio/nuvoton/nct5535d/superio.c new file mode 100644 index 0000000..5532353 --- /dev/null +++ b/src/superio/nuvoton/nct5535d/superio.c @@ -0,0 +1,84 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <device/device.h> +#include <device/pnp.h> +#include <pc80/keyboard.h> +#include <option.h> +#include <superio/conf_mode.h> + +#include "nct5535d.h" + +#define MAINBOARD_POWER_OFF 0 +#define MAINBOARD_POWER_ON 1 +#define MAINBOARD_POWER_KEEP 2 + +static void nct5535d_init(struct device *dev) +{ + uint8_t byte; + uint8_t power_status; + + if (!dev->enabled) + return; + + switch (dev->path.pnp.device) { + /* TODO: Might potentially need code for HWM etc. */ + case NCT5535D_KBC: + pc_keyboard_init(NO_AUX_DEVICE); + break; + case NCT5535D_ACPI: + /* Set power state after power fail */ + power_status = get_uint_option("power_on_after_fail", + CONFIG_MAINBOARD_POWER_FAILURE_STATE); + pnp_enter_conf_mode(dev); + pnp_set_logical_device(dev); + byte = pnp_read_config(dev, 0xe4); + byte &= ~0x04; + if (power_status == MAINBOARD_POWER_ON) + byte |= (0x1 << 5); + else if (power_status == MAINBOARD_POWER_KEEP) + byte |= (0x2 << 5); + pnp_write_config(dev, 0xe4, byte); + pnp_exit_conf_mode(dev); + printk(BIOS_INFO, "set power %s after power fail\n", power_status ? "on" : "off"); + break; + } +} + +static struct device_operations ops = { + .read_resources = noop_read_resources, + .set_resources = pnp_set_resources, + .enable_resources = pnp_enable_resources, + .enable = pnp_alt_enable, + .init = nct5535d_init, + .ops_pnp_mode = &pnp_conf_mode_8787_aa, +}; + +static struct pnp_info pnp_dev_info[] = { + { NULL, NCT5535D_SP1, PNP_IO0 | PNP_IRQ0, 0x0ff8, }, + { NULL, NCT5535D_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, + 0x0fff, 0x0fff, }, + { NULL, NCT5535D_ACPI}, + { NULL, NCT5535D_HWM_FPLED, PNP_IO0 | PNP_IO1 | PNP_IRQ0, + 0x0ffe, 0x0ffe, }, + { NULL, NCT5535D_GPIO678_V}, + { NULL, NCT5535D_WDT1}, + { NULL, NCT5535D_GPIO_PP_OD}, + { NULL, NCT5535D_PRT80}, + { NULL, NCT5535D_DSLP}, + { NULL, NCT5535D_GPIOBASE, PNP_IO0, 0x0ff8, }, + { NULL, NCT5535D_GPIO2}, + { NULL, NCT5535D_GPIO4}, + { NULL, NCT5535D_GPIO5}, + { NULL, NCT5535D_GPIO7}, + { NULL, NCT5535D_GPIO8}, +}; + +static void enable_dev(struct device *dev) +{ + pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); +} + +struct chip_operations superio_nuvoton_nct5535d_ops = { + .name = "NUVOTON NCT5535D Super I/O", + .enable_dev = enable_dev, +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/85834?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3fe0dd6fc3010a50b781ca7c5c39ea73b91978a5 Gerrit-Change-Number: 85834 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com>

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[S] Change in blobs[main]: soc/mediatek/mt8196: Add GPUEB firmware v1.0
by Jarried Lin (Code Review) 03 Jan '25

03 Jan '25

Attention is currently required from: Andy Hsu, Yidi Lin, Yu-Ping Wu. Jarried Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/blobs/+/85763?usp=email ) Change subject: soc/mediatek/mt8196: Add GPUEB firmware v1.0 ...................................................................... Patch Set 6: (3 comments) File soc/mediatek/mt8196/README.md: https://review.coreboot.org/c/blobs/+/85763/comment/05611537_03c4c421?usp=e… : PS4, Line 207: tinysys-gpueb-RV33_A.mkpt_fw.img > gpueb_fw. […] Done https://review.coreboot.org/c/blobs/+/85763/comment/f5eb272b_bcf1c755?usp=e… : PS4, Line 216: tinysys-gpueb-RV33_A.mkpt_fw.img > gpueb_fw. […] Done File soc/mediatek/mt8196/gpueb_fw.img.md5: https://review.coreboot.org/c/blobs/+/85763/comment/781b315b_d41fa69f?usp=e… : PS4, Line 1: > There should be a `*` if you used `md5sum -b`. Done -- To view, visit https://review.coreboot.org/c/blobs/+/85763?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: blobs Gerrit-Branch: main Gerrit-Change-Id: I470f1575beea481cac2dcb5f3eb77587739ff2dc Gerrit-Change-Number: 85763 Gerrit-PatchSet: 6 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Andy Hsu <andy.hsu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Andy Hsu <andy.hsu(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Fri, 03 Jan 2025 02:23:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com>

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[S] Change in blobs[main]: soc/mediatek/mt8196: Add GPUEB firmware v1.0
by Jarried Lin (Code Review) 03 Jan '25

03 Jan '25

Attention is currently required from: Andy Hsu, Jarried Lin, Yidi Lin. Hello Andy Hsu, Yidi Lin, Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/blobs/+/85763?usp=email to look at the new patch set (#6). Change subject: soc/mediatek/mt8196: Add GPUEB firmware v1.0 ...................................................................... soc/mediatek/mt8196: Add GPUEB firmware v1.0 Add initial GPUEB firmware. TEST=Build pass BUG=b:317009620 Change-Id: I470f1575beea481cac2dcb5f3eb77587739ff2dc Signed-off-by: Andy.Hsu <andy.hsu(a)mediatek.corp-partner.google.com> --- M soc/mediatek/mt8196/README.md A soc/mediatek/mt8196/gpueb_fw.img A soc/mediatek/mt8196/gpueb_fw.img.md5 A soc/mediatek/mt8196/gpueb_release_notes.txt 4 files changed, 26 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/blobs refs/changes/63/85763/6 -- To view, visit https://review.coreboot.org/c/blobs/+/85763?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: blobs Gerrit-Branch: main Gerrit-Change-Id: I470f1575beea481cac2dcb5f3eb77587739ff2dc Gerrit-Change-Number: 85763 Gerrit-PatchSet: 6 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Andy Hsu <andy.hsu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Andy Hsu <andy.hsu(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com>

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[S] Change in blobs[main]: soc/mediatek/mt8196: Add GPUEB firmware v1.0
by Jarried Lin (Code Review) 03 Jan '25

03 Jan '25

Attention is currently required from: Andy Hsu, Jarried Lin, Yidi Lin. Hello Andy Hsu, Yidi Lin, Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/blobs/+/85763?usp=email to look at the new patch set (#5). The following approvals got outdated and were removed: Code-Review+2 by Yidi Lin Change subject: soc/mediatek/mt8196: Add GPUEB firmware v1.0 ...................................................................... soc/mediatek/mt8196: Add GPUEB firmware v1.0 Add initial GPUEB firmware. TEST=Build pass BUG=b:317009620 Change-Id: I470f1575beea481cac2dcb5f3eb77587739ff2dc Signed-off-by: Andy.Hsu <andy.hsu(a)mediatek.corp-partner.google.com> --- M soc/mediatek/mt8196/README.md A soc/mediatek/mt8196/gpueb_fw.img A soc/mediatek/mt8196/gpueb_fw.img.md5 A soc/mediatek/mt8196/gpueb_release_notes.txt 4 files changed, 26 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/blobs refs/changes/63/85763/5 -- To view, visit https://review.coreboot.org/c/blobs/+/85763?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: blobs Gerrit-Branch: main Gerrit-Change-Id: I470f1575beea481cac2dcb5f3eb77587739ff2dc Gerrit-Change-Number: 85763 Gerrit-PatchSet: 5 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Andy Hsu <andy.hsu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Andy Hsu <andy.hsu(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com>

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[S] Change in coreboot[main]: soc/intel/xeon_sp: Add fix for DPR silicon bug
by Name of user not set (Code Review) 03 Jan '25

03 Jan '25

Attention is currently required from: Christian Walter, Johnny Lin, Jonathan Zhang, Patrick Rudolph, Shuo Liu, Tim Chu, Vasiliy Khoruzhick. yuchi.chen(a)intel.com has posted comments on this change by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/85829?usp=email ) Change subject: soc/intel/xeon_sp: Add fix for DPR silicon bug ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/85829/comment/0caef3d0_6eeece4a?us… : PS1, Line 16: On previous CPUs and newer CPUs the assumption is still correct and What is the assumption here? DPR is below TSEG base? -- To view, visit https://review.coreboot.org/c/coreboot/+/85829?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia090013721053ae85001a3e7d47ad2b1ec9a3203 Gerrit-Change-Number: 85829 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Vasiliy Khoruzhick <vasilykh(a)arista.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: yuchi.chen(a)intel.com Gerrit-Attention: Vasiliy Khoruzhick <vasilykh(a)arista.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Fri, 03 Jan 2025 00:16:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: Documentation: Fix make rule for sphinx-autobuild
by Nicholas Chin (Code Review) 02 Jan '25

02 Jan '25

Attention is currently required from: Václav Straka. Nicholas Chin has posted comments on this change by Václav Straka. ( https://review.coreboot.org/c/coreboot/+/85833?usp=email ) Change subject: Documentation: Fix make rule for sphinx-autobuild ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85833?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3d3b0547acd7b070925d9bee818ee1ef230f5f46 Gerrit-Change-Number: 85833 Gerrit-PatchSet: 2 Gerrit-Owner: Václav Straka <venda.straka(a)gmail.com> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Attention: Václav Straka <venda.straka(a)gmail.com> Gerrit-Comment-Date: Thu, 02 Jan 2025 22:26:52 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: Documentation: Fix make rule for sphinx-autobuild
by Václav Straka (Code Review) 02 Jan '25

02 Jan '25

Attention is currently required from: Nicholas Chin. Václav Straka has posted comments on this change by Václav Straka. ( https://review.coreboot.org/c/coreboot/+/85833?usp=email ) Change subject: Documentation: Fix make rule for sphinx-autobuild ...................................................................... Patch Set 2: (1 comment) File Documentation/Makefile.sphinx: https://review.coreboot.org/c/coreboot/+/85833/comment/bbd35316_9a8ed054?us… : PS1, Line 24: $(ALLSPHINXOPTS) > ALLSPHINXOPTS seems to be outdated; it was removed when this file was regenerated in commit 35599f9a […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/85833?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3d3b0547acd7b070925d9bee818ee1ef230f5f46 Gerrit-Change-Number: 85833 Gerrit-PatchSet: 2 Gerrit-Owner: Václav Straka <venda.straka(a)gmail.com> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Thu, 02 Jan 2025 22:26:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nicholas Chin <nic.c3.14(a)gmail.com>

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[XS] Change in coreboot[main]: Documentation: Fix make rule for sphinx-autobuild
by Václav Straka (Code Review) 02 Jan '25

02 Jan '25

Attention is currently required from: Václav Straka. Hello Nicholas Chin, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85833?usp=email to look at the new patch set (#2). Change subject: Documentation: Fix make rule for sphinx-autobuild ...................................................................... Documentation: Fix make rule for sphinx-autobuild Add source directory to arguments of sphinx-autobuild Tested in docker and natively Change-Id: I3d3b0547acd7b070925d9bee818ee1ef230f5f46 Signed-off-by: Vesek <venda.straka(a)gmail.com> --- M Documentation/Makefile.sphinx 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/85833/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85833?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3d3b0547acd7b070925d9bee818ee1ef230f5f46 Gerrit-Change-Number: 85833 Gerrit-PatchSet: 2 Gerrit-Owner: Václav Straka <venda.straka(a)gmail.com> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Attention: Václav Straka <venda.straka(a)gmail.com>

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[XS] Change in coreboot[main]: Documentation: Fix make rule for sphinx-autobuild
by Nicholas Chin (Code Review) 02 Jan '25

02 Jan '25

Attention is currently required from: Václav Straka. Nicholas Chin has posted comments on this change by Václav Straka. ( https://review.coreboot.org/c/coreboot/+/85833?usp=email ) Change subject: Documentation: Fix make rule for sphinx-autobuild ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > Also, considering that sphinx seems to want to move away from the generated makefile (Makefile. […] I guess the only real use of `Makefile.sphinx` right now is for handling non-html targets (latex, texinto, man, etc) through `make -f Makefile.sphinx non-html-target` but I doubt those are really used by anyone. -- To view, visit https://review.coreboot.org/c/coreboot/+/85833?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3d3b0547acd7b070925d9bee818ee1ef230f5f46 Gerrit-Change-Number: 85833 Gerrit-PatchSet: 1 Gerrit-Owner: Václav Straka <venda.straka(a)gmail.com> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Attention: Václav Straka <venda.straka(a)gmail.com> Gerrit-Comment-Date: Thu, 02 Jan 2025 22:23:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nicholas Chin <nic.c3.14(a)gmail.com>

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