coreboot-gerrit January 2025

coreboot-gerrit@coreboot.org

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[XS] Change in coreboot[main]: mb/google/rauru: Correct the argument type of ADC
by Jarried Lin (Code Review) 03 Jan '25

03 Jan '25

Attention is currently required from: Hope Wang, Hung-Te Lin, Yidi Lin, Yu-Ping Wu. Hello Hope Wang, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/85840?usp=email to review the following change. Change subject: mb/google/rauru: Correct the argument type of ADC ...................................................................... mb/google/rauru: Correct the argument type of ADC Correct the argument type when calling the mt6363_sdmadc_read API. TEST=Build pass BUG=b:317009620 Change-Id: I3d55e787dd86d474c299b2f7ad4a2fefda436a60 Signed-off-by: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> --- M src/mainboard/google/rauru/boardid.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/85840/1 diff --git a/src/mainboard/google/rauru/boardid.c b/src/mainboard/google/rauru/boardid.c index e3e0979..fc0230d 100644 --- a/src/mainboard/google/rauru/boardid.c +++ b/src/mainboard/google/rauru/boardid.c @@ -38,7 +38,7 @@ static uint32_t get_adc_index(unsigned int channel) { - int value; + u32 value; mt6363_sdmadc_read(channel, &value, SDMADC_OPEN, AUXADC_VAL_PROCESSED); assert(channel < ARRAY_SIZE(adc_voltages)); -- To view, visit https://review.coreboot.org/c/coreboot/+/85840?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3d55e787dd86d474c299b2f7ad4a2fefda436a60 Gerrit-Change-Number: 85840 Gerrit-PatchSet: 1 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com>

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[S] Change in coreboot[main]: soc/mediatek/mt8196: Correct the argument type of MT6363
by Jarried Lin (Code Review) 03 Jan '25

03 Jan '25

Attention is currently required from: Hope Wang. Hello Hope Wang, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/85839?usp=email to review the following change. Change subject: soc/mediatek/mt8196: Correct the argument type of MT6363 ...................................................................... soc/mediatek/mt8196: Correct the argument type of MT6363 Correct the argument type of the mt6363_sdmadc_read API and the return value type of the mt6363_read16 API. TEST=Build pass BUG=b:317009620 Change-Id: I0f768e23473fa924245d90ab1e4fa383ec437db3 Signed-off-by: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> --- M src/soc/mediatek/common/include/soc/mt6363.h M src/soc/mediatek/common/include/soc/mt6363_sdmadc.h M src/soc/mediatek/common/mt6363.c M src/soc/mediatek/common/mt6363_sdmadc.c 4 files changed, 5 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/85839/1 diff --git a/src/soc/mediatek/common/include/soc/mt6363.h b/src/soc/mediatek/common/include/soc/mt6363.h index 19b23d4..4659119 100644 --- a/src/soc/mediatek/common/include/soc/mt6363.h +++ b/src/soc/mediatek/common/include/soc/mt6363.h @@ -108,7 +108,7 @@ void mt6363_enable_vram_digrf(bool enable); void mt6363_enable_vram_mdfe(bool enable); void mt6363_init_pmif_arb(void); -u32 mt6363_read16(u32 reg); +u16 mt6363_read16(u32 reg); void mt6363_write8(u32 reg, u8 reg_val); void mt6363_write_field(u32 reg, u32 val, u32 mask, u32 shift); void mt6363_init_setting(void); diff --git a/src/soc/mediatek/common/include/soc/mt6363_sdmadc.h b/src/soc/mediatek/common/include/soc/mt6363_sdmadc.h index ae990c9..8735824 100644 --- a/src/soc/mediatek/common/include/soc/mt6363_sdmadc.h +++ b/src/soc/mediatek/common/include/soc/mt6363_sdmadc.h @@ -84,7 +84,7 @@ } sdmadc_hw_info; }; -int mt6363_sdmadc_read(enum auxadc_channel channel, int *val, enum sdmadc_pures pures, +int mt6363_sdmadc_read(enum auxadc_channel channel, u32 *val, enum sdmadc_pures pures, enum auxadc_val_type type); #endif /* __MT6363_SDMADC_H__ */ diff --git a/src/soc/mediatek/common/mt6363.c b/src/soc/mediatek/common/mt6363.c index 20ef9f0..b16f6b1 100644 --- a/src/soc/mediatek/common/mt6363.c +++ b/src/soc/mediatek/common/mt6363.c @@ -25,7 +25,7 @@ }; static struct pmif *pmif_arb; -u32 mt6363_read16(u32 reg) +u16 mt6363_read16(u32 reg) { u16 rdata = 0; diff --git a/src/soc/mediatek/common/mt6363_sdmadc.c b/src/soc/mediatek/common/mt6363_sdmadc.c index eb4b978..647423d 100644 --- a/src/soc/mediatek/common/mt6363_sdmadc.c +++ b/src/soc/mediatek/common/mt6363_sdmadc.c @@ -61,11 +61,11 @@ _Static_assert(ARRAY_SIZE(mt6363_sdmadc_chan_specs) == AUXADC_CHAN_MAX, "Wrong array size for mt6363_sdmadc_chan_specs"); -int mt6363_sdmadc_read(enum auxadc_channel channel, int *val, +int mt6363_sdmadc_read(enum auxadc_channel channel, u32 *val, enum sdmadc_pures pures, enum auxadc_val_type type) { u8 wdata; - u32 regval; + u16 regval; u32 elapsed = 0; const struct auxadc_chan_spec *chan; -- To view, visit https://review.coreboot.org/c/coreboot/+/85839?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0f768e23473fa924245d90ab1e4fa383ec437db3 Gerrit-Change-Number: 85839 Gerrit-PatchSet: 1 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> Gerrit-Attention: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com>

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[XS] Change in coreboot[main]: soc/mediatek/mt8196: Correct MT6363 buck5 enable API
by Jarried Lin (Code Review) 03 Jan '25

03 Jan '25

Attention is currently required from: Hope Wang. Hello Hope Wang, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/85838?usp=email to review the following change. Change subject: soc/mediatek/mt8196: Correct MT6363 buck5 enable API ...................................................................... soc/mediatek/mt8196: Correct MT6363 buck5 enable API MT6363 buck5 is not used in rauru/navi. Fixed the incorrect mask and offset in the enable API. TEST=build pass BUG=b:365445188 Change-Id: I0af1e0582ae8fc1e219f3cce536aed9985108be5 Signed-off-by: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> --- M src/soc/mediatek/common/mt6363.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/85838/1 diff --git a/src/soc/mediatek/common/mt6363.c b/src/soc/mediatek/common/mt6363.c index 691282b..20ef9f0 100644 --- a/src/soc/mediatek/common/mt6363.c +++ b/src/soc/mediatek/common/mt6363.c @@ -211,7 +211,7 @@ void mt6363_enable_buck5(bool enable) { - mt6363_write_field(PMIC_VBUCK5_OP_EN_2, enable, 0x7, 0); + mt6363_write_field(PMIC_VBUCK5_OP_EN_2, enable, 0x1, 7); } void mt6363_enable_vcn15(bool enable) -- To view, visit https://review.coreboot.org/c/coreboot/+/85838?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0af1e0582ae8fc1e219f3cce536aed9985108be5 Gerrit-Change-Number: 85838 Gerrit-PatchSet: 1 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> Gerrit-Attention: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com>

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[M] Change in coreboot[main]: cpu/x86/64bit: Install extended page tables in BSS
by Patrick Rudolph (Code Review) 03 Jan '25

03 Jan '25

Attention is currently required from: Christian Walter, Johnny Lin, Jonathan Zhang, Jérémy Compostella, Shuo Liu, Tim Chu. Patrick Rudolph has posted comments on this change by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/85806?usp=email ) Change subject: cpu/x86/64bit: Install extended page tables in BSS ...................................................................... Patch Set 3: (1 comment) File src/cpu/x86/64bit/mmu.c: https://review.coreboot.org/c/coreboot/+/85806/comment/ee7fd5ef_e7b1cfc5?us… : PS3, Line 59: if (cpu_supports_1gb_hugepage()) { : const uintptr_t max_addr = 1ULL * GiB * 512ULL * 512ULL; : const uint64_t incr = 1ULL * GiB; : : /* Build P4MLE */ : for (int i = 0; i < 512; i++) : p4mle[i] = _GEN_DIR(&pdpt[i * 512]); : : /* Build PDPT */ : uint64_t *page_table_ptr = pdpt; : for (uintptr_t addr = 0; addr < max_addr; addr += incr, page_table_ptr++) : *page_table_ptr = _GEN_PAGE(addr); : } else { : const uintptr_t max_addr = 2ULL * MiB * 512ULL * 512ULL; : const uint64_t incr = 2ULL * MiB; : : /* Build P4MLE */ : p4mle[0] = _GEN_DIR(&pdpt[0]); : : /* Build PDPT */ : for (int i = 0; i < 512; i++) : pdpt[i] = _GEN_DIR(&pdt[i * 512]); : : /* Build PDT */ : uint64_t *page_table_ptr = pdt; : for (uintptr_t addr = 0; addr < max_addr; addr += incr, page_table_ptr++) : *page_table_ptr = _GEN_PAGE(addr); : } : > There are a lot in common between these two branches, isn't it a way to share more code ? I don't see that. Please explain how it can be improved without reducing readability. -- To view, visit https://review.coreboot.org/c/coreboot/+/85806?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifab50975e0382a1f5c27b55bca1dbbb66b37ba3a Gerrit-Change-Number: 85806 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Fri, 03 Jan 2025 08:18:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com>

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[S] Change in coreboot[main]: soc/intel/xeon_sp: Add fix for DPR silicon bug
by Patrick Rudolph (Code Review) 03 Jan '25

03 Jan '25

Attention is currently required from: Christian Walter, Johnny Lin, Jonathan Zhang, Shuo Liu, Tim Chu, Vasiliy Khoruzhick, yuchi.chen(a)intel.com. Patrick Rudolph has posted comments on this change by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/85829?usp=email ) Change subject: soc/intel/xeon_sp: Add fix for DPR silicon bug ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/85829/comment/2af0bf82_731dd181?us… : PS1, Line 16: On previous CPUs and newer CPUs the assumption is still correct and > The assumption is that DRP TOP bits are never read as 0, as this sentence is stating. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/85829?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia090013721053ae85001a3e7d47ad2b1ec9a3203 Gerrit-Change-Number: 85829 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Vasiliy Khoruzhick <vasilykh(a)arista.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: yuchi.chen(a)intel.com Gerrit-Attention: yuchi.chen(a)intel.com Gerrit-Attention: Vasiliy Khoruzhick <vasilykh(a)arista.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Fri, 03 Jan 2025 08:10:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: yuchi.chen(a)intel.com Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com>

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[S] Change in coreboot[main]: soc/intel/xeon_sp: Add fix for DPR silicon bug
by Patrick Rudolph (Code Review) 03 Jan '25

03 Jan '25

Attention is currently required from: Christian Walter, Johnny Lin, Jonathan Zhang, Shuo Liu, Tim Chu, Vasiliy Khoruzhick, yuchi.chen(a)intel.com. Patrick Rudolph has posted comments on this change by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/85829?usp=email ) Change subject: soc/intel/xeon_sp: Add fix for DPR silicon bug ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/85829/comment/5f606880_c698fe2c?us… : PS1, Line 16: On previous CPUs and newer CPUs the assumption is still correct and > What is the assumption here? DPR is below TSEG base? The assumption is that DRP TOP bits are never read as 0, as this sentence is stating. Will rephrase the commit message. -- To view, visit https://review.coreboot.org/c/coreboot/+/85829?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia090013721053ae85001a3e7d47ad2b1ec9a3203 Gerrit-Change-Number: 85829 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Vasiliy Khoruzhick <vasilykh(a)arista.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: yuchi.chen(a)intel.com Gerrit-Attention: yuchi.chen(a)intel.com Gerrit-Attention: Vasiliy Khoruzhick <vasilykh(a)arista.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Fri, 03 Jan 2025 08:08:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: yuchi.chen(a)intel.com

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[XS] Change in coreboot[main]: [test] clang EMULATION_QEMU_POWER8 test build
by Elyes Haouas (Code Review) 03 Jan '25

03 Jan '25

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85837?usp=email ) Change subject: [test] clang EMULATION_QEMU_POWER8 test build ...................................................................... [test] clang EMULATION_QEMU_POWER8 test build Change-Id: I168e4ca7e2c2780175e4cc6565211be917ea0ae5 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/mainboard/emulation/qemu-power8/Makefile.mk 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/85837/1 diff --git a/src/mainboard/emulation/qemu-power8/Makefile.mk b/src/mainboard/emulation/qemu-power8/Makefile.mk index c1484b9..ab5ec44 100644 --- a/src/mainboard/emulation/qemu-power8/Makefile.mk +++ b/src/mainboard/emulation/qemu-power8/Makefile.mk @@ -5,8 +5,8 @@ bootblock-y += rom_media.c romstage-y += cbmem.c romstage-y += romstage.c -ramstage-y += timer.c romstage-y += uart.c romstage-y += rom_media.c +ramstage-y += timer.c ramstage-y += uart.c ramstage-y += rom_media.c -- To view, visit https://review.coreboot.org/c/coreboot/+/85837?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I168e4ca7e2c2780175e4cc6565211be917ea0ae5 Gerrit-Change-Number: 85837 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr>

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[L] Change in coreboot[main]: soc/mediatek/mt8196: Add GPUEB support
by Jarried Lin (Code Review) 03 Jan '25

03 Jan '25

Attention is currently required from: Andy Hsu, Hung-Te Lin, Yidi Lin, Yu-Ping Wu. Jarried Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85654?usp=email ) Change subject: soc/mediatek/mt8196: Add GPUEB support ...................................................................... Patch Set 7: (1 comment) File src/soc/mediatek/mt8196/include/soc/memlayout.ld: https://review.coreboot.org/c/coreboot/+/85654/comment/acf8b821_322d8fd9?us… : PS6, Line 9: > tab Done -- To view, visit https://review.coreboot.org/c/coreboot/+/85654?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0f10dfc753f73df97ea08a4c23e97de416832be2 Gerrit-Change-Number: 85654 Gerrit-PatchSet: 7 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Andy Hsu <andy.hsu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alvin Liu <alvin.liu(a)mediatek.corp-partner.google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Andy Hsu <andy.hsu(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Fri, 03 Jan 2025 06:39:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com>

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[L] Change in coreboot[main]: soc/mediatek/mt8196: Add GPUEB support
by Jarried Lin (Code Review) 03 Jan '25

03 Jan '25

Attention is currently required from: Andy Hsu, Hung-Te Lin, Jarried Lin, Yidi Lin, Yu-Ping Wu. Hello Andy Hsu, Hung-Te Lin, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85654?usp=email to look at the new patch set (#7). The following approvals got outdated and were removed: Code-Review+1 by Yidi Lin Change subject: soc/mediatek/mt8196: Add GPUEB support ...................................................................... soc/mediatek/mt8196: Add GPUEB support GPUEB is a micro-processor used for GPU power management. It is also responsible for controlling GPU DVFS and GPU thermal throttling. This gpueb load flow adds 47ms to the boot time. coreboot log: CBFS: Found 'gpueb_fw.img' @0x84740 size 0x29736 in mcache @0xfffdd374 Loaded (and reset) gpueb_fw.img in 47 msecs. TEST=Boot ok BUG=b:317009620 Signed-off-by: Andy.Hsu <andy.hsu(a)mediatek.corp-partner.google.com> Change-Id: I0f10dfc753f73df97ea08a4c23e97de416832be2 --- M src/soc/mediatek/common/include/soc/symbols.h M src/soc/mediatek/mt8196/Kconfig M src/soc/mediatek/mt8196/Makefile.mk A src/soc/mediatek/mt8196/gpueb.c M src/soc/mediatek/mt8196/include/soc/addressmap.h A src/soc/mediatek/mt8196/include/soc/gpueb.h A src/soc/mediatek/mt8196/include/soc/gpueb_priv.h M src/soc/mediatek/mt8196/include/soc/memlayout.ld M src/soc/mediatek/mt8196/soc.c 9 files changed, 609 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/85654/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/85654?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0f10dfc753f73df97ea08a4c23e97de416832be2 Gerrit-Change-Number: 85654 Gerrit-PatchSet: 7 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Andy Hsu <andy.hsu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alvin Liu <alvin.liu(a)mediatek.corp-partner.google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Andy Hsu <andy.hsu(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com>

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[L] Change in coreboot[main]: soc/mediatek/mt8196: Add GPUEB support
by Yidi Lin (Code Review) 03 Jan '25

03 Jan '25

Attention is currently required from: Andy Hsu, Hung-Te Lin, Jarried Lin, Yu-Ping Wu. Yidi Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85654?usp=email ) Change subject: soc/mediatek/mt8196: Add GPUEB support ...................................................................... Patch Set 6: Code-Review+1 (1 comment) File src/soc/mediatek/mt8196/include/soc/memlayout.ld: https://review.coreboot.org/c/coreboot/+/85654/comment/4bcdca80_a9da129a?us… : PS6, Line 9: tab -- To view, visit https://review.coreboot.org/c/coreboot/+/85654?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0f10dfc753f73df97ea08a4c23e97de416832be2 Gerrit-Change-Number: 85654 Gerrit-PatchSet: 6 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Andy Hsu <andy.hsu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alvin Liu <alvin.liu(a)mediatek.corp-partner.google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Andy Hsu <andy.hsu(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Fri, 03 Jan 2025 06:30:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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coreboot-gerrit January 2025