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Change subject: mb/google/fatcat: Enable PCH Energy Report
......................................................................
mb/google/fatcat: Enable PCH Energy Report
This enables PCH Energy report feature.
BUG=b:373915085
TEST=Build fatcat and check UPD-PchPmDisableEnergyReport is configured
correctly.
Change-Id: Ie318f21cf00a74fd68c86dd39efb5e020e444085
Signed-off-by: Jamie Ryu <jamie.m.ryu(a)intel.com>
---
M src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb
1 file changed, 4 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/85615/3
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Change subject: mb/google/fatcat: Remove Safe Settings
......................................................................
Patch Set 2:
(1 comment)
File src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/85615/comment/870c638d_d5d57678?us… :
PS1, Line 38:
: # TODO: Safe Setting. Needs to be removed later
: # Disable C1 C-state auto-demotion
: register "disable_c1_state_auto_demotion" = "true"
> all previous generation devices had this config set to `true` therefore, we might use the same confi […]
Let me check this with PTL and update.
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Attention is currently required from: Bora Guvendik, Intel coreboot Reviewers, Jamie Ryu, Jayvik Desai, Kapil Porwal, Pranava Y N, Sowmya Aralguppe, Vikrant L Jadeja, Wonkyu Kim.
Hello Bora Guvendik, Intel coreboot Reviewers, Jayvik Desai, Jérémy Compostella, Kapil Porwal, Pranava Y N, Sowmya Aralguppe, Subrata Banik, Vikrant L Jadeja, Wonkyu Kim, build bot (Jenkins),
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Change subject: soc/intel/pantherlake: Update Crashlog config
......................................................................
soc/intel/pantherlake: Update Crashlog config
This will configure CpuCrashLogEnable regardless of Tracehub
configuration as Crashlog feature does not have a dependency
with Tracehub.
TEST=Build fatcat and check Crashlog is enabled without enabling
Tracehub.
Change-Id: I6f37e9f4a1f55ffc576af955c92d4073068eb97a
Signed-off-by: Jamie Ryu <jamie.m.ryu(a)intel.com>
---
M src/soc/intel/pantherlake/romstage/fsp_params.c
1 file changed, 2 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/85614/2
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Change subject: soc/mediatek/mt8196: Add mtk_fsp_romstage version v1.0
......................................................................
Patch Set 4: Code-Review+2
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Change subject: soc/mediatek/mt8196: Add PI_IMG firmware v1.0
......................................................................
Patch Set 2: Code-Review+2
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Change subject: soc/mediatek/mt8196: Correct the region size for mcufw_reserved
......................................................................
soc/mediatek/mt8196: Correct the region size for mcufw_reserved
Adjust the allocated region size for mcufw_reserved from 52K to 68K.
TEST=Build pass.
BUG=b:390334489
Change-Id: I1c17c1492d5568f4d51ff45e1fb90e067eae5cb1
Signed-off-by: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86108
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---
M src/soc/mediatek/mt8196/include/soc/memlayout.ld
1 file changed, 8 insertions(+), 8 deletions(-)
Approvals:
Yu-Ping Wu: Looks good to me, approved
Yidi Lin: Looks good to me, approved
build bot (Jenkins): Verified
diff --git a/src/soc/mediatek/mt8196/include/soc/memlayout.ld b/src/soc/mediatek/mt8196/include/soc/memlayout.ld
index 74f1543..ef6a146 100644
--- a/src/soc/mediatek/mt8196/include/soc/memlayout.ld
+++ b/src/soc/mediatek/mt8196/include/soc/memlayout.ld
@@ -24,18 +24,18 @@
/* EMPTY(0x0010bc90, 29K - 144) */
/*
* MCUPM exchanges data with kernel driver using SRAM 0x00113000 ~
- * 0x0011ffff. The address is hardcoded in MCUPM image.
+ * 0x00123fff. The address is hardcoded in MCUPM image.
*/
- REGION(mcufw_reserved, 0x00113000, 52K, 4K)
+ REGION(mcufw_reserved, 0x00113000, 68K, 4K)
/* End of regions that need to stay in SRAM. */
/* Regions can be moved to SRAM_L2C. */
- CBFS_MCACHE(0x00120000, 16k)
- VBOOT2_WORK(0x00124000, 12K)
- FMAP_CACHE(0x00127000, 2k)
- TPM_LOG(0x00127800, 2k)
- TIMESTAMP(0x00128000, 1k)
+ CBFS_MCACHE(0x00124000, 16k)
+ VBOOT2_WORK(0x00128000, 12K)
+ FMAP_CACHE(0x0012B000, 2k)
+ TPM_LOG(0x0012B800, 2k)
+ TIMESTAMP(0x0012C000, 1k)
/* End of regions that can also be moved to SRAM_L2C. */
- /* EMPTY(0x00128400, 95K) */
+ /* EMPTY(0x0012C400, 79K) */
SRAM_END(0x00140000)
/*
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Change subject: mb/google/corsola: Increase ANX7625 data trail time
......................................................................
Patch Set 4:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/86101/comment/9bf10e94_e349481b?us… :
PS3, Line 15:
> Please mention this in the commit message. (*Copy* instead of *migrated* seems to be more correct. […]
Acknowledged
Commit Message:
https://review.coreboot.org/c/coreboot/+/86101/comment/4117262d_edbd415f?us… :
PS4, Line 16: id:391304679
> b:391304679
Acknowledged
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I'd like you to reexamine a change. Please visit
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Change subject: mb/google/corsola: Increase ANX7625 data trail time
......................................................................
mb/google/corsola: Increase ANX7625 data trail time
Currently, the eDP panel has display shift issue. This issue
is caused by too short HS-trail time.
Based on hardware design ANX7625 requires more HS-trail time to
finish mipi data packet decoding before entering LP mode.
So increase HS-trail time to avoid effect of entering LP mode.
da_hs_trail value copy from "kukui/panel_anx7625.c", verified
on corsola.
BUG=b:391304679
BRANCH=corsola
TEST=Display is normal on corsola
Change-Id: I677667240c7f3b0e14c6a728931921e32f539c57
Signed-off-by: Xin Ji <xji(a)analogix.corp-partner.google.com>
---
M src/mainboard/google/corsola/panel_anx7625.c
1 file changed, 6 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/86101/5
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Julius Werner has posted comments on this change by Julius Werner. ( https://review.coreboot.org/c/coreboot/+/86142?usp=email )
Change subject: libpayload: Unify selfboot() implementations
......................................................................
Patch Set 1:
(1 comment)
File payloads/libpayload/libc/selfboot.c:
https://review.coreboot.org/c/coreboot/+/86142/comment/fbba02a0_e8231ae9?us… :
PS1, Line 35: __attribute__((__regparm__(0)))
I think technically this doesn't really do anything, because our default calling convention is already `regparm(0)` to begin with. But coreboot also still does it when loading the payload, so I guess it's more consistent to do it here too.
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