coreboot-gerrit January 2025

coreboot-gerrit@coreboot.org

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[M] Change in coreboot[main]: mb/asus/p8z77-v: Attempt to correctly route PCIe lanes
by Angel Pons (Code Review) 24 Jan '25

24 Jan '25

Attention is currently required from: Bill XIE, Keith Hui. Angel Pons has posted comments on this change by Keith Hui. ( https://review.coreboot.org/c/coreboot/+/85413?usp=email ) Change subject: mb/asus/p8z77-v: Attempt to correctly route PCIe lanes ...................................................................... Patch Set 3: (1 comment) File src/mainboard/asus/p8x7x-series/variants/p8z77-v/cmos.layout: https://review.coreboot.org/c/coreboot/+/85413/comment/9dd0959b_e67a1d0b?us… : PS3, Line 30: always_use_sata6ge Silly question: what does the trailing `e` mean? -- To view, visit https://review.coreboot.org/c/coreboot/+/85413?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If41197a1f817a48c209d25fc1ae461ec97ccf16c Gerrit-Change-Number: 85413 Gerrit-PatchSet: 3 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Attention: Keith Hui <buurin(a)gmail.com> Gerrit-Comment-Date: Fri, 24 Jan 2025 16:24:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: mb/starlabs/starbook/adl_n: Remove switch property from back USB port
by 9elements QA (Code Review) 24 Jan '25

24 Jan '25

9elements QA has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/86086?usp=email ) Change subject: mb/starlabs/starbook/adl_n: Remove switch property from back USB port ...................................................................... Patch Set 3: Automatic boot test returned (PASS/FAIL/TOTAL): 11 / 1 / 12 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/230926 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/230924 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/230923 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/230922 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/230921 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/230920 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/230919 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/230918 FAIL: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/230917 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/230916 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/230915 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/230914 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/86086?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic6b77f44a2d2607d201a2b097cea41aa361ebbee Gerrit-Change-Number: 86086 Gerrit-PatchSet: 3 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Fri, 24 Jan 2025 15:16:04 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

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[M] Change in coreboot[main]: mb/supermicro: add support for x13sae-f
by Andy Ebrahiem (Code Review) 24 Jan '25

24 Jan '25

Andy Ebrahiem has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86145?usp=email ) Change subject: mb/supermicro: add support for x13sae-f ...................................................................... mb/supermicro: add support for x13sae-f Change-Id: If823a27071f282adc122c0bcd910161ae1ba95a3 Signed-off-by: Andy <andy(a)9elements.com> --- A src/mainboard/supermicro/x13sae-f/Kconfig A src/mainboard/supermicro/x13sae-f/Kconfig.name A src/mainboard/supermicro/x13sae-f/Makefile.inc A src/mainboard/supermicro/x13sae-f/board_info.txt A src/mainboard/supermicro/x13sae-f/bootblock.c A src/mainboard/supermicro/x13sae-f/devicetree.cb A src/mainboard/supermicro/x13sae-f/dsdt.asl A src/mainboard/supermicro/x13sae-f/mainboard.c A src/mainboard/supermicro/x13sae-f/romstage.c 9 files changed, 115 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/86145/1 diff --git a/src/mainboard/supermicro/x13sae-f/Kconfig b/src/mainboard/supermicro/x13sae-f/Kconfig new file mode 100644 index 0000000..4bc7369 --- /dev/null +++ b/src/mainboard/supermicro/x13sae-f/Kconfig @@ -0,0 +1,49 @@ +# ## SPDX-License-Identifier: GPL-2.0-only + +if BOARD_SUPERMICRO_X13SAE_F + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select SOC_INTEL_RAPTORLAKE_PCH_S + select BOARD_ROMSIZE_KB_32768 + select DRIVERS_UART_8250IO + # select DRIVERS_ASPEED_AST2050 + # select DRIVERS_ASPEED_AST_COMMON + select HAVE_ACPI_TABLES + select HAVE_ACPI_RESUME + select HAVE_IFD_BIN + select HAVE_INTEL_FSP + select HAVE_GBE_BIN + select MAINBOARD_USES_IFD_GBE_REGION + select SUPERIO_NUVOTON_COMMON_COM_A + select SUPERIO_NUVOTON_NCT6791D + select HAVE_EM100_SUPPORT + + +config MAINBOARD_DIR + string + default "supermicro/x13sae-f" + +config MAINBOARD_PART_NUMBER + string + default "X13SAE-F" + +config IFD_BIN_PATH + string + default "3rdparty/blobs/mainboard/\$(MAINBOARDDIR)/descriptor.bin" + +config ME_BIN_PATH + string + default "3rdparty/blobs/mainboard/\$(MAINBOARDDIR)/me.bin" + +config GBE_BIN_PATH + string + default "3rdparty/blobs/mainboard/\$(MAINBOARDDIR)/gbe.bin" + +config SUPERIO_NUVOTON_ENABLE_UART + bool "Enable SuperIO UART for debugging" + default y + + + +# endif \ No newline at end of file diff --git a/src/mainboard/supermicro/x13sae-f/Kconfig.name b/src/mainboard/supermicro/x13sae-f/Kconfig.name new file mode 100644 index 0000000..9d60338 --- /dev/null +++ b/src/mainboard/supermicro/x13sae-f/Kconfig.name @@ -0,0 +1,4 @@ +## SPDX-License-Identifier: GPL-2.0-only + +config BOARD_SUPERMICRO_X13SAE_F + bool "X13SAE-F" diff --git a/src/mainboard/supermicro/x13sae-f/Makefile.inc b/src/mainboard/supermicro/x13sae-f/Makefile.inc new file mode 100644 index 0000000..82cb3a1 --- /dev/null +++ b/src/mainboard/supermicro/x13sae-f/Makefile.inc @@ -0,0 +1,3 @@ +bootblock-y += bootblock.c +romstage-y += romstage.c +ramstage-y += mainboard.c \ No newline at end of file diff --git a/src/mainboard/supermicro/x13sae-f/board_info.txt b/src/mainboard/supermicro/x13sae-f/board_info.txt new file mode 100644 index 0000000..0da68e7 --- /dev/null +++ b/src/mainboard/supermicro/x13sae-f/board_info.txt @@ -0,0 +1,7 @@ +Category: desktop +Board URL: https://www.supermicro.com/de/products/motherboard/x13sae-f +ROM IC: MX25L25673G +ROM package: SOIC-8 +ROM socketed: no +Flashrom support: yes +Release year: 2022 \ No newline at end of file diff --git a/src/mainboard/supermicro/x13sae-f/bootblock.c b/src/mainboard/supermicro/x13sae-f/bootblock.c new file mode 100644 index 0000000..205501c --- /dev/null +++ b/src/mainboard/supermicro/x13sae-f/bootblock.c @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootblock_common.h> +#include <console/console.h> +#include <reset.h> + +void bootblock_mainboard_early_init(void) +{ + printk(BIOS_DEBUG, "mainboard_early_init\n"); + board_reset(); +} \ No newline at end of file diff --git a/src/mainboard/supermicro/x13sae-f/devicetree.cb b/src/mainboard/supermicro/x13sae-f/devicetree.cb new file mode 100644 index 0000000..a05bb85 --- /dev/null +++ b/src/mainboard/supermicro/x13sae-f/devicetree.cb @@ -0,0 +1,6 @@ +chip soc/intel/alderlake + device domain 0 on + device pci 00.0 on end + device pci 15.0 on end + end +end \ No newline at end of file diff --git a/src/mainboard/supermicro/x13sae-f/dsdt.asl b/src/mainboard/supermicro/x13sae-f/dsdt.asl new file mode 100644 index 0000000..584f330 --- /dev/null +++ b/src/mainboard/supermicro/x13sae-f/dsdt.asl @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 +) +{ + #include <acpi/dsdt_top.asl> + #include <soc/intel/common/block/acpi/acpi/platform.asl> + #include <soc/intel/common/block/acpi/acpi/globalnvs.asl> + #include <cpu/intel/common/acpi/cpu.asl> + + Device (\_SB.PCI0) { + #include <soc/intel/common/block/acpi/acpi/northbridge.asl> + #include <soc/intel/alderlake/acpi/southbridge.asl> + #include <soc/intel/alderlake/acpi/tcss.asl> + } + + #include <southbridge/intel/common/acpi/sleepstates.asl> +} diff --git a/src/mainboard/supermicro/x13sae-f/mainboard.c b/src/mainboard/supermicro/x13sae-f/mainboard.c new file mode 100644 index 0000000..6344766 --- /dev/null +++ b/src/mainboard/supermicro/x13sae-f/mainboard.c @@ -0,0 +1,3 @@ +#include <device/device.h> + +struct chip_operations mainboard_ops = {}; \ No newline at end of file diff --git a/src/mainboard/supermicro/x13sae-f/romstage.c b/src/mainboard/supermicro/x13sae-f/romstage.c new file mode 100644 index 0000000..da4fea6 --- /dev/null +++ b/src/mainboard/supermicro/x13sae-f/romstage.c @@ -0,0 +1,6 @@ +#include <soc/romstage.h> + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + +} \ No newline at end of file -- To view, visit https://review.coreboot.org/c/coreboot/+/86145?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If823a27071f282adc122c0bcd910161ae1ba95a3 Gerrit-Change-Number: 86145 Gerrit-PatchSet: 1 Gerrit-Owner: Andy Ebrahiem <ahmet.ebrahiem(a)9elements.com>

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[S] Change in coreboot[main]: mb/asus/p8x7x-series: Blink power LED during suspend
by Keith Hui (Code Review) 24 Jan '25

24 Jan '25

Attention is currently required from: Keith Hui. Hello Paul Menzel, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/82557?usp=email to look at the new patch set (#4). Change subject: mb/asus/p8x7x-series: Blink power LED during suspend ...................................................................... mb/asus/p8x7x-series: Blink power LED during suspend Extends commit 57946ad8174a ("mb/asus/p8z77-m[_pro]: Blink power LED during suspend") to the entire family. Also, we don't need the 0x for Arg0; it can't go larger than 5. Applied this patch and CB:82556 while developing a port for Asus P8Z77-V LE PLUS mainboard (which uses GPIO8 for power LED). Its power LED does blink during suspend. Change-Id: Ie30e5ef79a87a3dca6875b0a6e07ae99d0d79e6e Signed-off-by: Keith Hui <buurin(a)gmail.com> --- M src/mainboard/asus/p8x7x-series/acpi/platform.asl 1 file changed, 8 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/82557/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/82557?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie30e5ef79a87a3dca6875b0a6e07ae99d0d79e6e Gerrit-Change-Number: 82557 Gerrit-PatchSet: 4 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Keith Hui <buurin(a)gmail.com>

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[S] Change in coreboot[main]: mb/google/rauru: Configure firmware display for eDP panel
by 9elements QA (Code Review) 24 Jan '25

24 Jan '25

9elements QA has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85952?usp=email ) Change subject: mb/google/rauru: Configure firmware display for eDP panel ...................................................................... Patch Set 17: Automatic boot test returned (PASS/FAIL/TOTAL): 11 / 1 / 12 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/230965 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/230963 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/230962 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/230961 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/230960 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/230959 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/230958 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/230957 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/230956 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/230955 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/230954 FAIL: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/230953 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/85952?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic928b2478c41ccd03223fd2b73d9e81d303a2036 Gerrit-Change-Number: 85952 Gerrit-PatchSet: 17 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Nancy Lin <nancy.lin(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Fri, 24 Jan 2025 14:35:06 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

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[M] Change in coreboot[main]: mb/amd/birman_plus: Update PCIe Slot configurations
by Nick Kochlowski (Code Review) 24 Jan '25

24 Jan '25

Attention is currently required from: Ana Carolina Cabral. Nick Kochlowski has posted comments on this change by Ana Carolina Cabral. ( https://review.coreboot.org/c/coreboot/+/85493?usp=email ) Change subject: mb/amd/birman_plus: Update PCIe Slot configurations ...................................................................... Patch Set 21: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/85493?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia310ea616006479b9a052afb99d08df6a11431f4 Gerrit-Change-Number: 85493 Gerrit-PatchSet: 21 Gerrit-Owner: Ana Carolina Cabral <ana.cpmelo95(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Nick Kochlowski <nickkochlowski(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ana Carolina Cabral <ana.cpmelo95(a)gmail.com> Gerrit-Comment-Date: Fri, 24 Jan 2025 13:28:59 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: mb/google/trulo/var/uldrenite: Add fw_config probe for touchscreen
by John Su (Code Review) 24 Jan '25

24 Jan '25

John Su has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86144?usp=email ) Change subject: mb/google/trulo/var/uldrenite: Add fw_config probe for touchscreen ...................................................................... mb/google/trulo/var/uldrenite: Add fw_config probe for touchscreen Use fw_config to probe touchscreen. BUG=b:392040004 BRANCH=firmware-trulo-15217.771.B TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: I63512e85052bce974ffb0b738164bea440bd413c Signed-off-by: John Su <john_su(a)compal.corp-partner.google.com> --- M src/mainboard/google/brya/variants/uldrenite/overridetree.cb M src/mainboard/google/brya/variants/uldrenite/variant.c 2 files changed, 50 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/86144/1 diff --git a/src/mainboard/google/brya/variants/uldrenite/overridetree.cb b/src/mainboard/google/brya/variants/uldrenite/overridetree.cb index f7ff776..927d0c4 100644 --- a/src/mainboard/google/brya/variants/uldrenite/overridetree.cb +++ b/src/mainboard/google/brya/variants/uldrenite/overridetree.cb @@ -1,3 +1,10 @@ +fw_config + field TOUCHSCREEN 4 4 + option TOUCHSCREEN_UNKNOWN 0 + option TOUCHSCREEN_NONE 1 + end +end + chip soc/intel/alderlake register "sagv" = "SaGv_Enabled" @@ -348,7 +355,9 @@ register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E17)" register "enable_delay_ms" = "1" register "has_power_resource" = "true" - device i2c 10 on end + device i2c 10 on + probe TOUCHSCREEN TOUCHSCREEN_UNKNOWN + end end # EKTH5012 chip drivers/i2c/hid register "generic.hid" = ""ELAN900C"" @@ -364,7 +373,9 @@ register "generic.stop_delay_ms" = "150" register "generic.has_power_resource" = "1" register "hid_desc_reg_offset" = "0x01" - device i2c 16 on end + device i2c 16 on + probe TOUCHSCREEN TOUCHSCREEN_UNKNOWN + end end # EKTH7D18 chip drivers/i2c/hid register "generic.hid" = ""GXTP7996"" @@ -379,7 +390,9 @@ register "generic.enable_delay_ms" = "10" register "generic.has_power_resource" = "1" register "hid_desc_reg_offset" = "0x01" - device i2c 5d on end + device i2c 5d on + probe TOUCHSCREEN TOUCHSCREEN_UNKNOWN + end end # GXTP7996 chip drivers/i2c/hid register "generic.hid" = ""WDHT0002"" @@ -394,7 +407,9 @@ register "generic.enable_delay_ms" = "1" register "generic.has_power_resource" = "1" register "hid_desc_reg_offset" = "0x20" - device i2c 2c on end + device i2c 2c on + probe TOUCHSCREEN TOUCHSCREEN_UNKNOWN + end end # WDT8752A chip drivers/i2c/hid register "generic.hid" = ""WDHT2601"" @@ -409,7 +424,9 @@ register "generic.enable_delay_ms" = "1" register "generic.has_power_resource" = "1" register "hid_desc_reg_offset" = "0x20" - device i2c 3c on end + device i2c 3c on + probe TOUCHSCREEN TOUCHSCREEN_UNKNOWN + end end # WDT8790A chip drivers/i2c/hid register "generic.hid" = ""GTCH7502"" @@ -424,7 +441,9 @@ register "generic.enable_delay_ms" = "30" register "generic.has_power_resource" = "1" register "hid_desc_reg_offset" = "0x01" - device i2c 40 on end + device i2c 40 on + probe TOUCHSCREEN TOUCHSCREEN_UNKNOWN + end end # GTCH7502 end # I2C5 device ref pcie_rp2 on diff --git a/src/mainboard/google/brya/variants/uldrenite/variant.c b/src/mainboard/google/brya/variants/uldrenite/variant.c index 753abb6..96b2291 100644 --- a/src/mainboard/google/brya/variants/uldrenite/variant.c +++ b/src/mainboard/google/brya/variants/uldrenite/variant.c @@ -4,6 +4,7 @@ #include <baseboard/variants.h> #include <console/console.h> #include <delay.h> +#include <fw_config.h> #define RW350R_RST_DELAY_MS 20 #define RW350R_PERST_DELAY_MS 30 @@ -21,6 +22,30 @@ PAD_CFG_GPO(GPP_F13, 1, DEEP), }; +static const struct pad_config touchscreen_disable_pads[] = { + /* A21 : TCHSCR_REPORT_EN */ + PAD_NC(GPP_A21, NONE), + /* B16 : SOC_I2C_TCHSCR_SDA */ + PAD_NC(GPP_B16, NONE), + /* B17 : SOC_I2C_TCHSCR_SCL */ + PAD_NC(GPP_B17, NONE), + /* D15 : TCHSCR_RST_L */ + PAD_NC(GPP_D15, NONE), + /* D16 : TCHSCR_INT_ODL */ + PAD_NC(GPP_D16, NONE), + /* E17 : EN_PP3300_TCHSCR_X */ + PAD_NC(GPP_E17, NONE), +}; + +void fw_config_gpio_padbased_override(struct pad_config *padbased_table) +{ + if (fw_config_probe(FW_CONFIG(TOUCHSCREEN, TOUCHSCREEN_NONE))) { + printk(BIOS_INFO, "Disable touchscreen GPIO pins.\n"); + gpio_padbased_override(padbased_table, touchscreen_disable_pads, + ARRAY_SIZE(touchscreen_disable_pads)); + } +} + void variant_init(void) { /* -- To view, visit https://review.coreboot.org/c/coreboot/+/86144?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I63512e85052bce974ffb0b738164bea440bd413c Gerrit-Change-Number: 86144 Gerrit-PatchSet: 1 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com>

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[XL] Change in coreboot[main]: mb/novacustom: add V5x0TU board (Meteor Lake)
by Michał Żygowski (Code Review) 24 Jan '25

24 Jan '25

Attention is currently required from: Maciej Pijanowski, Michał Kopeć, Paul Menzel, Tim Crawford. Michał Żygowski has posted comments on this change by Michał Kopeć. ( https://review.coreboot.org/c/coreboot/+/82673?usp=email ) Change subject: mb/novacustom: add V5x0TU board (Meteor Lake) ...................................................................... Patch Set 25: (2 comments) File src/mainboard/novacustom/mtl-h/romstage.c: https://review.coreboot.org/c/coreboot/+/82673/comment/c344cbf2_74140616?us… : PS21, Line 13: .rcomp = { : /* Values for MTL-H DDR5 2R */ : .resistor = 100, : : .targets = {70, 30, 25, 25, 25}, : }, > You're right, removed. Done File src/mainboard/novacustom/mtl-h/romstage.c: https://review.coreboot.org/c/coreboot/+/82673/comment/32d7a0fb_b3821736?us… : PS25, Line 18: .dq_pins_interleaved = false, No need to initialize the field if its value is 0/false. -- To view, visit https://review.coreboot.org/c/coreboot/+/82673?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I82c73ddb1e76a9baf9b97e13124aa249ae1c2771 Gerrit-Change-Number: 82673 Gerrit-PatchSet: 25 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Fri, 24 Jan 2025 11:01:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michał Żygowski <michal.zygowski(a)3mdeb.com> Comment-In-Reply-To: Michał Kopeć <michal.kopec(a)3mdeb.com>

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[XS] Change in coreboot[main]: MAINTAINERS: Add Matt as a maintainer for Star Labs
by Sean Rhodes (Code Review) 24 Jan '25

24 Jan '25

Sean Rhodes has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86141?usp=email ) Change subject: MAINTAINERS: Add Matt as a maintainer for Star Labs ...................................................................... MAINTAINERS: Add Matt as a maintainer for Star Labs Change-Id: I47f51645e4f8dd8e8da8e527fd498af570a857e4 Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86141 Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M MAINTAINERS 1 file changed, 1 insertion(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved diff --git a/MAINTAINERS b/MAINTAINERS index fd86704..2ed4e22 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -631,6 +631,7 @@ STAR LABS MAINBOARDS M: Sean Rhodes <sean(a)starlabs.systems> +M: Matt DeVillier <matt.devillier(a)gmail.com> S: Maintained F: src/mainboard/starlabs/ -- To view, visit https://review.coreboot.org/c/coreboot/+/86141?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I47f51645e4f8dd8e8da8e527fd498af570a857e4 Gerrit-Change-Number: 86141 Gerrit-PatchSet: 2 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: soc/intel/pantherlake: Enable FSP debug log level control using CBFS
by Subrata Banik (Code Review) 24 Jan '25

24 Jan '25

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86002?usp=email ) Change subject: soc/intel/pantherlake: Enable FSP debug log level control using CBFS ...................................................................... soc/intel/pantherlake: Enable FSP debug log level control using CBFS This allows controlling the FSP debug log level using CBFS RAW binary files, providing more flexibility in debugging silicon firmware issues with a debug AP FW binary. The following CBFS files are used to determine the log levels: - fsp_pcd_debug_level: For the overall FSP debug log level. - fsp_mrc_debug_level: For the MRC (Memory Reference Code) debug log level. This capability is particularly useful when debugging issues that require examining both silicon and MRC logs simultaneously. BUG=b:227151510 TEST=Able to control the FSP debug log based on CBFS options To inject the fsp_pcd_debug_level and fsp_mrc_debug_level CBFS files with the desired log level, run: ``` cbfstool image-fatcat.serial.bin add-int -i 5 -n option/fsp_pcd_debug_level cbfstool image-fatcat.serial.bin add-int -i 5 -n option/fsp_mrc_debug_level ``` Change-Id: Ia2fc07188afde34d61ce8d50d3d722de48228e37 Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86002 Reviewed-by: Jérémy Compostella <jeremy.compostella(a)intel.com> Reviewed-by: Julius Werner <jwerner(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> --- M src/soc/intel/pantherlake/fsp_params.c M src/soc/intel/pantherlake/romstage/fsp_params.c 2 files changed, 9 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Jérémy Compostella: Looks good to me, approved Julius Werner: Looks good to me, approved Kapil Porwal: Looks good to me, approved diff --git a/src/soc/intel/pantherlake/fsp_params.c b/src/soc/intel/pantherlake/fsp_params.c index dfc47c6..a78059d 100644 --- a/src/soc/intel/pantherlake/fsp_params.c +++ b/src/soc/intel/pantherlake/fsp_params.c @@ -3,6 +3,7 @@ #include <bootmode.h> #include <cpu/intel/microcode.h> #include <fsp/api.h> +#include <fsp/debug.h> #include <fsp/fsp_debug_event.h> #include <fsp/fsp_gop_blt.h> #include <fsp/ppi/mp_service_ppi.h> @@ -685,7 +686,7 @@ /* Assign FspEventHandler arch Upd to use coreboot debug event handler */ if (CONFIG(FSP_USES_CB_DEBUG_EVENT_HANDLER) && CONFIG(CONSOLE_SERIAL) - && CONFIG(FSP_ENABLE_SERIAL_DEBUG)) + && CONFIG(FSP_ENABLE_SERIAL_DEBUG) && fsp_get_pcd_debug_log_level()) s_arch_cfg->FspEventHandler = (uintptr_t)((FSP_EVENT_HANDLER *) fsp_debug_event_handler); diff --git a/src/soc/intel/pantherlake/romstage/fsp_params.c b/src/soc/intel/pantherlake/romstage/fsp_params.c index 2bb4d21..7d965fd 100644 --- a/src/soc/intel/pantherlake/romstage/fsp_params.c +++ b/src/soc/intel/pantherlake/romstage/fsp_params.c @@ -2,6 +2,7 @@ #include <cpu/intel/common/common.h> #include <cpu/x86/msr.h> +#include <fsp/debug.h> #include <fsp/fsp_debug_event.h> #include <fsp/util.h> #include <intelblocks/cpulib.h> @@ -320,9 +321,12 @@ FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; FSPM_ARCHx_UPD *arch_upd = &mupd->FspmArchUpd; - enum fsp_log_level log_level = is_enabled ? fsp_map_console_log_level() : - FSP_LOG_LEVEL_DISABLE; - fsp_set_debug_level(m_cfg, log_level, log_level); + enum fsp_log_level fsp_log_level = is_enabled ? fsp_get_pcd_debug_log_level() : + FSP_LOG_LEVEL_DISABLE; + enum fsp_log_level mrc_log_level = is_enabled ? fsp_get_mrc_debug_log_level() : + FSP_LOG_LEVEL_DISABLE; + + fsp_set_debug_level(m_cfg, fsp_log_level, mrc_log_level); if ((m_cfg->PcdSerialDebugLevel > FSP_LOG_LEVEL_VERBOSE) || (m_cfg->SerialDebugMrcLevel > FSP_LOG_LEVEL_VERBOSE)) { -- To view, visit https://review.coreboot.org/c/coreboot/+/86002?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia2fc07188afde34d61ce8d50d3d722de48228e37 Gerrit-Change-Number: 86002 Gerrit-PatchSet: 12 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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