coreboot-gerrit January 2025

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[XS] Change in coreboot[main]: mb/starlabs/starlite_adl: Correct MODEM_CLKREQ configuration
by Sean Rhodes (Code Review) 24 Jan '25

24 Jan '25

Sean Rhodes has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86125?usp=email ) Change subject: mb/starlabs/starlite_adl: Correct MODEM_CLKREQ configuration ...................................................................... mb/starlabs/starlite_adl: Correct MODEM_CLKREQ configuration This GPIO is used as MODEM_CLKREQ, which is Native Function 1. Adjust the configuration accordingly. Change-Id: Icc8be62e620a3e51826fb7c2c040da317e7eb470 Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86125 Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c 1 file changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved diff --git a/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c b/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c index cb4308f..14e57c5 100644 --- a/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c +++ b/src/mainboard/starlabs/starlite_adl/variants/mk_v/gpio.c @@ -296,8 +296,8 @@ PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1), /* F4: CNV RF Reset */ PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), - /* F5: Not used MODEM_CLKREQ */ - PAD_CFG_NF(GPP_F5, NONE, DEEP, NF2), + /* F5: MODEM_CLKREQ */ + PAD_CFG_NF(GPP_F5, NONE, DEEP, NF1), /* F6: CNV PA Blanking */ PAD_NC(GPP_F6, NONE), /* F7: TBT LSX VCCIO Weak Internal PD 20K -- To view, visit https://review.coreboot.org/c/coreboot/+/86125?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icc8be62e620a3e51826fb7c2c040da317e7eb470 Gerrit-Change-Number: 86125 Gerrit-PatchSet: 2 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: soc/intel/meteorlake: Move CNVi control out of chipset.cb
by Sean Rhodes (Code Review) 24 Jan '25

24 Jan '25

Sean Rhodes has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86088?usp=email ) Change subject: soc/intel/meteorlake: Move CNVi control out of chipset.cb ...................................................................... soc/intel/meteorlake: Move CNVi control out of chipset.cb Not every board will use CNVi, so move this out of the chipset.cb and into devicetree. Change-Id: Ie12e828b2f0a65e46a526746bc06af288270d0d1 Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86088 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb M src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb M src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb M src/mainboard/system76/mtl/devicetree.cb M src/soc/intel/meteorlake/chipset.cb 5 files changed, 7 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved diff --git a/src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb b/src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb index bdebde5..19eb34e 100644 --- a/src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb +++ b/src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb @@ -1,4 +1,6 @@ chip soc/intel/meteorlake + # Enable CNVi WiFi + register "cnvi_wifi_core" = "true" # GPE configuration register "pmc_gpe0_dw0" = "GPP_D" diff --git a/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb b/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb index 55de7d2..04b7cf6 100644 --- a/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb +++ b/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb @@ -1,4 +1,6 @@ chip soc/intel/meteorlake + # Enable CNVi WiFi + register "cnvi_wifi_core" = "true" # GPE configuration register "pmc_gpe0_dw0" = "GPP_B" diff --git a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb index 45c8f0b..d4f2ea3 100644 --- a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb +++ b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb @@ -9,6 +9,8 @@ end chip soc/intel/meteorlake + # Enable CNVi WiFi + register "cnvi_wifi_core" = "true" # GPE configuration register "pmc_gpe0_dw0" = "GPP_B" diff --git a/src/mainboard/system76/mtl/devicetree.cb b/src/mainboard/system76/mtl/devicetree.cb index 0e1eaac..899788d 100644 --- a/src/mainboard/system76/mtl/devicetree.cb +++ b/src/mainboard/system76/mtl/devicetree.cb @@ -34,6 +34,7 @@ device ref ioe_shared_sram on end device ref pmc_shared_sram on end device ref cnvi_wifi on + register "cnvi_wifi_core" = "true" register "cnvi_bt_core" = "true" register "cnvi_bt_audio_offload" = "true" chip drivers/wifi/generic diff --git a/src/soc/intel/meteorlake/chipset.cb b/src/soc/intel/meteorlake/chipset.cb index 865b3d0..9087dd8 100644 --- a/src/soc/intel/meteorlake/chipset.cb +++ b/src/soc/intel/meteorlake/chipset.cb @@ -29,9 +29,6 @@ # Temporary setting TCC of 90C = Tj max (110) - TCC_Offset (20) register "tcc_offset" = "20" - # Enable CNVi WiFi - register "cnvi_wifi_core" = "true" - device domain 0 on device pci 00.0 alias system_agent on end device pci 01.0 alias pcie_rp12 off end -- To view, visit https://review.coreboot.org/c/coreboot/+/86088?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie12e828b2f0a65e46a526746bc06af288270d0d1 Gerrit-Change-Number: 86088 Gerrit-PatchSet: 5 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com>

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[XS] Change in coreboot[main]: soc/intel/alderlake: Fix incorrect reporting of S0ix
by Sean Rhodes (Code Review) 24 Jan '25

24 Jan '25

Sean Rhodes has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86089?usp=email ) ( 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/intel/alderlake: Fix incorrect reporting of S0ix ...................................................................... soc/intel/alderlake: Fix incorrect reporting of S0ix If S0ix is not enabled, then it should not be reported that it is supported. TEST=boot linux on starlabs/starlite_adl, check s2idle isn't listed under `/sys/power/mem_sleep`. Change-Id: Ia31fbfd0b9795990b0ca98220bb002bf2c3857b2 Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86089 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> --- M src/soc/intel/alderlake/cpu.c 1 file changed, 4 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved diff --git a/src/soc/intel/alderlake/cpu.c b/src/soc/intel/alderlake/cpu.c index 00c683c..9e4ed52 100644 --- a/src/soc/intel/alderlake/cpu.c +++ b/src/soc/intel/alderlake/cpu.c @@ -323,6 +323,10 @@ uint8_t get_supported_lpm_mask(void) { + const config_t *conf = config_of_soc(); + if (!conf->s0ix_enable) + return 0; + enum adl_cpu_type type = get_adl_cpu_type(); switch (type) { case ADL_M: /* fallthrough */ -- To view, visit https://review.coreboot.org/c/coreboot/+/86089?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia31fbfd0b9795990b0ca98220bb002bf2c3857b2 Gerrit-Change-Number: 86089 Gerrit-PatchSet: 4 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

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[XS] Change in coreboot[main]: soc/intel/alderlake: Fix incorrect reporting of S0ix
by Sean Rhodes (Code Review) 24 Jan '25

24 Jan '25

Attention is currently required from: Dinesh Gehlot, Intel coreboot Reviewers, Jayvik Desai, Jérémy Compostella, Kapil Porwal, Matt DeVillier, Nick Vaccaro, Paul Menzel. Sean Rhodes has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/86089?usp=email ) Change subject: soc/intel/alderlake: Fix incorrect reporting of S0ix ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: > I found only four occurrences of this function. You are taking care of one. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/86089?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia31fbfd0b9795990b0ca98220bb002bf2c3857b2 Gerrit-Change-Number: 86089 Gerrit-PatchSet: 3 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Fri, 24 Jan 2025 19:59:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sean Rhodes <sean(a)starlabs.systems> Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com>

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[S] Change in coreboot[main]: soc/intel/{meteorlake,pantherlake,tigerlake}: Fix incorrect reporting...
by Sean Rhodes (Code Review) 24 Jan '25

24 Jan '25

Sean Rhodes has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/86133?usp=email ) Change subject: soc/intel/{meteorlake,pantherlake,tigerlake}: Fix incorrect reporting of S0ix ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/86133?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifcf70d127cdea64bdf42cbc9a60dfc4ec740615a Gerrit-Change-Number: 86133 Gerrit-PatchSet: 3 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 24 Jan 2025 19:59:16 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: mb/google/fatcat: Enable s0ix
by Jamie Ryu (Code Review) 24 Jan '25

24 Jan '25

Jamie Ryu has posted comments on this change by Jamie Ryu. ( https://review.coreboot.org/c/coreboot/+/84923?usp=email ) Change subject: mb/google/fatcat: Enable s0ix ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/84923?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I80c65782830a2a22a9e8bb39615717a11183d30f Gerrit-Change-Number: 84923 Gerrit-PatchSet: 1 Gerrit-Owner: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 24 Jan 2025 19:03:53 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: mb/starlabs/*: Drop PNP definition for 4e.00
by Matt DeVillier (Code Review) 24 Jan '25

24 Jan '25

Attention is currently required from: Sean Rhodes. Matt DeVillier has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/86147?usp=email ) Change subject: mb/starlabs/*: Drop PNP definition for 4e.00 ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86147?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6d9c3982b128e1480bc0948e19825465274dd769 Gerrit-Change-Number: 86147 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Comment-Date: Fri, 24 Jan 2025 17:34:45 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: mb/google/brox/var/lotso: Update gpio setting
by 9elements QA (Code Review) 24 Jan '25

24 Jan '25

9elements QA has posted comments on this change by Jian Tong. ( https://review.coreboot.org/c/coreboot/+/85966?usp=email ) Change subject: mb/google/brox/var/lotso: Update gpio setting ...................................................................... Patch Set 2: Automatic boot test returned (PASS/FAIL/TOTAL): 11 / 1 / 12 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/230790 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/230788 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/230787 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/230786 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/230785 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/230784 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/230783 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/230782 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/230781 FAIL: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/230780 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/230779 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/230778 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/85966?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I132b43fd552d2babfbcd497bc6a017f354c69e10 Gerrit-Change-Number: 85966 Gerrit-PatchSet: 2 Gerrit-Owner: Jian Tong <tongjian(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Bob Moragues <moragues(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Marx Wang <marx.wang(a)intel.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Jinfang Mao <maojinfang(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Fri, 24 Jan 2025 17:32:57 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: mb/starlabs/*: Drop PNP definition for 4e.00
by Sean Rhodes (Code Review) 24 Jan '25

24 Jan '25

Sean Rhodes has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/86147?usp=email ) Change subject: mb/starlabs/*: Drop PNP definition for 4e.00 ...................................................................... Patch Set 1: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/86147?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6d9c3982b128e1480bc0948e19825465274dd769 Gerrit-Change-Number: 86147 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 24 Jan 2025 17:03:32 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: mb/google/dedede: Select INTEL_CRASHLOG only for ChromeOS builds
by Sowmya Aralguppe (Code Review) 24 Jan '25

24 Jan '25

Attention is currently required from: Balaji Manigandan, Intel coreboot Reviewers, Jakub Czapiga, Jędrzej Ciupis, Matt DeVillier, Pratikkumar V Prajapati, Subrata Banik. Sowmya Aralguppe has posted comments on this change by Matt DeVillier. ( https://review.coreboot.org/c/coreboot/+/84359?usp=email ) Change subject: mb/google/dedede: Select INTEL_CRASHLOG only for ChromeOS builds ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: > would like to get some resolution here - either get this patch merged to fix dedede boards, or if cr […] CPU Crashlog capability is missing in the crashlog device 0.a.0 hence CPU crashlog is not working - CrashLog DVSEC should be present in CFG address 0x120 in device 10. Read ID for Telemetry: 0x0 differs from expected: 0x23 CPU crashlog capability not found. PMC crashLog size in legacy mode : 0xD00 legacy mode PMC crashlog size adjusted to: 0x0 m_cpu_crashLog_size : 0x0 bytes Skipping CPU crashLog collection. Data not present. working on a workaround for this issue -- To view, visit https://review.coreboot.org/c/coreboot/+/84359?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I53be4befe9a04bdaece21f40f93af6599baa7e0b Gerrit-Change-Number: 84359 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Reviewer: Balaji Manigandan <balaji.bmg(a)gmail.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jędrzej Ciupis <jciupis(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Jędrzej Ciupis <jciupis(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Balaji Manigandan <balaji.bmg(a)gmail.com> Gerrit-Attention: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Comment-Date: Fri, 24 Jan 2025 16:47:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com>

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coreboot-gerrit January 2025