coreboot-gerrit January 2025

coreboot-gerrit@coreboot.org

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[XS] Change in coreboot[main]: Revert "soc/intel/alderlake: Disable UFS controllers only on S5 resume"
by Subrata Banik (Code Review) 25 Jan '25

25 Jan '25

Attention is currently required from: Dinesh Gehlot, Intel coreboot Reviewers, Jayvik Desai, Jérémy Compostella, Kapil Porwal, Karthik Ramasubramanian, Nick Vaccaro. Subrata Banik has posted comments on this change by Karthik Ramasubramanian. ( https://review.coreboot.org/c/coreboot/+/86111?usp=email ) Change subject: Revert "soc/intel/alderlake: Disable UFS controllers only on S5 resume" ...................................................................... Patch Set 4: (1 comment) File src/soc/intel/alderlake/romstage/romstage.c: https://review.coreboot.org/c/coreboot/+/86111/comment/d772110b_94164fdc?us… : PS4, Line 202: ps->prev_sleep_state == ACPI_S5 We are only issuing a warm reset post UFS disablement in the S5 flow. What would happen if the reset type is not S5 (and some other reset type introduces this issue) and UFS is disabled but does not hit warm reset? I guess the only corner case you have seen so far where UFS is disabled but S0ix is not working (and it works after warm reset) is mostly due to the fact that you are disabling UFS on all boots but only issuing a system reset in the S5 flow (so PMC is not aware of certain change in UFS state). I would like to understand what sleep types, other than S5, are encountering this issue. There are only four sleep types: S0, S3, S4, and S5. S3 and S4 are not supported, and S0 represents warm resets. This leaves us with S5 only. Does it make sense to check CSE reset types (looking at the CSE FW status register along with the S5 type) to cover this corner case as well? -- To view, visit https://review.coreboot.org/c/coreboot/+/86111?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1d7089a90bc42a2b36c26b05b81c1a2f12861fdc Gerrit-Change-Number: 86111 Gerrit-PatchSet: 4 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Bob Moragues <moragues(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Wentao Qin <qinwentao(a)huaqin.corp-partner.google.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Sat, 25 Jan 2025 07:17:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: Revert "mb/google/fatcat: Enable SAGv"
by Subrata Banik (Code Review) 25 Jan '25

25 Jan '25

Attention is currently required from: Bora Guvendik, Jayvik Desai, Kapil Porwal, Pranava Y N. Hello Bora Guvendik, Jayvik Desai, Kapil Porwal, Pranava Y N, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86154?usp=email to look at the new patch set (#2). Change subject: Revert "mb/google/fatcat: Enable SAGv" ...................................................................... Revert "mb/google/fatcat: Enable SAGv" This reverts commit 1e720b0a9b1cf35b9581824a47d57477a2b10a7f. Reason for revert: Resulted into MRC hang with ES1 SoC. Need to revert SaGv CL to unblock fatcat boot with ES1 SoC. Change-Id: I50041d6289b2d33aea5532ff563d32f09403d91b Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb 1 file changed, 0 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/86154/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86154?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I50041d6289b2d33aea5532ff563d32f09403d91b Gerrit-Change-Number: 86154 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com>

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[XS] Change in coreboot[main]: mb/google/fatcat: Enable SAGv
by Subrata Banik (Code Review) 25 Jan '25

25 Jan '25

Subrata Banik has created a revert of this change. ( https://review.coreboot.org/c/coreboot/+/85272?usp=email ) Change subject: mb/google/fatcat: Enable SAGv ...................................................................... -- To view, visit https://review.coreboot.org/c/coreboot/+/85272?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: revert Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I340f4951fd33deadaac53edd30e2cf6bfc2a750b Gerrit-Change-Number: 85272 Gerrit-PatchSet: 3 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com>

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[XS] Change in coreboot[main]: Revert "mb/google/fatcat: Enable SAGv"
by Subrata Banik (Code Review) 25 Jan '25

25 Jan '25

Attention is currently required from: Bora Guvendik, Pranava Y N. Hello Bora Guvendik, build bot (Jenkins), Pranava Y N, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/86154?usp=email to review the following change. Change subject: Revert "mb/google/fatcat: Enable SAGv" ...................................................................... Revert "mb/google/fatcat: Enable SAGv" This reverts commit 1e720b0a9b1cf35b9581824a47d57477a2b10a7f. Reason for revert: Resulted into MRC hang with ES1 SoC. Need to revert SaGv CL to unblock fatcat boot with ES1 SoC. Change-Id: I50041d6289b2d33aea5532ff563d32f09403d91b --- M src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb 1 file changed, 0 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/86154/1 diff --git a/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb b/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb index ec87353..b9dcbbd 100644 --- a/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb +++ b/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb @@ -30,9 +30,6 @@ register "tcss_ports[2]" = "TCSS_PORT_EMPTY" # Disable USB-C Port 2 register "tcss_ports[3]" = "TCSS_PORT_EMPTY" # Disable USB-C Port 3 - # Enable SAGv - register "sagv" = "SAGV_ENABLED" - # Enable s0ix register "s0ix_enable" = "false" -- To view, visit https://review.coreboot.org/c/coreboot/+/86154?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I50041d6289b2d33aea5532ff563d32f09403d91b Gerrit-Change-Number: 86154 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com>

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[M] Change in coreboot[main]: mb/asus/p8z77-v: Attempt to correctly route PCIe lanes
by Bill XIE (Code Review) 25 Jan '25

25 Jan '25

Attention is currently required from: Keith Hui. Bill XIE has posted comments on this change by Keith Hui. ( https://review.coreboot.org/c/coreboot/+/85413?usp=email ) Change subject: mb/asus/p8z77-v: Attempt to correctly route PCIe lanes ...................................................................... Patch Set 3: (1 comment) File src/mainboard/asus/p8x7x-series/variants/p8z77-v/early_init.c: https://review.coreboot.org/c/coreboot/+/85413/comment/9c8e4bc3_fb5f1ed6?us… : PS2, Line 77: {7, 34, 20, -1} > I saw your dumps and honestly I can't see I missed anything. […] https://send.aslaets.be/download/31cabd06aa987000/#KS26QEieJbuBewAJhgJQ_g , containing autoport dump and ramstage cbmem log, downloadable 5 times in 5 days. -- To view, visit https://review.coreboot.org/c/coreboot/+/85413?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If41197a1f817a48c209d25fc1ae461ec97ccf16c Gerrit-Change-Number: 85413 Gerrit-PatchSet: 3 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Keith Hui <buurin(a)gmail.com> Gerrit-Comment-Date: Sat, 25 Jan 2025 04:33:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Bill XIE <persmule(a)hardenedlinux.org> Comment-In-Reply-To: Keith Hui <buurin(a)gmail.com>

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[S] Change in coreboot[main]: soc/intel/{meteorlake,pantherlake,tigerlake}: Fix incorrect reporting...
by Subrata Banik (Code Review) 25 Jan '25

25 Jan '25

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Intel coreboot Reviewers, Jakub Czapiga, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Pranava Y N, Sean Rhodes, Tarun. Subrata Banik has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/86133?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: soc/intel/{meteorlake,pantherlake,tigerlake}: Fix incorrect reporting of S0ix ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/86133/comment/5a1c2a4c_40aaadef?us… : PS3, Line 7: meteorlake `mtl,ptl,tgl` might help to fit the title line < 72 ? -- To view, visit https://review.coreboot.org/c/coreboot/+/86133?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifcf70d127cdea64bdf42cbc9a60dfc4ec740615a Gerrit-Change-Number: 86133 Gerrit-PatchSet: 3 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Sat, 25 Jan 2025 03:36:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: soc/intel/{meteorlake,pantherlake,tigerlake}: Fix incorrect reporting...
by Subrata Banik (Code Review) 25 Jan '25

25 Jan '25

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Intel coreboot Reviewers, Jakub Czapiga, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Pranava Y N, Sean Rhodes, Tarun. Subrata Banik has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/86133?usp=email ) Change subject: soc/intel/{meteorlake,pantherlake,tigerlake}: Fix incorrect reporting of S0ix ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86133?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifcf70d127cdea64bdf42cbc9a60dfc4ec740615a Gerrit-Change-Number: 86133 Gerrit-PatchSet: 3 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Sat, 25 Jan 2025 03:36:10 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in blobs[main]: soc/mediatek/mt8196: Add mtk_fsp_romstage version v1.0
by Yidi Lin (Code Review) 25 Jan '25

25 Jan '25

Yidi Lin has submitted this change. ( https://review.coreboot.org/c/blobs/+/86110?usp=email ) Change subject: soc/mediatek/mt8196: Add mtk_fsp_romstage version v1.0 ...................................................................... soc/mediatek/mt8196: Add mtk_fsp_romstage version v1.0 mtk_fsp_romstage initializes power switch in romstage. TEST=Build pass BUG=b:373797027 Change-Id: Ice4a51f375a86693674545a7730b16e656c57ac4 Signed-off-by: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com> --- M soc/mediatek/mt8196/README.md A soc/mediatek/mt8196/mtk_fsp_romstage.elf A soc/mediatek/mt8196/mtk_fsp_romstage.elf.md5 A soc/mediatek/mt8196/mtk_fsp_romstage_release_notes.txt 4 files changed, 30 insertions(+), 0 deletions(-) Approvals: Yu-Ping Wu: Verified; Looks good to me, approved Yidi Lin: Looks good to me, approved diff --git a/soc/mediatek/mt8196/README.md b/soc/mediatek/mt8196/README.md index e64601b..be063d5 100644 --- a/soc/mediatek/mt8196/README.md +++ b/soc/mediatek/mt8196/README.md @@ -7,6 +7,7 @@ - spm_firmware.bin - gpueb_fw.img - pi_img.img +- mtk_fsp_romstage.elf -------------------------------------------------------------------------------- # MCUPM introduction @@ -235,3 +236,24 @@ `$ strings pi_img.img | grep "pi_img firmware"` -------------------------------------------------------------------------------- +# mtk_fsp_romstage.elf introduction +It is a new blob named MediaTek firmware support package (mtk-fsp) in romstage that includes: + +- power switch: It is a hardware design used to switch between two power inputs to determine + the output voltage. This design is typically applied to systems that require + dynamic voltage adjustment, such as the Constant Voltage, Constant Current of SRAM. + +## Who uses it +Coreboot loads `mtk_fsp_romstage.elf` during the first bootup. + +## How to load `mtk_fsp_romstage.elf` +Coreboot locates `mtk_fsp_romstage.elf` file, locates the entry point `_start()` to execute +`mtk_fsp_romstage.elf`. + +## Return values +0 on success; non-zero on failure. + +## Version +`$ strings mtk_fsp_romstage.elf | grep "interface version"` + +-------------------------------------------------------------------------------- diff --git a/soc/mediatek/mt8196/mtk_fsp_romstage.elf b/soc/mediatek/mt8196/mtk_fsp_romstage.elf new file mode 100644 index 0000000..9531fae --- /dev/null +++ b/soc/mediatek/mt8196/mtk_fsp_romstage.elf Binary files differ diff --git a/soc/mediatek/mt8196/mtk_fsp_romstage.elf.md5 b/soc/mediatek/mt8196/mtk_fsp_romstage.elf.md5 new file mode 100644 index 0000000..b549ff4 --- /dev/null +++ b/soc/mediatek/mt8196/mtk_fsp_romstage.elf.md5 @@ -0,0 +1 @@ +463e1b4fb3bae09d875f086164ddee92 *mtk_fsp_romstage.elf diff --git a/soc/mediatek/mt8196/mtk_fsp_romstage_release_notes.txt b/soc/mediatek/mt8196/mtk_fsp_romstage_release_notes.txt new file mode 100644 index 0000000..4bc3d98 --- /dev/null +++ b/soc/mediatek/mt8196/mtk_fsp_romstage_release_notes.txt @@ -0,0 +1,7 @@ +# 1.0 + +1. An official build from ChromeOS version 16169.0.0. + +2. Included changes: + +- CL:*7872928 mt8196: Add DPSW support -- To view, visit https://review.coreboot.org/c/blobs/+/86110?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: blobs Gerrit-Branch: main Gerrit-Change-Id: Ice4a51f375a86693674545a7730b16e656c57ac4 Gerrit-Change-Number: 86110 Gerrit-PatchSet: 4 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com>

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[XS] Change in coreboot[main]: Revert "soc/intel/alderlake: Disable UFS controllers only on S5 resume"
by Bob Moragues (Code Review) 25 Jan '25

25 Jan '25

Attention is currently required from: Dinesh Gehlot, Intel coreboot Reviewers, Jayvik Desai, Jérémy Compostella, Kapil Porwal, Karthik Ramasubramanian, Nick Vaccaro. Bob Moragues has posted comments on this change by Karthik Ramasubramanian. ( https://review.coreboot.org/c/coreboot/+/86111?usp=email ) Change subject: Revert "soc/intel/alderlake: Disable UFS controllers only on S5 resume" ...................................................................... Patch Set 4: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/86111?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1d7089a90bc42a2b36c26b05b81c1a2f12861fdc Gerrit-Change-Number: 86111 Gerrit-PatchSet: 4 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Bob Moragues <moragues(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Wentao Qin <qinwentao(a)huaqin.corp-partner.google.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Sat, 25 Jan 2025 00:22:08 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: mb/google/brox: Check to powergate the UFS controller
by Karthik Ramasubramanian (Code Review) 25 Jan '25

25 Jan '25

Attention is currently required from: Karthik Ramasubramanian. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86151?usp=email to look at the new patch set (#3). Change subject: mb/google/brox: Check to powergate the UFS controller ...................................................................... mb/google/brox: Check to powergate the UFS controller On boards with non-UFS storage, during certain kind of resets UFS controller is not powergated even though it is disabled. This leads to suspend/resume failures during that boot cycle. UFS controller is always disabled in romstage. If the UFS controller is disabled in devicetree and is not powergated, then trigger an extra reset for UFS disablement to take effect. BUG=b:391449110 TEST=Build Brox BIOS image and boot to OS. Ensure that when the device switches from normal mode to developer mode. [INFO ] ISH Status: 0x7f, UFS0 Status: 0x60 [ERROR] ISH and/or UFS not powergated. [INFO ] fw_config match found: RETIMER=RETIMER_JHL8040 [INFO ] CBFS: Found 'rts5453_retimer_jhl8040.hash' @0x92740 size 0x3 in mcache @0x76abc410 [INFO ] VB2:vb2_digest_init() 3 bytes, hash algo 2, HW acceleration enabled [INFO ] Triggering warm reset to disable UFS [INFO ] system_reset() called! Change-Id: I31f1cfc995a98bb345ac64ec3ae68a3bcc413f29 Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> --- M src/mainboard/google/brox/variants/baseboard/brox/Makefile.mk M src/mainboard/google/brox/variants/baseboard/brox/ramstage.c R src/mainboard/google/brox/variants/baseboard/brox/reset_check.c 3 files changed, 47 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/86151/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/86151?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I31f1cfc995a98bb345ac64ec3ae68a3bcc413f29 Gerrit-Change-Number: 86151 Gerrit-PatchSet: 3 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com>

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