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Change subject: soc/mediatek/mt8196: Correct MT6363 buck5 enable API
......................................................................
Patch Set 1:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/85838/comment/ee7dc351_2d70199a?us… :
PS1, Line 7: Correct MT6363 buck5 enable API
Fix MT6363 buck5 enablement API
https://review.coreboot.org/c/coreboot/+/85838/comment/4afbdcc9_5f57ead4?us… :
PS1, Line 9: MT6363 buck5 is not used in rauru/navi. Fixed the incorrect mask and
: offset in the enable API.
The MT6363 buck5 API's mask and offset settings were incorrect, preventing the buck from being disabled. This issue is resolved by correcting these two values.
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Change subject: testetsttestsetsete
......................................................................
Abandoned
It's just test.
Very Sorry...
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Change subject: testetsttestsetsete
......................................................................
testetsttestsetsete
Change-Id: I652bc4916f5c623be352d476b083098b8240d03d
Signed-off-by: test <test(a)test.com>
---
M Makefile
1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/85854/1
diff --git a/Makefile b/Makefile
index 491e702..c49f8c6 100644
--- a/Makefile
+++ b/Makefile
@@ -1,4 +1,5 @@
## SPDX-License-Identifier: BSD-3-Clause
+#testtest
ifneq ($(words $(CURDIR)),1)
$(error Error: Path to the main directory cannot contain spaces)
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Change subject: soc/mediatek/mt8196: Add PMIC MT6363 ADC driver
......................................................................
Patch Set 30:
(2 comments)
File src/soc/mediatek/common/mt6363_sdmadc.c:
https://review.coreboot.org/c/coreboot/+/85128/comment/006907a5_6673daff?us… :
PS30, Line 64: int
> Sorry, I just found a few problems when reviewing CB:85666. […]
https://review.coreboot.org/c/coreboot/+/85839https://review.coreboot.org/c/coreboot/+/85128/comment/69be0ddd_7ffc698c?us… :
PS30, Line 107: regval * chan->hw_info.ratio[0] * chan->hw_info.ref_volt
> @jarried.lin@mediatek. […]
Done in https://review.coreboot.org/c/coreboot/+/85839, regval uses u16 type.
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Change subject: soc/mediatek/mt8196: Correct MT6363 buck5 enable API
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
> Why does the solution modify the mask/offset instead of deleting the function?
Because the buck5 of mt6363 needs to be disabled in disable_pmic_ldo API.
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Change subject: soc/mediatek/mt8196: Add delay in pmif_spmi.c
......................................................................
Patch Set 3:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/85799/comment/9ea9956a_a9e7c4d8?us… :
PS2, Line 7: Add delay in pmif_spmi.c
> Can we be more specific? For example, `Delay 0.5ms before enabling cmd issue`. […]
The 500 microseconds delay is implemented to ensure that the two fields, inf_en and arb_en of the PMIF can be written successfully.
write32(&arb->mtk_pmif->inf_en, PMIF_SPMI_SW_CHAN);
write32(&arb->mtk_pmif->arb_en, PMIF_SPMI_SW_CHAN);
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Change subject: mb/asus/p8x7x-series: Add Z77-A as a variant
......................................................................
Patch Set 3:
(1 comment)
File src/mainboard/asus/p8x7x-series/variants/z77-a/hda/hda_verb.c:
PS1:
> Seems like an extra file which wasn't supposed to be committed?
It is. Thanks for the catch.
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Hello Nicholas Chin, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/85836?usp=email
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The following approvals got outdated and were removed:
Code-Review+1 by Nicholas Chin, Verified+1 by build bot (Jenkins)
Change subject: mb/asus/p8x7x-series: Add Z77-A as a variant
......................................................................
mb/asus/p8x7x-series: Add Z77-A as a variant
Constructed from a mix of similar boards, boardview and vendor firmware
analysis. Not hardware tested.
It has a RTL8111F LAN chip with no EEPROM for vital product data like
LED configurations or MAC addresses. User will need to set their MAC
address during 'make menuconfig'.
Change-Id: Id1a81b321c236bb1fd2763d69531958ef6f4b4e6
Signed-off-by: Keith Hui <buurin(a)gmail.com>
---
M src/mainboard/asus/p8x7x-series/Kconfig
M src/mainboard/asus/p8x7x-series/Kconfig.name
A src/mainboard/asus/p8x7x-series/variants/z77-a/board_info.txt
A src/mainboard/asus/p8x7x-series/variants/z77-a/cmos.default
A src/mainboard/asus/p8x7x-series/variants/z77-a/cmos.layout
A src/mainboard/asus/p8x7x-series/variants/z77-a/data.vbt
A src/mainboard/asus/p8x7x-series/variants/z77-a/early_init.c
A src/mainboard/asus/p8x7x-series/variants/z77-a/gma-mainboard.ads
A src/mainboard/asus/p8x7x-series/variants/z77-a/gpio.c
A src/mainboard/asus/p8x7x-series/variants/z77-a/hda_verb.c
A src/mainboard/asus/p8x7x-series/variants/z77-a/overridetree.cb
11 files changed, 516 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/85836/2
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Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Change subject: mb/asus/p8z77-v_lx2: Change super I/O chip to nct5535d
......................................................................
mb/asus/p8z77-v_lx2: Change super I/O chip to nct5535d
Boardview indicates this board uses the smaller superio/nuvoton/nct5535d.
Cut devices not present or remaining off from overridetree.
Builds, but not function tested.
Change-Id: Ie68f6f5b1be67ddabc8afee1dbd2db3c8b4f180b
Signed-off-by: Keith Hui <buurin(a)gmail.com>
---
M src/mainboard/asus/p8x7x-series/Kconfig
M src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/overridetree.cb
2 files changed, 4 insertions(+), 15 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/85835/2
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Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#2).
The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)
Change subject: superio/nuvoton: Add NCT5535D
......................................................................
superio/nuvoton: Add NCT5535D
NCT5535D is a 64-pin LPC super I/O chip found on many Asus P8x7x series
mainboards with no publicly available datasheet. However, based on
mb/asus/p8z77-v_lx2, this chip can probably be driven like a NCT6779D,
on which this is based.
Devices not present on this chip compared to NCT6779D are parallel port,
serial port B, GPIOs 0,1,3,6.
p8z77-v_lx2 still builds once modified for this chip, but is not
tested further.
Change-Id: I3fe0dd6fc3010a50b781ca7c5c39ea73b91978a5
Signed-off-by: Keith Hui <buurin(a)gmail.com>
---
A src/superio/nuvoton/nct5535d/Kconfig
A src/superio/nuvoton/nct5535d/Makefile.mk
A src/superio/nuvoton/nct5535d/acpi/superio.asl
A src/superio/nuvoton/nct5535d/nct5535d.h
A src/superio/nuvoton/nct5535d/superio.c
5 files changed, 302 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/85834/2
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