coreboot-gerrit January 2025

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[M] Change in coreboot[main]: nb/sandybridge: Implement adjustable DRAM voltages
by Riku Viitanen (Code Review) 25 Jan '25

25 Jan '25

Attention is currently required from: Angel Pons, Intel coreboot Reviewers, Riku Viitanen. Hello Angel Pons, Intel coreboot Reviewers, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85793?usp=email to look at the new patch set (#15). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: nb/sandybridge: Implement adjustable DRAM voltages ...................................................................... nb/sandybridge: Implement adjustable DRAM voltages Many mainboards implement adjustable voltage rails for DRAM and other components. For example, on cold start, ASRock Z77 Extreme4's DRAM voltage regulator defaults to 1.6V and an SMBus connected current DAC is used to offset this to achieve the desired operating voltage. Sensible default limits of 1.25V-1.65V are implemented. Mainboards define their hardware's limits in Kconfig. Users can choose between the default automatic selection mode and select upper and lower limits or set a voltage manually in Kconfig, within mainboard hardware limits. Automatic voltage selection takes into account both SPD and XMP data. Care is taken to not undervolt or overvolt any modules according to their own reported specifications. Current choice favours higher performance. Still, if no XMP profile is used due to their requested voltages being too high for any other DIMM or the system, or XMP data simply not existing, the lowest supported voltage is used instead. This strategy is similar enough to at least two OEM firmwares observed: ASRock Z77 Extreme4 and ASUS P8H67-I DELUXE. ASRock was tested with i7-3770K and DDR3 XMP and non-XMP DIMMs in various combinations. ASUS was tested with i5-2500K and various DDR3 and DDR3L SO-DIMMs. Since hardware implementations differ, once suitable voltage is selected, a callback "set_dram_voltage()" is called to do the actual voltage setting. Mainboards need to implement this in romstage, or use a driver like CB:85887. Change-Id: I1a8857deee85fd635429afd3cbf93cad7a7d589b Signed-off-by: Riku Viitanen <riku.viitanen(a)protonmail.com> --- M src/northbridge/intel/sandybridge/Kconfig M src/northbridge/intel/sandybridge/raminit.c M src/northbridge/intel/sandybridge/raminit_common.h M src/northbridge/intel/sandybridge/raminit_native.c M src/northbridge/intel/sandybridge/sandybridge.h 5 files changed, 131 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/85793/15 -- To view, visit https://review.coreboot.org/c/coreboot/+/85793?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1a8857deee85fd635429afd3cbf93cad7a7d589b Gerrit-Change-Number: 85793 Gerrit-PatchSet: 15 Gerrit-Owner: Riku Viitanen <riku.viitanen(a)protonmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Riku Viitanen <riku.viitanen(a)protonmail.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com>

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[XS] Change in coreboot[main]: util/crossgcc: Add missing printf variable
by Raul Rangel (Code Review) 24 Jan '25

24 Jan '25

Attention is currently required from: Jon Murphy, Karthik Ramasubramanian, Martin L Roth. Raul Rangel has posted comments on this change by Jon Murphy. ( https://review.coreboot.org/c/coreboot/+/86148?usp=email ) Change subject: util/crossgcc: Add missing printf variable ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86148?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I195718e43ea842970f5fa986315c9e9f11395362 Gerrit-Change-Number: 86148 Gerrit-PatchSet: 2 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Fri, 24 Jan 2025 22:29:40 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: util/crossgcc: Add missing printf variable
by Jon Murphy (Code Review) 24 Jan '25

24 Jan '25

Attention is currently required from: Karthik Ramasubramanian, Martin L Roth, Raul Rangel. Jon Murphy has posted comments on this change by Jon Murphy. ( https://review.coreboot.org/c/coreboot/+/86148?usp=email ) Change subject: util/crossgcc: Add missing printf variable ...................................................................... Patch Set 2: (2 comments) File util/crossgcc/buildgcc: https://review.coreboot.org/c/coreboot/+/86148/comment/9585977f_f8863f06?us… : PS1, Line 859: ${LIBSTDCXX_INCLUDE_PATH} > Quote this too, or change it to `[[ ]]` Done https://review.coreboot.org/c/coreboot/+/86148/comment/e434975d_eee64eb6?us… : PS1, Line 861: ${LIBSTDCXX_INCLUDE_PATH} > Quotes Done -- To view, visit https://review.coreboot.org/c/coreboot/+/86148?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I195718e43ea842970f5fa986315c9e9f11395362 Gerrit-Change-Number: 86148 Gerrit-PatchSet: 2 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Fri, 24 Jan 2025 22:27:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org>

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[XS] Change in coreboot[main]: util/crossgcc: Add missing printf variable
by Raul Rangel (Code Review) 24 Jan '25

24 Jan '25

Attention is currently required from: Jon Murphy, Karthik Ramasubramanian, Martin L Roth. Raul Rangel has posted comments on this change by Jon Murphy. ( https://review.coreboot.org/c/coreboot/+/86148?usp=email ) Change subject: util/crossgcc: Add missing printf variable ...................................................................... Patch Set 1: (1 comment) File util/crossgcc/buildgcc: https://review.coreboot.org/c/coreboot/+/86148/comment/4bd6ca5f_e486373c?us… : PS1, Line 859: ${LIBSTDCXX_INCLUDE_PATH} Quote this too, or change it to `[[ ]]` -- To view, visit https://review.coreboot.org/c/coreboot/+/86148?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I195718e43ea842970f5fa986315c9e9f11395362 Gerrit-Change-Number: 86148 Gerrit-PatchSet: 1 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Fri, 24 Jan 2025 21:53:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: util/crossgcc: Add missing printf variable
by Raul Rangel (Code Review) 24 Jan '25

24 Jan '25

Attention is currently required from: Jon Murphy, Karthik Ramasubramanian, Martin L Roth. Raul Rangel has posted comments on this change by Jon Murphy. ( https://review.coreboot.org/c/coreboot/+/86148?usp=email ) Change subject: util/crossgcc: Add missing printf variable ...................................................................... Patch Set 1: Code-Review+2 (2 comments) File util/crossgcc/buildgcc: https://review.coreboot.org/c/coreboot/+/86148/comment/704e68bc_76e379a4?us… : PS1, Line 861: printf Odd choice of using printf over string substitution. https://review.coreboot.org/c/coreboot/+/86148/comment/a26dc9bb_09ca5687?us… : PS1, Line 861: ${LIBSTDCXX_INCLUDE_PATH} Quotes -- To view, visit https://review.coreboot.org/c/coreboot/+/86148?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I195718e43ea842970f5fa986315c9e9f11395362 Gerrit-Change-Number: 86148 Gerrit-PatchSet: 1 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Fri, 24 Jan 2025 21:52:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: Revert "soc/intel/alderlake: Disable UFS controllers only on S5 resume"
by Karthik Ramasubramanian (Code Review) 24 Jan '25

24 Jan '25

Attention is currently required from: Dinesh Gehlot, Intel coreboot Reviewers, Jayvik Desai, Jérémy Compostella, Kapil Porwal, Karthik Ramasubramanian, Nick Vaccaro. Hello Dinesh Gehlot, Intel coreboot Reviewers, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86111?usp=email to look at the new patch set (#3). Change subject: Revert "soc/intel/alderlake: Disable UFS controllers only on S5 resume" ...................................................................... Revert "soc/intel/alderlake: Disable UFS controllers only on S5 resume" This reverts commit 5e580c79dfd43387e6d375c94c6d95c520189111. On boards with non-UFS storage, currently UFS controller is disabled only when the system is coming out of S5 sleep state. On certain kind of resets during boot flow, this leaves some UFS resources turned on and causing the suspend failure. To fix this issue, disable UFS controller on every boot cycle. BUG=b:391449110 TEST=Build Brox BIOS image and boot to OS. Ensure that when the device switches from normal mode to developer mode and vice-versa, the device is able to suspend/resume successfully. Change-Id: I1d7089a90bc42a2b36c26b05b81c1a2f12861fdc Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> --- M src/soc/intel/alderlake/romstage/romstage.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/86111/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/86111?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1d7089a90bc42a2b36c26b05b81c1a2f12861fdc Gerrit-Change-Number: 86111 Gerrit-PatchSet: 3 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Bob Moragues <moragues(a)google.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Wentao Qin <qinwentao(a)huaqin.corp-partner.google.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com>

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[S] Change in coreboot[main]: mb/google/brox: Check to powergate the UFS controller
by Karthik Ramasubramanian (Code Review) 24 Jan '25

24 Jan '25

Attention is currently required from: Karthik Ramasubramanian. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86151?usp=email to look at the new patch set (#2). Change subject: mb/google/brox: Check to powergate the UFS controller ...................................................................... mb/google/brox: Check to powergate the UFS controller On boards with non-UFS storage, during certain kind of resets UFS controller is not powergated even though it is disabled. This leads to suspend/resume failures during that boot cycle. UFS controller is always disabled in romstage. If the UFS controller is disabled in devicetree and is not powergated, then trigger an extra reset for UFS disablement to take effect. BUG=b:391449110 TEST=Build Brox BIOS image and boot to OS. Ensure that when the device switches from normal mode to developer mode. Change-Id: I31f1cfc995a98bb345ac64ec3ae68a3bcc413f29 Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> --- M src/mainboard/google/brox/variants/baseboard/brox/Makefile.mk M src/mainboard/google/brox/variants/baseboard/brox/ramstage.c R src/mainboard/google/brox/variants/baseboard/brox/reset_check.c 3 files changed, 46 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/86151/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86151?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I31f1cfc995a98bb345ac64ec3ae68a3bcc413f29 Gerrit-Change-Number: 86151 Gerrit-PatchSet: 2 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com>

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[S] Change in coreboot[main]: mb/google/brox: Check to powergate the UFS controller
by Karthik Ramasubramanian (Code Review) 24 Jan '25

24 Jan '25

Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86151?usp=email ) Change subject: mb/google/brox: Check to powergate the UFS controller ...................................................................... mb/google/brox: Check to powergate the UFS controller On boards with non-UFS storage, during certain kind of resets UFS controller is not powergated even though it is disabled. This leads to suspend/resume failures during that boot cycle. UFS controller is always disabled in romstage. If the UFS controller is disabled in devicetree and is not powergated, then trigger an extra reset for UFS disablement to take effect. BUG=b:391449110 TEST=Build Brox BIOS image and boot to OS. Ensure that when the device switches from normal mode to developer mode. Change-Id: I31f1cfc995a98bb345ac64ec3ae68a3bcc413f29 --- M src/mainboard/google/brox/variants/baseboard/brox/Makefile.mk M src/mainboard/google/brox/variants/baseboard/brox/ramstage.c R src/mainboard/google/brox/variants/baseboard/brox/reset_check.c 3 files changed, 46 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/86151/1 diff --git a/src/mainboard/google/brox/variants/baseboard/brox/Makefile.mk b/src/mainboard/google/brox/variants/baseboard/brox/Makefile.mk index b3149ba..eb8625d 100644 --- a/src/mainboard/google/brox/variants/baseboard/brox/Makefile.mk +++ b/src/mainboard/google/brox/variants/baseboard/brox/Makefile.mk @@ -4,10 +4,11 @@ romstage-y += memory.c romstage-y += gpio.c -romstage-y += romstage.c +romstage-y += reset_check.c romstage-$(CONFIG_MAINBOARD_USE_EARLY_LIBGFXINIT) += gma-mainboard.ads ramstage-y += gpio.c ramstage-y += ramstage.c +ramstage-y += reset_check.c smm-$(CONFIG_SMMSTORE) += gpio.c diff --git a/src/mainboard/google/brox/variants/baseboard/brox/ramstage.c b/src/mainboard/google/brox/variants/baseboard/brox/ramstage.c index f079d7a..3ac9dbd 100644 --- a/src/mainboard/google/brox/variants/baseboard/brox/ramstage.c +++ b/src/mainboard/google/brox/variants/baseboard/brox/ramstage.c @@ -2,11 +2,14 @@ #include <acpi/acpi_device.h> #include <baseboard/variants.h> +#include <bootstate.h> +#include <cf9_reset.h> #include <console/console.h> #include <device/pci_ops.h> #include <drivers/intel/dptf/chip.h> #include <ec/google/chromeec/ec.h> #include <intelblocks/power_limit.h> +#include <intelblocks/pmclib.h> #include <soc/pci_devs.h> #include <static.h> @@ -100,3 +103,44 @@ settings->pl1.min_power, settings->pl1.max_power, settings->pl2.min_power, settings->pl2.max_power, soc_config->tdp_pl4); } + +#define PMC_PCH_ISH_IP_PG_STS_OFFSET 0x1D92 +#define ISH_PG_STS BIT(1) + +#define PMC_PCH_UFS0_IP_PG_STS_OFFSET 0x1D96 +#define UFS0_PG_STS BIT(4) + +extern bool mainboard_expects_another_reset(void); + +static uint8_t pmc_get_pch_ip_pg_sts(uint32_t offset) +{ + uint8_t val = 0; + uintptr_t pmc_bar; + + pmc_bar = soc_read_pmc_base(); + val = read8p(pmc_bar + offset); + return val; +} + +static bool is_ish_and_ufs_powergated(void) +{ + uint8_t ish_pg_sts = pmc_get_pch_ip_pg_sts(PMC_PCH_ISH_IP_PG_STS_OFFSET); + uint8_t ufs0_pg_sts = pmc_get_pch_ip_pg_sts(PMC_PCH_UFS0_IP_PG_STS_OFFSET); + + printk(BIOS_INFO, "ISH Status: 0x%02x, UFS0 Status: 0x%02x\n", ish_pg_sts, ufs0_pg_sts); + if ((ish_pg_sts & ISH_PG_STS) && (ufs0_pg_sts & UFS0_PG_STS)) + return true; + return false; +} + +static void recheck_ufs_state(void *unused) +{ + if (!is_devfn_enabled(PCH_DEVFN_UFS) && !is_ish_and_ufs_powergated()) { + printk(BIOS_ERR, "ISH and/or UFS not powergated.\n"); + if (!mainboard_expects_another_reset()) { + printk(BIOS_INFO, "Triggering warm reset to disable UFS\n"); + system_reset(); + } + } +} +BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_EXIT, recheck_ufs_state, NULL); diff --git a/src/mainboard/google/brox/variants/baseboard/brox/romstage.c b/src/mainboard/google/brox/variants/baseboard/brox/reset_check.c similarity index 100% rename from src/mainboard/google/brox/variants/baseboard/brox/romstage.c rename to src/mainboard/google/brox/variants/baseboard/brox/reset_check.c -- To view, visit https://review.coreboot.org/c/coreboot/+/86151?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I31f1cfc995a98bb345ac64ec3ae68a3bcc413f29 Gerrit-Change-Number: 86151 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com>

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[XS] Change in coreboot[main]: Revert "soc/intel/alderlake: Disable UFS controllers only on S5 resume"
by Karthik Ramasubramanian (Code Review) 24 Jan '25

24 Jan '25

Attention is currently required from: Dinesh Gehlot, Intel coreboot Reviewers, Jayvik Desai, Jérémy Compostella, Kapil Porwal, Karthik Ramasubramanian, Nick Vaccaro. Hello Dinesh Gehlot, Intel coreboot Reviewers, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/86111?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Code-Review+2 by Dinesh Gehlot, Code-Review-1 by Karthik Ramasubramanian, Verified+1 by build bot (Jenkins) Change subject: Revert "soc/intel/alderlake: Disable UFS controllers only on S5 resume" ...................................................................... Revert "soc/intel/alderlake: Disable UFS controllers only on S5 resume" This reverts commit 5e580c79dfd43387e6d375c94c6d95c520189111. On boards with non-UFS storage, currently UFS controller is disabled only when the system is coming out of S5 sleep state. On certain kind of resets during boot flow, this leaves some UFS resources turned on and causing the suspend failure. To fix this issue, disable UFS controller on every boot cycle. BUG=b:391449110 TEST=Build Brox BIOS image and boot to OS. Ensure that when the device switches from normal mode to developer mode and vice-versa, the device is able to suspend/resume successfully. Change-Id: I1d7089a90bc42a2b36c26b05b81c1a2f12861fdc Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com --- M src/soc/intel/alderlake/romstage/romstage.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/86111/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86111?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1d7089a90bc42a2b36c26b05b81c1a2f12861fdc Gerrit-Change-Number: 86111 Gerrit-PatchSet: 2 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Bob Moragues <moragues(a)google.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Wentao Qin <qinwentao(a)huaqin.corp-partner.google.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com>

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[XS] Change in coreboot[main]: mb/starlabs/{byte_adl,starlite_adl}: Add SSD detect timeout
by Matt DeVillier (Code Review) 24 Jan '25

24 Jan '25

Attention is currently required from: Sean Rhodes. Matt DeVillier has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/86150?usp=email ) Change subject: mb/starlabs/{byte_adl,starlite_adl}: Add SSD detect timeout ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86150?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibade3043489b82e5308231472dfe2c629b591661 Gerrit-Change-Number: 86150 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Comment-Date: Fri, 24 Jan 2025 21:20:28 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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