coreboot-gerrit January 2025

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[M] Change in coreboot[main]: drivers/intel/fsp2_0: Add option to control debug log level using CBFS
by Subrata Banik (Code Review) 24 Jan '25

24 Jan '25

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86001?usp=email ) Change subject: drivers/intel/fsp2_0: Add option to control debug log level using CBFS ...................................................................... drivers/intel/fsp2_0: Add option to control debug log level using CBFS This commit relies on newly added Kconfig option, USE_CBFS_FILE_OPTION_BACKEND, which allows controlling the FSP debug log level using CBFS options (RAW binary files). The default log-level is setup in coreboot while stitching the CBFS option binaries depending upon the coreboot log-level. Following files will be used to determine the log levels: - fsp_pcd_debug_level: For the overall FSP debug log level. - fsp_mrc_debug_level: For the MRC (Memory Reference Code) debug log level. In absense of these files, the FSP console log-level is determine by calling into fsp_map_console_log_level API. The values in these files should correspond to the FSP_LOG_LEVEL_* enum values. This change allows for more flexibility in controlling the FSP debug log level, especially in cases of debugging silicon firmware issues with a debug AP FW binary. This capability is particularly useful when debugging issues that require examining both silicon and MRC logs simultaneously. BUG=b:227151510 TEST=Able to control the FSP debug log based on CBFS options To inject the fsp_pcd_debug_level and fsp_mrc_debug_level CBFS files with the desired log level, run: ``` cbfstool image-fatcat.serial.bin add-int -i 5 -n option/fsp_pcd_debug_level cbfstool image-fatcat.serial.bin add-int -i 5 -n option/fsp_mrc_debug_level ``` With both fsp_pcd_debug_level and fsp_mrc_debug_level present in the RO CBFS, both the silicon firmware and MRC behave as debug binaries. To verify the presence of both log-level RAW CBFS binaries in the CBFS RO slot, run: ``` sudo cbfstool fatcat/image-rex0.serial.bin print | grep fsp_ ``` This should output: ``` option/fsp_mrc_debug_level 0x88e40 raw 8 none option/fsp_pcd_debug_level 0x2a7400 raw 8 none ``` Change-Id: I2c14d26021dd0048fa24024119df857e216f18bd Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86001 Reviewed-by: Jérémy Compostella <jeremy.compostella(a)intel.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> --- M src/drivers/intel/fsp2_0/debug.c M src/drivers/intel/fsp2_0/include/fsp/debug.h 2 files changed, 52 insertions(+), 0 deletions(-) Approvals: Jérémy Compostella: Looks good to me, approved build bot (Jenkins): Verified Kapil Porwal: Looks good to me, approved diff --git a/src/drivers/intel/fsp2_0/debug.c b/src/drivers/intel/fsp2_0/debug.c index 9dc964d..431618c 100644 --- a/src/drivers/intel/fsp2_0/debug.c +++ b/src/drivers/intel/fsp2_0/debug.c @@ -6,6 +6,7 @@ #include <cpu/x86/mtrr.h> #include <fsp/debug.h> #include <fsp/util.h> +#include <option.h> enum fsp_call_phase { BEFORE_FSP_CALL, @@ -178,3 +179,13 @@ display_mtrrs(); } + +enum fsp_log_level fsp_get_pcd_debug_log_level(void) +{ + return get_uint_option("fsp_pcd_debug_level", fsp_map_console_log_level()); +} + +enum fsp_log_level fsp_get_mrc_debug_log_level(void) +{ + return get_uint_option("fsp_mrc_debug_level", fsp_map_console_log_level()); +} diff --git a/src/drivers/intel/fsp2_0/include/fsp/debug.h b/src/drivers/intel/fsp2_0/include/fsp/debug.h index e7f9f25..c7c2990 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/debug.h +++ b/src/drivers/intel/fsp2_0/include/fsp/debug.h @@ -63,4 +63,45 @@ /* Callback to verify that current GPIO configuration matches the saved snapshot */ size_t gpio_verify_snapshot(void); +/* + * Retrieve fsp_pcd_debug_level file from option backend (e.g. CBFS) to identify the log-level + * used for outputting FSP debug messages. + * + * 1. Critical errors, need action etc., FSP_LOG_LEVEL_ERR aka value 1 + * 2. #1 including warnings, FSP_LOG_LEVEL_ERR_WARN aka value 2 + * 3. #2 including additional informational messages, FSP_LOG_LEVEL_ERR_WARN_INFO aka value 3 + * + * The default log-level is setup in coreboot while stitching the CBFS option binaries + * depending upon the coreboot log-level. One can override that using below example: + * + * Here is an example of adding fsp_pcd_debug_level option binary file into the RO-CBFS + * to specify the FSP log-level: + * - cbfstool <AP FW image> add-int -i <log-level> -n option/fsp_pcd_debug_level + * + * If OPTION_BACKEND_NONE then the then, use log levels will be determined by + * calling into fsp_map_console_log_level API. + */ +enum fsp_log_level fsp_get_pcd_debug_log_level(void); +/* + * Retrieve fsp_mrc_debug_level file from option backend (e.g. CBFS) to identify the log-level + * used for outputting FSP debug messages. + * + * 1. Critical errors, need action etc., FSP_LOG_LEVEL_ERR aka value 1 + * 2. #1 including warnings, FSP_LOG_LEVEL_ERR_WARN aka value 2 + * 3. #2 including additional informational messages, FSP_LOG_LEVEL_ERR_WARN_INFO aka value 3 + * 4. #3 including event logs, FSP_LOG_LEVEL_ERR_WARN_INFO_EVENT aka value 4 + * 5. Use FSP_LOG_LEVEL_VERBOSE aka 5 for all types of debug messages. + * + * The default log-level is setup in coreboot while stitching the CBFS option binaries + * depending upon the coreboot log-level. One can override that using below example: + * + * Here is an example of adding fsp_mrc_debug_level option binary file into the RO-CBFS + * to specify the FSP log-level: + * - cbfstool <AP FW image> add-int -i <log-level> -n option/fsp_mrc_debug_level + * + * If OPTION_BACKEND_NONE then the then, use log levels will be determined by + * calling into fsp_map_console_log_level API. + */ +enum fsp_log_level fsp_get_mrc_debug_log_level(void); + #endif /* _FSP2_0_DEBUG_H_ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/86001?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2c14d26021dd0048fa24024119df857e216f18bd Gerrit-Change-Number: 86001 Gerrit-PatchSet: 12 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

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[XS] Change in coreboot[main]: commonlib/dt: Fix incorrect cell properties
by Kapil Porwal (Code Review) 24 Jan '25

24 Jan '25

Kapil Porwal has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/86030?usp=email ) Change subject: commonlib/dt: Fix incorrect cell properties ...................................................................... Abandoned Not required anymore. -- To view, visit https://review.coreboot.org/c/coreboot/+/86030?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: abandon Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1d360a4cc0a02462a53866bf375e5d4c85177a05 Gerrit-Change-Number: 86030 Gerrit-PatchSet: 1 Gerrit-Owner: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: commonlib/dt: Fix incorrect cell properties
by Kapil Porwal (Code Review) 24 Jan '25

24 Jan '25

Attention is currently required from: Julius Werner, Subrata Banik. Kapil Porwal has posted comments on this change by Kapil Porwal. ( https://review.coreboot.org/c/coreboot/+/86030?usp=email ) Change subject: commonlib/dt: Fix incorrect cell properties ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > > If we exit from PASS#2 without returning cell properties of current parent (i.e. […] Thanks Julius for the explanation. I am abandoning this CL as this is not required anymore. -- To view, visit https://review.coreboot.org/c/coreboot/+/86030?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1d360a4cc0a02462a53866bf375e5d4c85177a05 Gerrit-Change-Number: 86030 Gerrit-PatchSet: 1 Gerrit-Owner: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Fri, 24 Jan 2025 07:20:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Kapil Porwal <kapilporwal(a)google.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org>

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[S] Change in coreboot[main]: mb/google/fatcat: Move FP from GSPI0A to GSPI0
by Subrata Banik (Code Review) 24 Jan '25

24 Jan '25

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86143?usp=email ) Change subject: mb/google/fatcat: Move FP from GSPI0A to GSPI0 ...................................................................... mb/google/fatcat: Move FP from GSPI0A to GSPI0 This moves the FP device from GSPI0A to GSPI0 to align with the hardware design. The FP device was initially placed on GSPI0A, which was incorrect. This commit rectifies the configuration by moving it to the correct GSPI0 interface. This change ensures that the CRFP device is correctly connected and functions as expected. BUG=b:377595986 TEST=Able to build and boot google/fatcat. Change-Id: I3996f1a054204689ad733c650b6f71f1482c0b22 Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/mainboard/google/fatcat/variants/fatcat/overridetree.cb 1 file changed, 20 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/86143/1 diff --git a/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb b/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb index 5414e15..cb4c21a 100644 --- a/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb +++ b/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb @@ -108,9 +108,9 @@ }" register "serial_io_gspi_mode" = "{ - [PchSerialIoIndexGSPI0] = PchSerialIoDisabled, + [PchSerialIoIndexGSPI0] = PchSerialIoPci, [PchSerialIoIndexGSPI1] = PchSerialIoDisabled, - [PchSerialIoIndexGSPI0A] = PchSerialIoPci, + [PchSerialIoIndexGSPI0A] = PchSerialIoDisabled, }" # Intel Common SoC Config @@ -395,24 +395,6 @@ end end - device ref gspi0a on - chip drivers/spi/acpi - register "name" = ""CRFP"" - register "hid" = "ACPI_DT_NAMESPACE_HID" - register "uid" = "1" - register "compat_string" = ""google,cros-ec-spi"" - register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_D01_IRQ)" - register "wake" = "GPE0_DW1_01" - register "has_power_resource" = "true" - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C15)" - register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E19)" - register "enable_delay_ms" = "3" - device spi 0 on - probe FP FP_PRESENT - end - end # FPMCU - end - device ref xhci on chip drivers/usb/acpi device ref xhci_root_hub on @@ -850,6 +832,24 @@ end end # I2C5 + device ref gspi0 on + chip drivers/spi/acpi + register "name" = ""CRFP"" + register "hid" = "ACPI_DT_NAMESPACE_HID" + register "uid" = "1" + register "compat_string" = ""google,cros-ec-spi"" + register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_D01_IRQ)" + register "wake" = "GPE0_DW1_01" + register "has_power_resource" = "true" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C15)" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E19)" + register "enable_delay_ms" = "3" + device spi 0 on + probe FP FP_PRESENT + end + end # FPMCU + end + device ref smbus on end device ref npk on end device ref hda on -- To view, visit https://review.coreboot.org/c/coreboot/+/86143?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3996f1a054204689ad733c650b6f71f1482c0b22 Gerrit-Change-Number: 86143 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com>

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[XS] Change in coreboot[main]: commonlib/dt: Fix incorrect cell properties
by Julius Werner (Code Review) 24 Jan '25

24 Jan '25

Attention is currently required from: Kapil Porwal, Subrata Banik. Julius Werner has posted comments on this change by Kapil Porwal. ( https://review.coreboot.org/c/coreboot/+/86030?usp=email ) Change subject: commonlib/dt: Fix incorrect cell properties ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > If we exit from PASS#2 without returning cell properties of current parent (i.e. "/abc") the cell properties would contain values from PASS#1 which is not correct. No, that is correct, that's the whole point of the original patch. See the FDT specification here: https://devicetree-specification.readthedocs.io/en/stable/devicetree-basics… > The #address-cells property defines the number of <u32> cells used to encode the address field in a child node’s reg property. The cells properties of a node define the rules for the reg properties of its _children_. That means when you use the normal pattern of ``` struct device_tree_node *node = dt_find_node(tree->root, "/cpus/cpu@0", &address_cells, &size_cells, 0); dt_read_reg_prop(node, address_cells, size_cells, regions, ARRAY_SIZE(regions)); ``` you want `address_cells` and `size_cells` to contain the value up to `/cpus`, _not_ up to `/cpus/cpu@0`. `fdt_find_node()` was already doing the same thing for the same reason. -- To view, visit https://review.coreboot.org/c/coreboot/+/86030?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1d360a4cc0a02462a53866bf375e5d4c85177a05 Gerrit-Change-Number: 86030 Gerrit-PatchSet: 1 Gerrit-Owner: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Fri, 24 Jan 2025 06:38:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Kapil Porwal <kapilporwal(a)google.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org>

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[M] Change in coreboot[main]: mb/asus/p8z77-v: Attempt to correctly route PCIe lanes
by Keith Hui (Code Review) 24 Jan '25

24 Jan '25

Attention is currently required from: Bill XIE. Keith Hui has posted comments on this change by Keith Hui. ( https://review.coreboot.org/c/coreboot/+/85413?usp=email ) Change subject: mb/asus/p8z77-v: Attempt to correctly route PCIe lanes ...................................................................... Patch Set 3: (1 comment) File src/mainboard/asus/p8x7x-series/variants/p8z77-v/early_init.c: https://review.coreboot.org/c/coreboot/+/85413/comment/de6780b5_cc6d222a?us… : PS2, Line 77: {7, 34, 20, -1} > Thanks Bill. Got it. Will take a look. I saw your dumps and honestly I can't see I missed anything. My card detect logic at PCIEX1_2 appears to be correct. Let's go back to coreboot with this patch. We need to see what differs between vendor dump and coreboot dump, all with your Marvell SATA card in PCIEX1_2. I'd also like to get your console log to see what ramstage is seeing when scanning the PCIe bus. Failing these, we'll need to bring in more eyes. -- To view, visit https://review.coreboot.org/c/coreboot/+/85413?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If41197a1f817a48c209d25fc1ae461ec97ccf16c Gerrit-Change-Number: 85413 Gerrit-PatchSet: 3 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Comment-Date: Fri, 24 Jan 2025 06:38:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Bill XIE <persmule(a)hardenedlinux.org> Comment-In-Reply-To: Keith Hui <buurin(a)gmail.com>

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[XS] Change in coreboot[main]: drivers/intel/dptf: Suppress unnecessary static function
by Elyes Haouas (Code Review) 24 Jan '25

24 Jan '25

Elyes Haouas has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86130?usp=email ) Change subject: drivers/intel/dptf: Suppress unnecessary static function ...................................................................... drivers/intel/dptf: Suppress unnecessary static function This commit eliminates the superfluous get_dptf_platform_info() static function. Change-Id: I0b9d150bab8486cb7e437d5e2b3caa880e14f886 Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/86130 Reviewed-by: Jamie Ryu <jamie.m.ryu(a)intel.com> Reviewed-by: Elyes Haouas <ehaouas(a)noos.fr> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Bora Guvendik <bora.guvendik(a)intel.com> --- M src/drivers/intel/dptf/dptf.c 1 file changed, 1 insertion(+), 6 deletions(-) Approvals: Elyes Haouas: Looks good to me, approved build bot (Jenkins): Verified Bora Guvendik: Looks good to me, approved Jamie Ryu: Looks good to me, approved diff --git a/src/drivers/intel/dptf/dptf.c b/src/drivers/intel/dptf/dptf.c index b6f5005..0b60dcf 100644 --- a/src/drivers/intel/dptf/dptf.c +++ b/src/drivers/intel/dptf/dptf.c @@ -496,15 +496,10 @@ #endif }; -static const struct dptf_platform_info *get_dptf_platform_info(void) -{ - return &generic_dptf_platform_info; -} - /* Add minimal definitions of DPTF devices into the SSDT */ static void write_device_definitions(const struct device *dev) { - const struct dptf_platform_info *platform_info = get_dptf_platform_info(); + const struct dptf_platform_info *platform_info = &generic_dptf_platform_info; const struct drivers_intel_dptf_config *config; struct device *parent; enum dptf_participant p; -- To view, visit https://review.coreboot.org/c/coreboot/+/86130?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0b9d150bab8486cb7e437d5e2b3caa880e14f886 Gerrit-Change-Number: 86130 Gerrit-PatchSet: 2 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Deepika Punyamurtula <deepika.punyamurtula(a)intel.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: drivers/intel/dptf: Suppress unnecessary static function
by Elyes Haouas (Code Review) 24 Jan '25

24 Jan '25

Attention is currently required from: Deepika Punyamurtula, Intel coreboot Reviewers, Jérémy Compostella. Elyes Haouas has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/86130?usp=email ) Change subject: drivers/intel/dptf: Suppress unnecessary static function ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86130?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0b9d150bab8486cb7e437d5e2b3caa880e14f886 Gerrit-Change-Number: 86130 Gerrit-PatchSet: 1 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Deepika Punyamurtula <deepika.punyamurtula(a)intel.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Deepika Punyamurtula <deepika.punyamurtula(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Comment-Date: Fri, 24 Jan 2025 06:29:48 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: libpayload: Unify selfboot() implementations
by Subrata Banik (Code Review) 24 Jan '25

24 Jan '25

Attention is currently required from: Julius Werner, Stephen Boyd, Yu-Ping Wu. Subrata Banik has posted comments on this change by Julius Werner. ( https://review.coreboot.org/c/coreboot/+/86142?usp=email ) Change subject: libpayload: Unify selfboot() implementations ...................................................................... Patch Set 1: (1 comment) File payloads/libpayload/libc/selfboot.c: https://review.coreboot.org/c/coreboot/+/86142/comment/24d898fa_5ca940b1?us… : PS1, Line 35: __attribute__((__regparm__(0))) > I think technically this doesn't really do anything, because our default calling convention is already `regparm(0)` to begin with. But coreboot also still does it when loading the payload, so I guess it's more consistent to do it here too. +2 -- To view, visit https://review.coreboot.org/c/coreboot/+/86142?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If14040e38d968b5eea31cd6cd25efb1845a7b081 Gerrit-Change-Number: 86142 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Stephen Boyd <swboyd(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Stephen Boyd <swboyd(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Fri, 24 Jan 2025 06:14:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org>

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[XS] Change in coreboot[main]: commonlib/dt: Fix incorrect cell properties
by Subrata Banik (Code Review) 24 Jan '25

24 Jan '25

Attention is currently required from: Julius Werner, Kapil Porwal. Subrata Banik has posted comments on this change by Kapil Porwal. ( https://review.coreboot.org/c/coreboot/+/86030?usp=email ) Change subject: commonlib/dt: Fix incorrect cell properties ...................................................................... Patch Set 1: -Code-Review (1 comment) Patchset: PS1: > I see it now. These properties are actually meant for the child nodes. Hence we need to fix the test case instead. that make sense -- To view, visit https://review.coreboot.org/c/coreboot/+/86030?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1d360a4cc0a02462a53866bf375e5d4c85177a05 Gerrit-Change-Number: 86030 Gerrit-PatchSet: 1 Gerrit-Owner: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Fri, 24 Jan 2025 05:56:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Kapil Porwal <kapilporwal(a)google.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org>

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coreboot-gerrit January 2025