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[L] Change in coreboot[main]: soc/mediatek/mt8196: Add GPUEB support
by Alvin Liu (Code Review) 03 Jan '25

03 Jan '25

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[L] Change in coreboot[main]: soc/mediatek/mt8196: Add GPUEB support
by Jarried Lin (Code Review) 03 Jan '25

03 Jan '25

Attention is currently required from: Andy Hsu, Hung-Te Lin, Jarried Lin, Yidi Lin, Yu-Ping Wu. Hello Andy Hsu, Hung-Te Lin, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85654?usp=email to look at the new patch set (#6). Change subject: soc/mediatek/mt8196: Add GPUEB support ...................................................................... soc/mediatek/mt8196: Add GPUEB support GPUEB is a micro-processor used for GPU power management. It is also responsible for controlling GPU DVFS and GPU thermal throttling. This gpueb load flow adds 47ms to the boot time. coreboot log: CBFS: Found 'gpueb_fw.img' @0x84740 size 0x29736 in mcache @0xfffdd374 Loaded (and reset) gpueb_fw.img in 47 msecs. TEST=Boot ok BUG=b:317009620 Signed-off-by: Andy.Hsu <andy.hsu(a)mediatek.corp-partner.google.com> Change-Id: I0f10dfc753f73df97ea08a4c23e97de416832be2 --- M src/soc/mediatek/common/include/soc/symbols.h M src/soc/mediatek/mt8196/Kconfig M src/soc/mediatek/mt8196/Makefile.mk A src/soc/mediatek/mt8196/gpueb.c M src/soc/mediatek/mt8196/include/soc/addressmap.h A src/soc/mediatek/mt8196/include/soc/gpueb.h A src/soc/mediatek/mt8196/include/soc/gpueb_priv.h M src/soc/mediatek/mt8196/include/soc/memlayout.ld M src/soc/mediatek/mt8196/soc.c 9 files changed, 609 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/85654/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/85654?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0f10dfc753f73df97ea08a4c23e97de416832be2 Gerrit-Change-Number: 85654 Gerrit-PatchSet: 6 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Andy Hsu <andy.hsu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alvin Liu <alvin.liu(a)mediatek.corp-partner.google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Andy Hsu <andy.hsu(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com>

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[L] Change in coreboot[main]: soc/mediatek/mt8196: Add GPUEB support
by Alvin Liu (Code Review) 03 Jan '25

03 Jan '25

Attention is currently required from: Andy Hsu, Hung-Te Lin, Jarried Lin, Yidi Lin, Yu-Ping Wu. Alvin Liu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85654?usp=email ) Change subject: soc/mediatek/mt8196: Add GPUEB support ...................................................................... Patch Set 5: (16 comments) File src/soc/mediatek/mt8196/Makefile.mk: https://review.coreboot.org/c/coreboot/+/85654/comment/4bebfb52_a39e8136?us… : PS4, Line 81: $(CONFIG_GPUEB_FIRMWARE) > sort Done File src/soc/mediatek/mt8196/gpueb.c: https://review.coreboot.org/c/coreboot/+/85654/comment/43459b80_0a1cbfde?us… : PS4, Line 192: Fail > failed Done https://review.coreboot.org/c/coreboot/+/85654/comment/9c1ec38a_be1aac03?us… : PS4, Line 196: gpueb_ > remove `gpueb_` prefix Done https://review.coreboot.org/c/coreboot/+/85654/comment/1dc52eea_86be8e54?us… : PS4, Line 203: > die if `buf_size <= sizeof(*hdr)` Done https://review.coreboot.org/c/coreboot/+/85654/comment/59795c20_b06e19f8?us… : PS4, Line 204: hdr->magic == GPUEB_PT_MAGIC > Move this condition after the size check in line #205, because we should not access `hdr->magic` if […] Done https://review.coreboot.org/c/coreboot/+/85654/comment/a1f07a1a_b66763b9?us… : PS4, Line 205: gpueb_pt_hdr > `*hdr` Done https://review.coreboot.org/c/coreboot/+/85654/comment/05eb51b2_76014b47?us… : PS4, Line 247: auto_dma_fw[pt_id].fw_size <= GPUEB_SRAM_SIZE > `auto_dma_fw[pt_id].fw_addr + auto_dma_fw[pt_id]. […] Done https://review.coreboot.org/c/coreboot/+/85654/comment/c94b78db_9c66023d?us… : PS4, Line 279: __func__, mfg0_pwr_con); > merged to previous line Done https://review.coreboot.org/c/coreboot/+/85654/comment/82a10483_265872cb?us… : PS4, Line 366: gpueb_platform_load > gpueb_load Done https://review.coreboot.org/c/coreboot/+/85654/comment/7d0d80b0_c70b0f9b?us… : PS4, Line 373: Load FW failed > Failed to load FW Done https://review.coreboot.org/c/coreboot/+/85654/comment/bcbe28ab_c2c4f98a?us… : PS4, Line 376: Failed > Failed to wait for boot up Done File src/soc/mediatek/mt8196/include/soc/addressmap.h: https://review.coreboot.org/c/coreboot/+/85654/comment/aa31e7d1_8ad3b85b?us… : PS4, Line 198: GPU_EB > Either `GPUEB` or `GPU_EB`. Please be consistent with the name above. Done File src/soc/mediatek/mt8196/include/soc/gpueb_priv.h: https://review.coreboot.org/c/coreboot/+/85654/comment/39e9ab7c_9f1389b8?us… : PS4, Line 64: ( > remove Done File src/soc/mediatek/mt8196/include/soc/memlayout.ld: https://review.coreboot.org/c/coreboot/+/85654/comment/0671a571_ac891cb7?us… : PS4, Line 76: Memory > memory Done https://review.coreboot.org/c/coreboot/+/85654/comment/e2407187_6d1ca417?us… : PS4, Line 76: uP > `microprocessor` (or is this supposed to mean `MCU`?) Done https://review.coreboot.org/c/coreboot/+/85654/comment/252528dd_7ef2c4bc?us… : PS4, Line 76: /* Reserved Memory for the shared buffer between AP and uP */ > Could you explain more about the difference between these 2 regions? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/85654?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0f10dfc753f73df97ea08a4c23e97de416832be2 Gerrit-Change-Number: 85654 Gerrit-PatchSet: 5 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Andy Hsu <andy.hsu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alvin Liu <alvin.liu(a)mediatek.corp-partner.google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Andy Hsu <andy.hsu(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Fri, 03 Jan 2025 06:21:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com>

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[L] Change in coreboot[main]: soc/mediatek/mt8196: Add GPUEB support
by Jarried Lin (Code Review) 03 Jan '25

03 Jan '25

Attention is currently required from: Alvin Liu, Andy Hsu, Hung-Te Lin, Jarried Lin, Yidi Lin. Hello Andy Hsu, Hung-Te Lin, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85654?usp=email to look at the new patch set (#5). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/mediatek/mt8196: Add GPUEB support ...................................................................... soc/mediatek/mt8196: Add GPUEB support GPUEB is a micro-processor used for GPU power management. It is also responsible for controlling GPU DVFS and GPU thermal throttling. This gpueb load flow adds 47ms to the boot time. coreboot log: CBFS: Found 'gpueb_fw.img' @0x84740 size 0x29736 in mcache @0xfffdd374 Loaded (and reset) gpueb_fw.img in 47 msecs. TEST=Boot ok BUG=b:317009620 Signed-off-by: Andy.Hsu <andy.hsu(a)mediatek.corp-partner.google.com> Change-Id: I0f10dfc753f73df97ea08a4c23e97de416832be2 --- M src/soc/mediatek/common/include/soc/symbols.h M src/soc/mediatek/mt8196/Kconfig M src/soc/mediatek/mt8196/Makefile.mk A src/soc/mediatek/mt8196/gpueb.c M src/soc/mediatek/mt8196/include/soc/addressmap.h A src/soc/mediatek/mt8196/include/soc/gpueb.h A src/soc/mediatek/mt8196/include/soc/gpueb_priv.h M src/soc/mediatek/mt8196/include/soc/memlayout.ld M src/soc/mediatek/mt8196/soc.c 9 files changed, 615 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/85654/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/85654?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0f10dfc753f73df97ea08a4c23e97de416832be2 Gerrit-Change-Number: 85654 Gerrit-PatchSet: 5 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Andy Hsu <andy.hsu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alvin Liu <alvin.liu(a)mediatek.corp-partner.google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Alvin Liu <alvin.liu(a)mediatek.corp-partner.google.com> Gerrit-Attention: Andy Hsu <andy.hsu(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com>

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[L] Change in coreboot[main]: mb/asus/p8x7x-series: Add Z77-A as a variant
by Keith Hui (Code Review) 03 Jan '25

03 Jan '25

Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85836?usp=email ) Change subject: mb/asus/p8x7x-series: Add Z77-A as a variant ...................................................................... mb/asus/p8x7x-series: Add Z77-A as a variant Constructed from a mix of similar boards, boardview and vendor firmware analysis. Not hardware tested. It has a RTL8111F LAN chip with no EEPROM for vital product data like LED configurations or MAC addresses. User will need to set their MAC address during 'make menuconfig'. Change-Id: Id1a81b321c236bb1fd2763d69531958ef6f4b4e6 Signed-off-by: Keith Hui <buurin(a)gmail.com> --- M src/mainboard/asus/p8x7x-series/Kconfig M src/mainboard/asus/p8x7x-series/Kconfig.name A src/mainboard/asus/p8x7x-series/variants/z77-a/board_info.txt A src/mainboard/asus/p8x7x-series/variants/z77-a/cmos.default A src/mainboard/asus/p8x7x-series/variants/z77-a/cmos.layout A src/mainboard/asus/p8x7x-series/variants/z77-a/data.vbt A src/mainboard/asus/p8x7x-series/variants/z77-a/early_init.c A src/mainboard/asus/p8x7x-series/variants/z77-a/gma-mainboard.ads A src/mainboard/asus/p8x7x-series/variants/z77-a/gpio.c A src/mainboard/asus/p8x7x-series/variants/z77-a/hda/hda_verb.c A src/mainboard/asus/p8x7x-series/variants/z77-a/hda_verb.c A src/mainboard/asus/p8x7x-series/variants/z77-a/overridetree.cb 12 files changed, 553 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/85836/1 diff --git a/src/mainboard/asus/p8x7x-series/Kconfig b/src/mainboard/asus/p8x7x-series/Kconfig index da3d10b..0ea9907 100644 --- a/src/mainboard/asus/p8x7x-series/Kconfig +++ b/src/mainboard/asus/p8x7x-series/Kconfig @@ -58,6 +58,14 @@ select SUPERIO_NUVOTON_NCT6779D select SUPERIO_NUVOTON_COMMON_COM_A +config BOARD_ASUS_Z77_A + select BOARD_ASUS_P8X7X_SERIES + select BOARD_ROMSIZE_KB_8192 + select RT8168_SET_LED_MODE + select SUPERIO_NUVOTON_NCT5535D + select USE_NATIVE_RAMINIT + select POWER_LED_USES_GPIO8 + if BOARD_ASUS_P8X7X_SERIES config POWER_LED_USES_GPIO8 @@ -75,6 +83,7 @@ default "p8z77-v_lx2" if BOARD_ASUS_P8Z77_V_LX2 default "p8z77-v" if BOARD_ASUS_P8Z77_V default "p8z77-m" if BOARD_ASUS_P8Z77_M + default "z77-a" if BOARD_ASUS_Z77_A config MAINBOARD_PART_NUMBER default "P8C WS" if BOARD_ASUS_P8C_WS @@ -83,6 +92,7 @@ default "P8Z77-V LX2" if BOARD_ASUS_P8Z77_V_LX2 default "P8Z77-V" if BOARD_ASUS_P8Z77_V default "P8Z77-M" if BOARD_ASUS_P8Z77_M + default "Z77-A" if BOARD_ASUS_Z77_A config OVERRIDE_DEVICETREE default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" diff --git a/src/mainboard/asus/p8x7x-series/Kconfig.name b/src/mainboard/asus/p8x7x-series/Kconfig.name index a5598ca..9bb4ce0 100644 --- a/src/mainboard/asus/p8x7x-series/Kconfig.name +++ b/src/mainboard/asus/p8x7x-series/Kconfig.name @@ -17,3 +17,6 @@ config BOARD_ASUS_P8Z77_M bool "P8Z77-M" + +config BOARD_ASUS_Z77_A + bool "Z77-A" diff --git a/src/mainboard/asus/p8x7x-series/variants/z77-a/board_info.txt b/src/mainboard/asus/p8x7x-series/variants/z77-a/board_info.txt new file mode 100644 index 0000000..b1293a5 --- /dev/null +++ b/src/mainboard/asus/p8x7x-series/variants/z77-a/board_info.txt @@ -0,0 +1,7 @@ +Category: desktop +Board URL: https://www.asus.com/supportonly/Z77-A/HelpDesk_Knowledge/ +ROM package: DIP-8 +ROM protocol: SPI +ROM socketed: y +Flashrom support: y +Release year: 2012 diff --git a/src/mainboard/asus/p8x7x-series/variants/z77-a/cmos.default b/src/mainboard/asus/p8x7x-series/variants/z77-a/cmos.default new file mode 100644 index 0000000..a69cf0f --- /dev/null +++ b/src/mainboard/asus/p8x7x-series/variants/z77-a/cmos.default @@ -0,0 +1,8 @@ +## SPDX-License-Identifier: GPL-2.0-only + +boot_option=Fallback +debug_level=Debug +gfx_uma_size=224M +nmi=Disable +sata_mode=AHCI +audio_panel_type=HDA diff --git a/src/mainboard/asus/p8x7x-series/variants/z77-a/cmos.layout b/src/mainboard/asus/p8x7x-series/variants/z77-a/cmos.layout new file mode 100644 index 0000000..a289393 --- /dev/null +++ b/src/mainboard/asus/p8x7x-series/variants/z77-a/cmos.layout @@ -0,0 +1,117 @@ +## SPDX-License-Identifier: GPL-2.0-only + +# ----------------------------------------------------------------- +entries + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 3 boot_option +388 4 h 0 reboot_counter + +# ----------------------------------------------------------------- +# coreboot config options: console +395 4 e 4 debug_level + +# ----------------------------------------------------------------- +# coreboot config options: southbridge + +# Non Maskable Interrupt(NMI) support, which is an interrupt that may +# occur on a RAM or unrecoverable error. +408 1 e 1 nmi + +409 2 e 5 power_on_after_fail +411 2 e 6 sata_mode + +# ----------------------------------------------------------------- +# coreboot config options: northbridge + +# gfx_uma_size +# Quantity of shared video memory the IGP can use +# +416 5 e 7 gfx_uma_size + +# ----------------------------------------------------------------- +# coreboot config options: usb3 + +# audio_panel_type +# HD Audio or AC'97 +# +425 1 e 9 audio_panel_type + +# ----------------------------------------------------------------- +# Sandy/Ivy Bridge MRC Scrambler Seed values +# note: MUST NOT be covered by checksum! +464 32 r 0 mrc_scrambler_seed +496 32 r 0 mrc_scrambler_seed_s3 +528 16 r 0 mrc_scrambler_seed_chk + +# ----------------------------------------------------------------- +# coreboot config options: check sums +544 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations +#ID value text + +# Generic on/off enum +1 0 Disable +1 1 Enable + +# boot_option +3 0 Fallback +3 1 Normal + +# debug_level +4 0 Emergency +4 1 Alert +4 2 Critical +4 3 Error +4 4 Warning +4 5 Notice +4 6 Info +4 7 Debug +4 8 Spew + +# power_on_after_fail +5 0 Disable +5 1 Enable +5 2 Keep + +# sata_mode +6 0 AHCI +6 1 Compatible +6 2 Legacy + +# gfx_uma_size (Intel IGP Video RAM size) +7 0 32M +7 1 64M +7 2 96M +7 3 128M +7 4 160M +7 5 192M +7 6 224M +7 7 256M +7 8 288M +7 9 320M +7 10 352M +7 11 384M +7 12 416M +7 13 448M +7 14 480M +7 15 512M +7 16 1024M + +# audio_panel_type +9 0 HDA +9 1 AC97 + +# ----------------------------------------------------------------- +# <startBit[must be byte-aligned]> <endBit[must be byte aligned]> +# <bit where to start storing checksum[must be 16bits-aligned]> +checksums + +checksum 392 431 544 diff --git a/src/mainboard/asus/p8x7x-series/variants/z77-a/data.vbt b/src/mainboard/asus/p8x7x-series/variants/z77-a/data.vbt new file mode 100644 index 0000000..d27f877cb --- /dev/null +++ b/src/mainboard/asus/p8x7x-series/variants/z77-a/data.vbt Binary files differ diff --git a/src/mainboard/asus/p8x7x-series/variants/z77-a/early_init.c b/src/mainboard/asus/p8x7x-series/variants/z77-a/early_init.c new file mode 100644 index 0000000..babbcc6 --- /dev/null +++ b/src/mainboard/asus/p8x7x-series/variants/z77-a/early_init.c @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <bootblock_common.h> +#include <device/pnp_ops.h> + +#include <superio/nuvoton/common/nuvoton.h> +#include <superio/nuvoton/nct5535d/nct5535d.h> + +#define SERIAL_DEV PNP_DEV(0x2e, NCT5535D_SP1) + +void bootblock_mainboard_early_init(void) +{ + nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + /* + * TODO: Put PCIe root port 6 into subtractive decode and have it accept I/O + * cycles. This should allow a POST card in the PCI slot, connected via an ASM1083 + * bridge to this port, to receive POST codes. + */ +} diff --git a/src/mainboard/asus/p8x7x-series/variants/z77-a/gma-mainboard.ads b/src/mainboard/asus/p8x7x-series/variants/z77-a/gma-mainboard.ads new file mode 100644 index 0000000..b046a43 --- /dev/null +++ b/src/mainboard/asus/p8x7x-series/variants/z77-a/gma-mainboard.ads @@ -0,0 +1,17 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (HDMI2, -- DVI-D port + HDMI3, -- HDMI port + Analog, -- VGA port + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/asus/p8x7x-series/variants/z77-a/gpio.c b/src/mainboard/asus/p8x7x-series/variants/z77-a/gpio.c new file mode 100644 index 0000000..a125300 --- /dev/null +++ b/src/mainboard/asus/p8x7x-series/variants/z77-a/gpio.c @@ -0,0 +1,178 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_NATIVE, + .gpio3 = GPIO_MODE_NATIVE, + .gpio4 = GPIO_MODE_NATIVE, + .gpio5 = GPIO_MODE_NATIVE, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_NATIVE, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_NATIVE, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_NATIVE, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_OUTPUT, /* Power LED */ + .gpio12 = GPIO_DIR_INPUT, + .gpio13 = GPIO_DIR_INPUT, /* PME# */ + .gpio15 = GPIO_DIR_INPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_OUTPUT, /* ME_UNLOCK */ + .gpio28 = GPIO_DIR_OUTPUT, /* IVR-related */ + .gpio29 = GPIO_DIR_INPUT, + .gpio31 = GPIO_DIR_OUTPUT, /* BCS1 to BIOS flashback chip */ +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio8 = GPIO_LEVEL_HIGH, + .gpio27 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, + .gpio31 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = {}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = {}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, /* Test pad */ + .gpio33 = GPIO_MODE_GPIO, /* Test pad */ + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_NATIVE, + .gpio36 = GPIO_MODE_NATIVE, + .gpio37 = GPIO_MODE_NATIVE, + .gpio38 = GPIO_MODE_NATIVE, + .gpio39 = GPIO_MODE_NATIVE, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_GPIO, + .gpio46 = GPIO_MODE_GPIO, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_NATIVE, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_NATIVE, + .gpio51 = GPIO_MODE_NATIVE, + .gpio52 = GPIO_MODE_NATIVE, + .gpio53 = GPIO_MODE_NATIVE, + .gpio54 = GPIO_MODE_NATIVE, + .gpio55 = GPIO_MODE_NATIVE, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, /* BCS0 to BIOS flashback chip */ + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio45 = GPIO_DIR_INPUT, + .gpio46 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, + .gpio33 = GPIO_LEVEL_HIGH, + .gpio57 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = {}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, /* RTL8111F ISOLATE# */ + .gpio69 = GPIO_MODE_GPIO, /* AI1314 EEPROM write protect */ + .gpio70 = GPIO_MODE_GPIO, /* O3_SMB_SWITCH */ + .gpio71 = GPIO_MODE_NATIVE, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_OUTPUT, + .gpio69 = GPIO_DIR_OUTPUT, + .gpio70 = GPIO_DIR_OUTPUT, + .gpio72 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { + .gpio68 = GPIO_LEVEL_HIGH, + .gpio69 = GPIO_LEVEL_LOW, + .gpio70 = GPIO_LEVEL_LOW, /* High connects AI1314 and its EEPROM to PCH SMBus */ +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = {}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/asus/p8x7x-series/variants/z77-a/hda/hda_verb.c b/src/mainboard/asus/p8x7x-series/variants/z77-a/hda/hda_verb.c new file mode 100644 index 0000000..f9eccf6 --- /dev/null +++ b/src/mainboard/asus/p8x7x-series/variants/z77-a/hda/hda_verb.c @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10ec0887, /* Codec Vendor / Device ID: Realtek */ + 0x104384a8, /* Subsystem ID */ + 15, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x104384a8), + AZALIA_PIN_CFG(0, 0x11, 0x90430130), + AZALIA_PIN_CFG(0, 0x12, 0x411111f0), + AZALIA_PIN_CFG(0, 0x14, 0x01014410), + AZALIA_PIN_CFG(0, 0x15, 0x411111f0), + AZALIA_PIN_CFG(0, 0x16, 0x411111f0), + AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, 0x01a19c50), + AZALIA_PIN_CFG(0, 0x19, 0x02a19c60), + AZALIA_PIN_CFG(0, 0x1a, 0x0181345f), + AZALIA_PIN_CFG(0, 0x1b, 0x02214c20), + AZALIA_PIN_CFG(0, 0x1c, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, 0x4016c629), + AZALIA_PIN_CFG(0, 0x1e, 0x01446140), + AZALIA_PIN_CFG(0, 0x1f, 0x411111f0), + + 0x80862806, /* Codec Vendor / Device ID: Intel */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(3, 0x80860101), + AZALIA_PIN_CFG(3, 0x05, 0x58560010), + AZALIA_PIN_CFG(3, 0x06, 0x58560020), + AZALIA_PIN_CFG(3, 0x07, 0x18560030), + +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/asus/p8x7x-series/variants/z77-a/hda_verb.c b/src/mainboard/asus/p8x7x-series/variants/z77-a/hda_verb.c new file mode 100644 index 0000000..7db7c51 --- /dev/null +++ b/src/mainboard/asus/p8x7x-series/variants/z77-a/hda_verb.c @@ -0,0 +1,81 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <device/azalia_device.h> +#include <option.h> + +/* Shorthands */ +#define AZALIA_PIN_REAR(dev, color, misc, association, sequence) \ +AZALIA_PIN_DESC(AZALIA_JACK, AZALIA_REAR, dev, AZALIA_STEREO_MONO_1_8, \ + color, misc, association, sequence) +#define AZALIA_PIN_FRONT(dev, color, misc, association, sequence) \ +AZALIA_PIN_DESC(AZALIA_JACK, AZALIA_FRONT, dev, AZALIA_STEREO_MONO_1_8, \ + color, misc, association, sequence) + +const u32 cim_verb_data[] = { + 0x10ec0887, /* Codec Vendor / Device ID: Realtek ALC887VD */ + 0x104384a8, /* Subsystem ID */ + 15, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x104384a8), + AZALIA_PIN_CFG(0, 0x11, AZALIA_PIN_DESC( + AZALIA_INTEGRATED, + AZALIA_ATAPI, + AZALIA_SPDIF_OUT, + AZALIA_ATAPI_INTERNAL, + AZALIA_COLOR_UNKNOWN, + AZALIA_NO_JACK_PRESENCE_DETECT, + 3, 0)), /* SPDIF out 2 */ + AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x14, AZALIA_PIN_REAR(AZALIA_LINE_OUT, AZALIA_GREEN, 4, 1, 0)), + AZALIA_PIN_CFG(0, 0x15, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x16, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_REAR(AZALIA_MIC_IN, AZALIA_PINK, 0xc, 5, 0)), + AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_FRONT(AZALIA_MIC_IN, AZALIA_PINK, 0xc, 6, 0)), + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_REAR(AZALIA_LINE_IN, AZALIA_BLUE, 4, 5, 15)), + AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_FRONT(AZALIA_HP_OUT, AZALIA_GREEN, 0xc, 2, 0)), + AZALIA_PIN_CFG(0, 0x1c, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1d, 0x4016c629), + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), /* SPDIF out 1 */ + AZALIA_PIN_CFG(0, 0x1f, AZALIA_PIN_CFG_NC(0)), /* SPDIF in */ + + 0x80862806, /* Codec Vendor / Device ID: Intel */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(3, 0x80860101), + AZALIA_PIN_CFG(3, 0x05, 0x58560010), + AZALIA_PIN_CFG(3, 0x06, 0x58560020), + AZALIA_PIN_CFG(3, 0x07, 0x18560030), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; + +void mainboard_azalia_program_runtime_verbs(u8 *base, u32 viddid) +{ + unsigned int ac97 = get_uint_option("audio_panel_type", 0) & 0x1; + + /* + * The verbs above are for a HD Audio front panel. + * With vendor firmware, if audio front panel type is set as AC97, line out 2 + * (0x1b) and mic 2 (0x19) pins of ALC887 are configured differently. + * + * The differences are all in the "Misc" fields of configuration defaults (in byte 2) + * as shown below. ALC887 datasheet did not offer details on what those bits + * (listed as reserved in HDA spec) are, so we'll have to take their word for it. + * + * Pin | 0x19 | 0x1b + * -----+------+----- + * HDA | 1100 | 1100 + * AC97 | 1001 | 0001 + */ + + const u32 verbs[] = { + AZALIA_VERB_12B(0, 0x19, 0x71d, 0x99), + AZALIA_VERB_12B(0, 0x1b, 0x71d, 0x41) + }; + + if ((viddid == 0x10ec0887) && ac97) { + azalia_program_verb_table(base, verbs, ARRAY_SIZE(verbs)); + } +} diff --git a/src/mainboard/asus/p8x7x-series/variants/z77-a/overridetree.cb b/src/mainboard/asus/p8x7x-series/variants/z77-a/overridetree.cb new file mode 100644 index 0000000..d359005 --- /dev/null +++ b/src/mainboard/asus/p8x7x-series/variants/z77-a/overridetree.cb @@ -0,0 +1,76 @@ +## SPDX-License-Identifier: GPL-2.0-only + +chip northbridge/intel/sandybridge + device domain 0 on + subsystemid 0x1043 0x84ca inherit + chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH + register "gen1_dec" = "0x000c0291" + register "usb_port_config" = "{ + {1, 0x357, 0}, /* Port 0: USB3 front internal header, top */ + {1, 0x357, 0}, /* Port 1: USB3 front internal header, bottom */ + {1, 0x357, 1}, /* Port 2: USB3 rear, top */ + {1, 0x557, 1}, /* Port 3: USB3 rear, bottom */ + {1, 0x446, 2}, /* Port 4: USB2 rear LAN, top */ + {1, 0x446, 2}, /* Port 5: USB2 rear LAN, bottom */ + {1, 7, 3}, /* Port 6: USB2 rear, top */ + {1, 7, 3}, /* Port 7: USB2 rear, bottom */ + {1, 6, 4}, /* Port 8: USB2 internal header USB56, top */ + {1, 0xf56, 4}, /* Port 9: USB2 internal header USB56, bottom */ + {1, 6, 5}, /* Port 10: USB2 internal header USB78, top */ + {1, 6, 5}, /* Port 11: USB2 internal header USB78, bottom */ + {0, 6, -1}, /* Ports 12/13: Not connected */ + {0, 0xa56, -1} + }" + + device ref pcie_rp1 on end # PCIEX16_2 (x4) + device ref pcie_rp5 on # RTL8111F GbE + subsystemid 0x1849 0x1e1a + chip drivers/net + register "customized_leds" = "0x482" + device pci 00.0 on end + end + end + device ref pcie_rp6 on end # ASM1083 PCI bridge + device ref pcie_rp7 on end # PCIEX1_1 + device ref pcie_rp8 on end # PCIEX1_2 + device ref lpc on + chip superio/nuvoton/nct5535d + device pnp 2e.2 on # UART A + io 0x60 = 0x3f8 # COM1 address + irq 0x70 = 4 + end + device pnp 2e.5 on # PS2 KBC + io 0x60 = 0x0060 # KBC1 base + io 0x62 = 0x0064 # KBC2 base + irq 0x70 = 1 # Keyboard IRQ + irq 0x72 = 12 # Mouse IRQ + drq 0xf0 = 0x82 # KBC 12Mhz/A20 speed/sw KBRST + drq 0x2a = 0x48 # UART A, PS/2 mouse, PS/2 keyboard + end + device pnp 2e.6 off end # CIR + device pnp 2e.8 off end # WDT1 + device pnp 2e.a on # ACPI + drq 0xe4 = 0x10 # Enable 3VSBSW#, needed for S3 suspend + drq 0xe7 = 0x11 # HWM reset by LRESET#, 0.5s S3 delay for compatibility + drq 0xf2 = 0x5d # Enable RSTOUT[0-2]# and PME + end + device pnp 2e.b on # HWM + io 0x60 = 0x290 # HWM address + io 0x62 = 0 # SB-TSI address (not used) + irq 0x70 = 0 + drq 0xe4 = 0xf9 # GP50, GP52, PWROK# + drq 0xf0 = 0x3e # Enable all fan input debouncers + end + device pnp 2e.e off end # CIR wake-up + device pnp 2e.f on # GPIO PP/OD select + drq 0xe4 = 0xfc # GP50,GP51 PP + drq 0xe6 = 0x7f # GP7x OD + end + device pnp 2e.9 off end # GPIO 2/4/5/8 + device pnp 2e.14 on end # Port 80 UART + device pnp 2e.16 off end # Deep sleep + end + end + end + end +end -- To view, visit https://review.coreboot.org/c/coreboot/+/85836?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id1a81b321c236bb1fd2763d69531958ef6f4b4e6 Gerrit-Change-Number: 85836 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com>

1 0

[S] Change in coreboot[main]: mb/asus/p8z77-v_lx2: Change super I/O chip to nct5535d
by Keith Hui (Code Review) 03 Jan '25

03 Jan '25

Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85835?usp=email ) Change subject: mb/asus/p8z77-v_lx2: Change super I/O chip to nct5535d ...................................................................... mb/asus/p8z77-v_lx2: Change super I/O chip to nct5535d Boardview indicates this board uses the smaller superio/nuvoton/nct5535d. Cut devices not present or remaining off from overridetree. Builds, but not function tested. Change-Id: Ie68f6f5b1be67ddabc8afee1dbd2db3c8b4f180b Signed-off-by: Keith Hui <buurin(a)gmail.com> --- M src/mainboard/asus/p8x7x-series/Kconfig M src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/overridetree.cb 2 files changed, 2 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/85835/1 diff --git a/src/mainboard/asus/p8x7x-series/Kconfig b/src/mainboard/asus/p8x7x-series/Kconfig index da3d10b..c3fb90c 100644 --- a/src/mainboard/asus/p8x7x-series/Kconfig +++ b/src/mainboard/asus/p8x7x-series/Kconfig @@ -38,7 +38,7 @@ select BOARD_ASUS_P8X7X_SERIES select BOARD_ROMSIZE_KB_8192 select REALTEK_8168_RESET - select SUPERIO_NUVOTON_NCT6779D + select SUPERIO_NUVOTON_NCT5535D select USE_NATIVE_RAMINIT select POWER_LED_USES_GPIO8 diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/overridetree.cb b/src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/overridetree.cb index 66bc5bb..66bc619 100644 --- a/src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/overridetree.cb +++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/overridetree.cb @@ -33,33 +33,23 @@ device ref pcie_rp8 on end # PCIEX1_2 device ref lpc on - chip superio/nuvoton/nct6779d - device pnp 2e.1 off end # Parallel + chip superio/nuvoton/nct5535d device pnp 2e.2 on # UART A io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 2e.3 off end # UART B, IR device pnp 2e.5 on # Keyboard io 0x60 = 0x0060 io 0x62 = 0x0064 irq 0x70 = 1 irq 0x72 = 12 end - device pnp 2e.6 off end # CIR device pnp 2e.7 off end # GPIO6-8 device pnp 2e.8 off end # WDT1, GPIO0, GPIO1 - device pnp 2e.108 off end # GPIO0 device pnp 2e.9 off end # GPIO8 - device pnp 2e.109 off end # GPIO1 device pnp 2e.209 on # GPIO2 irq 0xe0 = 0xff end - device pnp 2e.309 off end # GPIO3 - device pnp 2e.409 off end # GPIO4 - device pnp 2e.509 off end # GPIO5 - device pnp 2e.609 off end # GPIO6 - device pnp 2e.709 off end # GPIO7 device pnp 2e.a on end # ACPI device pnp 2e.b on # H/W Monitor, FP LED io 0x60 = 0x0290 -- To view, visit https://review.coreboot.org/c/coreboot/+/85835?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie68f6f5b1be67ddabc8afee1dbd2db3c8b4f180b Gerrit-Change-Number: 85835 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com>

1 0

[L] Change in coreboot[main]: superio/nuvoton: Add NCT5535D
by Keith Hui (Code Review) 03 Jan '25

03 Jan '25

Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85834?usp=email ) Change subject: superio/nuvoton: Add NCT5535D ...................................................................... superio/nuvoton: Add NCT5535D NCT5535D is a 64-pin LPC super I/O chip found on many Asus P8x7x series mainboards with no publicly available datasheet. However, based on mb/asus/p8z77-v_lx2, this chip can probably be driven like a NCT6779D, on which this is based. Devices not present on this chip compared to NCT6779D are parallel port, serial port B, GPIOs 0,1,3,6. p8z77-v_lx2 still builds once modified for this chip, but is not tested further. Change-Id: I3fe0dd6fc3010a50b781ca7c5c39ea73b91978a5 Signed-off-by: Keith Hui <buurin(a)gmail.com> --- A src/superio/nuvoton/nct5535d/Kconfig A src/superio/nuvoton/nct5535d/Makefile.mk A src/superio/nuvoton/nct5535d/acpi/superio.asl A src/superio/nuvoton/nct5535d/nct5535d.h A src/superio/nuvoton/nct5535d/superio.c 5 files changed, 304 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/85834/1 diff --git a/src/superio/nuvoton/nct5535d/Kconfig b/src/superio/nuvoton/nct5535d/Kconfig new file mode 100644 index 0000000..3dc2286 --- /dev/null +++ b/src/superio/nuvoton/nct5535d/Kconfig @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0-only + +config SUPERIO_NUVOTON_NCT5535D + bool + select SUPERIO_NUVOTON_COMMON_PRE_RAM + select HAVE_POWER_STATE_AFTER_FAILURE diff --git a/src/superio/nuvoton/nct5535d/Makefile.mk b/src/superio/nuvoton/nct5535d/Makefile.mk new file mode 100644 index 0000000..1b48a19 --- /dev/null +++ b/src/superio/nuvoton/nct5535d/Makefile.mk @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +ramstage-$(CONFIG_SUPERIO_NUVOTON_NCT5535D) += superio.c diff --git a/src/superio/nuvoton/nct5535d/acpi/superio.asl b/src/superio/nuvoton/nct5535d/acpi/superio.asl new file mode 100644 index 0000000..8da1f01 --- /dev/null +++ b/src/superio/nuvoton/nct5535d/acpi/superio.asl @@ -0,0 +1,180 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * Include this file into a mainboard's DSDT _SB device tree and it will + * expose the NCT5535D SuperIO and some of its functionality. + * + * It allows the change of IO ports, IRQs and DMA settings on logical + * devices, disabling and reenabling logical devices. + * + * LDN State + * 0x2 SP1 Implemented, untested + * 0x5 KBC Implemented, untested + * 0x8 GPIO Implemented, untested + * 0xb HWM Implemented, untested + * + * Controllable through preprocessor defines: + * SUPERIO_DEV Device identifier for this SIO (e.g. SIO0) + * SUPERIO_PNP_BASE I/O address of the first PnP configuration register + * NCT5535D_SHOW_SP1 If defined, Serial Port 1 will be exposed. + * NCT5535D_SHOW_KBC If defined, the Keyboard Controller will be exposed. + * NCT5535D_SHOW_GPIO If defined, GPIO support will be exposed. + * NCT5535D_SHOW_HWM If defined, the Environment Controller will be exposed. + */ + +#undef SUPERIO_CHIP_NAME +#define SUPERIO_CHIP_NAME NCT5535D +#include <superio/acpi/pnp.asl> + +#undef PNP_DEFAULT_PSC +#define PNP_DEFAULT_PSC Return (0) /* no power management */ + +#define ENABLE_KEYBOARD_WAKEUP SKWK +#define POWER_LOSS_CONTROL SPWL + +Device(SUPERIO_DEV) { + Name (_HID, EisaId("PNP0A05")) + Name (_STR, Unicode("Nuvoton NCT5535D Super I/O")) + Name (_UID, SUPERIO_UID(SUPERIO_DEV,)) + + /* SuperIO configuration ports */ + OperationRegion (CREG, SystemIO, SUPERIO_PNP_BASE, 0x02) + Field (CREG, ByteAcc, NoLock, Preserve) + { + PNP_ADDR_REG, 8, + PNP_DATA_REG, 8, + } + IndexField (PNP_ADDR_REG, PNP_DATA_REG, ByteAcc, NoLock, Preserve) + { + Offset (0x07), + PNP_LOGICAL_DEVICE, 8, /* Logical device selector */ + + Offset (0x30), + PNP_DEVICE_ACTIVE, 1, /* Logical device activation */ + ACT1, 1, /* Logical device activation */ + ACT2, 1, /* Logical device activation */ + ACT3, 1, /* Logical device activation */ + ACT4, 1, /* Logical device activation */ + ACT5, 1, /* Logical device activation */ + ACT6, 1, /* Logical device activation */ + ACT7, 1, /* Logical device activation */ + + Offset (0x60), + PNP_IO0_HIGH_BYTE, 8, /* First I/O port base - high byte */ + PNP_IO0_LOW_BYTE, 8, /* First I/O port base - low byte */ + Offset (0x62), + PNP_IO1_HIGH_BYTE, 8, /* Second I/O port base - high byte */ + PNP_IO1_LOW_BYTE, 8, /* Second I/O port base - low byte */ + Offset (0x64), + PNP_IO2_HIGH_BYTE, 8, /* Third I/O port base - high byte */ + PNP_IO2_LOW_BYTE, 8, /* Third I/O port base - low byte */ + + Offset (0x70), + PNP_IRQ0, 8, /* First IRQ */ + Offset (0x72), + PNP_IRQ1, 8, /* Second IRQ */ + Offset (0x74), + PNP_DMA0, 8, /* DRQ */ + Offset (0xe0), /* Config register 0xe0 etc. */ + ,6, + ENABLE_KEYBOARD_WAKEUP, 1, + Offset (0xe4), + ,5, + POWER_LOSS_CONTROL, 2, + } + + Method (_CRS) + { + /* Announce the used I/O ports to the OS */ + Return (ResourceTemplate () { + IO (Decode16, SUPERIO_PNP_BASE, SUPERIO_PNP_BASE, 0x01, 0x02) + }) + } + + Method (SIOS, 1, NotSerialized) + { + if (Arg0 == 5) + { + } + Else + { + } + } + + Method (SIOW, 1, NotSerialized) + { + } + + #undef PNP_ENTER_MAGIC_1ST + #undef PNP_ENTER_MAGIC_2ND + #undef PNP_ENTER_MAGIC_3RD + #undef PNP_ENTER_MAGIC_4TH + #undef PNP_EXIT_MAGIC_1ST + #undef PNP_EXIT_SPECIAL_REG + #undef PNP_EXIT_SPECIAL_VAL + #define PNP_ENTER_MAGIC_1ST 0x87 + #define PNP_ENTER_MAGIC_2ND 0x87 + #define PNP_EXIT_MAGIC_1ST 0xaa + #include <superio/acpi/pnp_config.asl> + +#ifdef NCT5535D_SHOW_SP1 + #undef SUPERIO_UART_LDN + #undef SUPERIO_UART_DDN + #undef SUPERIO_UART_PM_REG + #undef SUPERIO_UART_PM_VAL + #undef SUPERIO_UART_PM_LDN + #define SUPERIO_UART_LDN 2 + #include <superio/acpi/pnp_uart.asl> +#endif + +#ifdef NCT5535D_SHOW_KBC + #undef SUPERIO_KBC_LDN + #undef SUPERIO_KBC_PS2M + #undef SUPERIO_KBC_PS2LDN + #define SUPERIO_KBC_LDN 5 + #define SUPERIO_KBC_PS2M + #include <superio/acpi/pnp_kbc.asl> +#endif + +#ifdef NCT5535D_SHOW_HWM + #undef SUPERIO_PNP_HID + #undef SUPERIO_PNP_LDN + #undef SUPERIO_PNP_DDN + #undef SUPERIO_PNP_NO_DIS + #undef SUPERIO_PNP_PM_REG + #undef SUPERIO_PNP_PM_VAL + #undef SUPERIO_PNP_PM_LDN + #undef SUPERIO_PNP_IO0 + #undef SUPERIO_PNP_IO1 + #undef SUPERIO_PNP_IO2 + #undef SUPERIO_PNP_IRQ0 + #undef SUPERIO_PNP_IRQ1 + #undef SUPERIO_PNP_DMA + #define SUPERIO_PNP_LDN 11 + #define SUPERIO_PNP_IO0 0x08, 0x08 + #define SUPERIO_PNP_IO1 0x08, 0x08 + #define SUPERIO_PNP_IRQ0 + #include <superio/acpi/pnp_generic.asl> +#endif + +#ifdef NCT5535D_SHOW_GPIO + #undef SUPERIO_PNP_HID + #undef SUPERIO_PNP_LDN + #undef SUPERIO_PNP_DDN + #undef SUPERIO_PNP_NO_DIS + #undef SUPERIO_PNP_PM_REG + #undef SUPERIO_PNP_PM_VAL + #undef SUPERIO_PNP_PM_LDN + #undef SUPERIO_PNP_IO0 + #undef SUPERIO_PNP_IO1 + #undef SUPERIO_PNP_IO2 + #undef SUPERIO_PNP_IRQ0 + #undef SUPERIO_PNP_IRQ1 + #undef SUPERIO_PNP_DMA + #undef PNP_DEVICE_ACTIVE + #define PNP_DEVICE_ACTIVE ACT3 + #define SUPERIO_PNP_LDN 8 + #define SUPERIO_PNP_IO0 0x08, 0x08 + #include <superio/acpi/pnp_generic.asl> +#endif +} diff --git a/src/superio/nuvoton/nct5535d/nct5535d.h b/src/superio/nuvoton/nct5535d/nct5535d.h new file mode 100644 index 0000000..9dbbee4 --- /dev/null +++ b/src/superio/nuvoton/nct5535d/nct5535d.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef SUPERIO_NUVOTON_NCT5535D_H +#define SUPERIO_NUVOTON_NCT5535D_H + +/* Logical Device Numbers (LDN). */ +#define NCT5535D_SP1 0x02 /* UART */ +#define NCT5535D_KBC 0x05 /* PS/2 keyboard and mouse */ +#define NCT5535D_CIR 0x06 /* Consumer IR */ +#define NCT5535D_GPIO678_V 0x07 /* GPIO 6/7/8 */ +#define NCT5535D_WDT1_GPIO01_V 0x08 /* WDT1, GPIO 0/1 */ +#define NCT5535D_GPIO12345678_V 0x09 /* GPIO 2/5/8 */ +#define NCT5535D_ACPI 0x0A /* ACPI */ +#define NCT5535D_HWM_FPLED 0x0B /* Hardware monitor & front LED */ +#define NCT5535D_WDT1 0x0D /* Watchdog timer 1 */ +#define NCT5535D_CIRWKUP 0x0E /* CIR wakeup */ +#define NCT5535D_GPIO_PP_OD 0x0F /* GPIO Push-Pull/Open drain select */ +#define NCT5535D_PRT80 0x14 /* Port 80 UART */ +#define NCT5535D_DSLP 0x16 /* Deep sleep */ + +/* virtual LDN for GPIO */ + +#define NCT5535D_GPIOBASE ((3 << 8) | NCT5535D_WDT1_GPIO01_V) + +#define NCT5535D_GPIO2 ((2 << 8) | NCT5535D_GPIO12345678_V) +#define NCT5535D_GPIO4 ((4 << 8) | NCT5535D_GPIO12345678_V) +#define NCT5535D_GPIO5 ((5 << 8) | NCT5535D_GPIO12345678_V) +#define NCT5535D_GPIO7 ((7 << 8) | NCT5535D_GPIO12345678_V) +#define NCT5535D_GPIO8 ((0 << 8) | NCT5535D_GPIO12345678_V) + +#endif /* SUPERIO_NUVOTON_NCT5535D_H */ diff --git a/src/superio/nuvoton/nct5535d/superio.c b/src/superio/nuvoton/nct5535d/superio.c new file mode 100644 index 0000000..5532353 --- /dev/null +++ b/src/superio/nuvoton/nct5535d/superio.c @@ -0,0 +1,84 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <device/device.h> +#include <device/pnp.h> +#include <pc80/keyboard.h> +#include <option.h> +#include <superio/conf_mode.h> + +#include "nct5535d.h" + +#define MAINBOARD_POWER_OFF 0 +#define MAINBOARD_POWER_ON 1 +#define MAINBOARD_POWER_KEEP 2 + +static void nct5535d_init(struct device *dev) +{ + uint8_t byte; + uint8_t power_status; + + if (!dev->enabled) + return; + + switch (dev->path.pnp.device) { + /* TODO: Might potentially need code for HWM etc. */ + case NCT5535D_KBC: + pc_keyboard_init(NO_AUX_DEVICE); + break; + case NCT5535D_ACPI: + /* Set power state after power fail */ + power_status = get_uint_option("power_on_after_fail", + CONFIG_MAINBOARD_POWER_FAILURE_STATE); + pnp_enter_conf_mode(dev); + pnp_set_logical_device(dev); + byte = pnp_read_config(dev, 0xe4); + byte &= ~0x04; + if (power_status == MAINBOARD_POWER_ON) + byte |= (0x1 << 5); + else if (power_status == MAINBOARD_POWER_KEEP) + byte |= (0x2 << 5); + pnp_write_config(dev, 0xe4, byte); + pnp_exit_conf_mode(dev); + printk(BIOS_INFO, "set power %s after power fail\n", power_status ? "on" : "off"); + break; + } +} + +static struct device_operations ops = { + .read_resources = noop_read_resources, + .set_resources = pnp_set_resources, + .enable_resources = pnp_enable_resources, + .enable = pnp_alt_enable, + .init = nct5535d_init, + .ops_pnp_mode = &pnp_conf_mode_8787_aa, +}; + +static struct pnp_info pnp_dev_info[] = { + { NULL, NCT5535D_SP1, PNP_IO0 | PNP_IRQ0, 0x0ff8, }, + { NULL, NCT5535D_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, + 0x0fff, 0x0fff, }, + { NULL, NCT5535D_ACPI}, + { NULL, NCT5535D_HWM_FPLED, PNP_IO0 | PNP_IO1 | PNP_IRQ0, + 0x0ffe, 0x0ffe, }, + { NULL, NCT5535D_GPIO678_V}, + { NULL, NCT5535D_WDT1}, + { NULL, NCT5535D_GPIO_PP_OD}, + { NULL, NCT5535D_PRT80}, + { NULL, NCT5535D_DSLP}, + { NULL, NCT5535D_GPIOBASE, PNP_IO0, 0x0ff8, }, + { NULL, NCT5535D_GPIO2}, + { NULL, NCT5535D_GPIO4}, + { NULL, NCT5535D_GPIO5}, + { NULL, NCT5535D_GPIO7}, + { NULL, NCT5535D_GPIO8}, +}; + +static void enable_dev(struct device *dev) +{ + pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); +} + +struct chip_operations superio_nuvoton_nct5535d_ops = { + .name = "NUVOTON NCT5535D Super I/O", + .enable_dev = enable_dev, +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/85834?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3fe0dd6fc3010a50b781ca7c5c39ea73b91978a5 Gerrit-Change-Number: 85834 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com>

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[S] Change in blobs[main]: soc/mediatek/mt8196: Add GPUEB firmware v1.0
by Jarried Lin (Code Review) 03 Jan '25

03 Jan '25

Attention is currently required from: Andy Hsu, Yidi Lin, Yu-Ping Wu. Jarried Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/blobs/+/85763?usp=email ) Change subject: soc/mediatek/mt8196: Add GPUEB firmware v1.0 ...................................................................... Patch Set 6: (3 comments) File soc/mediatek/mt8196/README.md: https://review.coreboot.org/c/blobs/+/85763/comment/05611537_03c4c421?usp=e… : PS4, Line 207: tinysys-gpueb-RV33_A.mkpt_fw.img > gpueb_fw. […] Done https://review.coreboot.org/c/blobs/+/85763/comment/f5eb272b_bcf1c755?usp=e… : PS4, Line 216: tinysys-gpueb-RV33_A.mkpt_fw.img > gpueb_fw. […] Done File soc/mediatek/mt8196/gpueb_fw.img.md5: https://review.coreboot.org/c/blobs/+/85763/comment/781b315b_d41fa69f?usp=e… : PS4, Line 1: > There should be a `*` if you used `md5sum -b`. Done -- To view, visit https://review.coreboot.org/c/blobs/+/85763?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: blobs Gerrit-Branch: main Gerrit-Change-Id: I470f1575beea481cac2dcb5f3eb77587739ff2dc Gerrit-Change-Number: 85763 Gerrit-PatchSet: 6 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Andy Hsu <andy.hsu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Andy Hsu <andy.hsu(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Fri, 03 Jan 2025 02:23:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com>

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[S] Change in blobs[main]: soc/mediatek/mt8196: Add GPUEB firmware v1.0
by Jarried Lin (Code Review) 03 Jan '25

03 Jan '25

Attention is currently required from: Andy Hsu, Jarried Lin, Yidi Lin. Hello Andy Hsu, Yidi Lin, Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/blobs/+/85763?usp=email to look at the new patch set (#6). Change subject: soc/mediatek/mt8196: Add GPUEB firmware v1.0 ...................................................................... soc/mediatek/mt8196: Add GPUEB firmware v1.0 Add initial GPUEB firmware. TEST=Build pass BUG=b:317009620 Change-Id: I470f1575beea481cac2dcb5f3eb77587739ff2dc Signed-off-by: Andy.Hsu <andy.hsu(a)mediatek.corp-partner.google.com> --- M soc/mediatek/mt8196/README.md A soc/mediatek/mt8196/gpueb_fw.img A soc/mediatek/mt8196/gpueb_fw.img.md5 A soc/mediatek/mt8196/gpueb_release_notes.txt 4 files changed, 26 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/blobs refs/changes/63/85763/6 -- To view, visit https://review.coreboot.org/c/blobs/+/85763?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: blobs Gerrit-Branch: main Gerrit-Change-Id: I470f1575beea481cac2dcb5f3eb77587739ff2dc Gerrit-Change-Number: 85763 Gerrit-PatchSet: 6 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Andy Hsu <andy.hsu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Andy Hsu <andy.hsu(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com>

1 0

[S] Change in blobs[main]: soc/mediatek/mt8196: Add GPUEB firmware v1.0
by Jarried Lin (Code Review) 03 Jan '25

03 Jan '25

Attention is currently required from: Andy Hsu, Jarried Lin, Yidi Lin. Hello Andy Hsu, Yidi Lin, Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/blobs/+/85763?usp=email to look at the new patch set (#5). The following approvals got outdated and were removed: Code-Review+2 by Yidi Lin Change subject: soc/mediatek/mt8196: Add GPUEB firmware v1.0 ...................................................................... soc/mediatek/mt8196: Add GPUEB firmware v1.0 Add initial GPUEB firmware. TEST=Build pass BUG=b:317009620 Change-Id: I470f1575beea481cac2dcb5f3eb77587739ff2dc Signed-off-by: Andy.Hsu <andy.hsu(a)mediatek.corp-partner.google.com> --- M soc/mediatek/mt8196/README.md A soc/mediatek/mt8196/gpueb_fw.img A soc/mediatek/mt8196/gpueb_fw.img.md5 A soc/mediatek/mt8196/gpueb_release_notes.txt 4 files changed, 26 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/blobs refs/changes/63/85763/5 -- To view, visit https://review.coreboot.org/c/blobs/+/85763?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: blobs Gerrit-Branch: main Gerrit-Change-Id: I470f1575beea481cac2dcb5f3eb77587739ff2dc Gerrit-Change-Number: 85763 Gerrit-PatchSet: 5 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Andy Hsu <andy.hsu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Andy Hsu <andy.hsu(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com>

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