coreboot-gerrit January 2025

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[L] Change in coreboot[main]: mb/asrock: Add Z87 Extreme3 (Haswell)
by Jan Philipp Groß (Code Review) 09 Jan '25

09 Jan '25

Jan Philipp Groß has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85926?usp=email ) Change subject: mb/asrock: Add Z87 Extreme3 (Haswell) ...................................................................... mb/asrock: Add Z87 Extreme3 (Haswell) This port was done via autoport and subsequent manual tweaking. Working: - Haswell MRC.bin - All four DDR3/DDR3L DIMM slots - S3 suspend and resume - D-Sub Port - DVI-D Port - HDMI Port - RJ-45 Gigabit LAN Port - Both rear USB 2.0 Ports - All four rear USB 3.1 Gen1 Ports - Both USB 2.0 headers - USB 3.1 Gen1 header - All six SATA3 6.0 Gb/s connectors by Intel - Both PCI Express 3.0 x16 slots (Tested with RX 550 PCIe x8 GPU) - PCI Express 2.0 x1 slots (tested with TL-WDN4800 WiFi adapter) - HD Audio Jack (Audio output tested only) - Front Audio Jack (Audio output tested only) not (yet) tested: - PCI slots - IR header - COM Port header - eSATA connector - PS/2 Mouse/Keyboard Port - Optical SPDIF Out Port Change-Id: I3c13c068d899588eda80b9957127bcb6ccf8bab0 Signed-off-by: Jan Philipp Groß <jeangrande(a)mailbox.org> --- A src/mainboard/asrock/z87_extreme3/Kconfig A src/mainboard/asrock/z87_extreme3/Kconfig.name A src/mainboard/asrock/z87_extreme3/Makefile.mk A src/mainboard/asrock/z87_extreme3/acpi/ec.asl A src/mainboard/asrock/z87_extreme3/acpi/platform.asl A src/mainboard/asrock/z87_extreme3/acpi/superio.asl A src/mainboard/asrock/z87_extreme3/board_info.txt A src/mainboard/asrock/z87_extreme3/bootblock.c A src/mainboard/asrock/z87_extreme3/data.vbt A src/mainboard/asrock/z87_extreme3/devicetree.cb A src/mainboard/asrock/z87_extreme3/dsdt.asl A src/mainboard/asrock/z87_extreme3/gma-mainboard.ads A src/mainboard/asrock/z87_extreme3/gpio.c A src/mainboard/asrock/z87_extreme3/hda_verb.c A src/mainboard/asrock/z87_extreme3/romstage.c 15 files changed, 535 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/85926/1 diff --git a/src/mainboard/asrock/z87_extreme3/Kconfig b/src/mainboard/asrock/z87_extreme3/Kconfig new file mode 100644 index 0000000..0b03123 --- /dev/null +++ b/src/mainboard/asrock/z87_extreme3/Kconfig @@ -0,0 +1,27 @@ +## SPDX-License-Identifier: GPL-2.0-only + +if BOARD_ASROCK_Z87_EXTREME3 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_GMA_HAVE_VBT + select MAINBOARD_HAS_LIBGFXINIT + select MAINBOARD_USES_IFD_GBE_REGION + select NORTHBRIDGE_INTEL_HASWELL + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_LYNXPOINT + select SUPERIO_NUVOTON_NCT6776 + +config MAINBOARD_DIR + default "asrock/z87_extreme3" + +config MAINBOARD_PART_NUMBER + default "Z87 Extreme3" + +config USBDEBUG_HCD_INDEX + default 2 # Rear: USB3_0_1 (Upper) + # Header: USB2_3 +endif diff --git a/src/mainboard/asrock/z87_extreme3/Kconfig.name b/src/mainboard/asrock/z87_extreme3/Kconfig.name new file mode 100644 index 0000000..3b90f10 --- /dev/null +++ b/src/mainboard/asrock/z87_extreme3/Kconfig.name @@ -0,0 +1,4 @@ +## SPDX-License-Identifier: GPL-2.0-only + +config BOARD_ASROCK_Z87_EXTREME3 + bool "Z87 Extreme3" diff --git a/src/mainboard/asrock/z87_extreme3/Makefile.mk b/src/mainboard/asrock/z87_extreme3/Makefile.mk new file mode 100644 index 0000000..c3cf55d --- /dev/null +++ b/src/mainboard/asrock/z87_extreme3/Makefile.mk @@ -0,0 +1,6 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += bootblock.c +bootblock-y += gpio.c +romstage-y += gpio.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/asrock/z87_extreme3/acpi/ec.asl b/src/mainboard/asrock/z87_extreme3/acpi/ec.asl new file mode 100644 index 0000000..16990d4 --- /dev/null +++ b/src/mainboard/asrock/z87_extreme3/acpi/ec.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: CC-PDDC */ + +/* Please update the license if adding licensable material. */ diff --git a/src/mainboard/asrock/z87_extreme3/acpi/platform.asl b/src/mainboard/asrock/z87_extreme3/acpi/platform.asl new file mode 100644 index 0000000..aff432b --- /dev/null +++ b/src/mainboard/asrock/z87_extreme3/acpi/platform.asl @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Method(_WAK, 1) +{ + Return(Package() {0, 0}) +} + +Method(_PTS, 1) +{ +} diff --git a/src/mainboard/asrock/z87_extreme3/acpi/superio.asl b/src/mainboard/asrock/z87_extreme3/acpi/superio.asl new file mode 100644 index 0000000..16990d4 --- /dev/null +++ b/src/mainboard/asrock/z87_extreme3/acpi/superio.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: CC-PDDC */ + +/* Please update the license if adding licensable material. */ diff --git a/src/mainboard/asrock/z87_extreme3/board_info.txt b/src/mainboard/asrock/z87_extreme3/board_info.txt new file mode 100644 index 0000000..6e3ed58 --- /dev/null +++ b/src/mainboard/asrock/z87_extreme3/board_info.txt @@ -0,0 +1,7 @@ +Category: desktop +Board URL: https://www.asrock.com/mb/Intel/Z87%20Extreme3/ +ROM protocol: SPI +Flashrom support: y +ROM package: DIP-8 (1x) +ROM socketed: y +Release year: 2013 diff --git a/src/mainboard/asrock/z87_extreme3/bootblock.c b/src/mainboard/asrock/z87_extreme3/bootblock.c new file mode 100644 index 0000000..7a6607c --- /dev/null +++ b/src/mainboard/asrock/z87_extreme3/bootblock.c @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/pnp_ops.h> +#include <superio/nuvoton/common/nuvoton.h> +#include <superio/nuvoton/nct6776/nct6776.h> +#include <southbridge/intel/lynxpoint/pch.h> + +#define GLOBAL_DEV PNP_DEV(0x2e, 0) +#define SERIAL_DEV PNP_DEV(0x2e, NCT6776_SP1) +#define ACPI_DEV PNP_DEV(0x2e, NCT6776_ACPI) + +void mainboard_config_superio(void) +{ + nuvoton_pnp_enter_conf_state(GLOBAL_DEV); + + /* Select SIO pin mux states */ + pnp_write_config(GLOBAL_DEV, 0x1a, 0xf0); + pnp_write_config(GLOBAL_DEV, 0x1b, 0x68); + pnp_write_config(GLOBAL_DEV, 0x1c, 0x00); + pnp_write_config(GLOBAL_DEV, 0x24, 0x5c); + pnp_write_config(GLOBAL_DEV, 0x27, 0xd0); + pnp_write_config(GLOBAL_DEV, 0x2a, 0x62); + pnp_write_config(GLOBAL_DEV, 0x2b, 0x20); + pnp_write_config(GLOBAL_DEV, 0x2c, 0x80); + pnp_write_config(GLOBAL_DEV, 0x2d, 0x00); + pnp_write_config(GLOBAL_DEV, 0x2f, 0x03); + + /* Power RAM in S3 and let the PCH handle power failure actions */ + pnp_set_logical_device(ACPI_DEV); + pnp_write_config(ACPI_DEV, 0xe4, 0x70); + + nuvoton_pnp_exit_conf_state(GLOBAL_DEV); + + /* Enable UART */ + nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} diff --git a/src/mainboard/asrock/z87_extreme3/data.vbt b/src/mainboard/asrock/z87_extreme3/data.vbt new file mode 100644 index 0000000..d592fa6 --- /dev/null +++ b/src/mainboard/asrock/z87_extreme3/data.vbt Binary files differ diff --git a/src/mainboard/asrock/z87_extreme3/devicetree.cb b/src/mainboard/asrock/z87_extreme3/devicetree.cb new file mode 100644 index 0000000..c1fbf24 --- /dev/null +++ b/src/mainboard/asrock/z87_extreme3/devicetree.cb @@ -0,0 +1,138 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +chip northbridge/intel/haswell + register "gpu_ddi_e_connected" = "1" + register "gpu_dp_b_hotplug" = "4" + register "gpu_dp_d_hotplug" = "4" + register "spd_addresses" = "{0x50, 0x51, 0x52, 0x53}" + chip cpu/intel/haswell + device cpu_cluster 0 on + ops haswell_cpu_bus_ops + end + end + device domain 0 on + ops haswell_pci_domain_ops + device pci 00.0 on # Desktop Host bridge + subsystemid 0x1849 0x0c00 + end + device pci 01.0 on # PEG + end + device pci 02.0 on # iGPU + subsystemid 0x1849 0x0412 + end + device pci 03.0 on # Mini-HD audio + subsystemid 0x1849 0x0c0c + end + chip southbridge/intel/lynxpoint # Intel Series 8 Lynx Point PCH + register "gen1_dec" = "0x000c0291" + register "gen2_dec" = "0x000c0241" + register "gen3_dec" = "0x000c0251" + register "gpe0_en_1" = "0x246" + register "sata_port0_gen3_dtle" = "0x2" + register "sata_port1_gen3_dtle" = "0x2" + register "sata_port_map" = "0x3f" + device pci 14.0 on # xHCI Controller + subsystemid 0x1849 0x8c31 + end + device pci 16.0 on # MEI #1 + subsystemid 0x1849 0x8c3a + end + device pci 16.1 off # MEI #2 + end + device pci 19.0 on # Intel Gigabit Ethernet + subsystemid 0x1849 0x153b + end + device pci 1a.0 on # USB2 EHCI #2 + subsystemid 0x1849 0x8c2d + end + device pci 1b.0 on # High Definition Audio + subsystemid 0x1849 0xc892 + end + device pci 1c.0 off end # RP #1 + device pci 1c.1 off end # RP #2 + device pci 1c.2 off end # RP #3 + device pci 1c.3 off end # RP #4 + device pci 1c.4 off end # RP #5 + device pci 1c.5 on # RP #6: PCIE1 x1 slot + subsystemid 0x1849 0x8c1a + end + device pci 1c.6 on # RP #7: ASM1083/1085 PCIe to PCI Bridge + subsystemid 0x1849 0x244e + end + device pci 1c.7 off end # RP #8 + device pci 1d.0 on # USB2 EHCI #1 + subsystemid 0x1849 0x8c26 + end + device pci 1f.0 on # LPC bridge + subsystemid 0x1849 0x8c44 + chip superio/nuvoton/nct6776 + device pnp 2e.0 off end # Floppy + device pnp 2e.1 on # Parallel + io 0x60 = 0x0378 + irq 0x70 = 6 + drq 0x74 = 2 + irq 0xf0 = 0x3b # + ECP and EPP 1.9 + end + device pnp 2e.2 on # UART A + io 0x60 = 0x03f8 + irq 0x70 = 4 + end + device pnp 2e.3 off end # UART B, IR + device pnp 2e.5 on # PS/2 Keyboard/Mouse + io 0x60 = 0x0060 + io 0x62 = 0x0064 + irq 0x70 = 1 # + Keyboard IRQ + irq 0x72 = 12 # + Mouse IRQ (unused) + end + device pnp 2e.6 off end # CIR + device pnp 2e.7 off end # GPIO8 + device pnp 2e.107 off end # GPIO9 + device pnp 2e.8 off end # WDT + device pnp 2e.108 on # GPIO0 + irq 0xe0 = 0xf9 # + GPIO0 direction + irq 0xe1 = 0xfd # + GPIO0 value + end + device pnp 2e.208 off end # GPIOA + device pnp 2e.308 off end # GPIO base + device pnp 2e.109 on # GPIO1 + irq 0xf0 = 0xf1 # + GPIO1 direction + irq 0xf1 = 0xf1 # + GPIO1 value + end + device pnp 2e.209 off end # GPIO2 + device pnp 2e.309 off end # GPIO3 + device pnp 2e.409 off end # GPIO4 + device pnp 2e.509 off end # GPIO5 + device pnp 2e.609 off end # GPIO6 + device pnp 2e.709 on # GPIO7 + irq 0xe0 = 0xff # + GPIO7 direction + end + device pnp 2e.a on # ACPI + irq 0xe4 = 0x10 # + Power RAM in S3 + irq 0xf0 = 0x20 + end + device pnp 2e.b on # HWM, LED + irq 0x30 = 0xe1 # + Fan RPM sense pins + io 0x60 = 0x0290 # + HWM base address + irq 0x70 = 0 + end + device pnp 2e.d off end # VID + device pnp 2e.e off end # CIR wake-up + device pnp 2e.f off end # GPIO PP/OD + device pnp 2e.14 off end # SVID + device pnp 2e.16 off end # Deep sleep + device pnp 2e.17 off end # GPIOA + end + end + device pci 1f.2 on # SATA Controller (AHCI) + subsystemid 0x1849 0x8c02 + end + device pci 1f.3 on # SMBus + subsystemid 0x1849 0x8c22 + end + device pci 1f.5 off # SATA Controller (Legacy) + end + device pci 1f.6 off # Thermal + end + end + end +end diff --git a/src/mainboard/asrock/z87_extreme3/dsdt.asl b/src/mainboard/asrock/z87_extreme3/dsdt.asl new file mode 100644 index 0000000..2eb0805 --- /dev/null +++ b/src/mainboard/asrock/z87_extreme3/dsdt.asl @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 +) +{ + #include <acpi/dsdt_top.asl> + #include "acpi/platform.asl" + #include <cpu/intel/common/acpi/cpu.asl> + #include <southbridge/intel/common/acpi/platform.asl> + /* global NVS and variables. */ + #include <southbridge/intel/lynxpoint/acpi/globalnvs.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> + + Device (\_SB.PCI0) + { + #include <northbridge/intel/haswell/acpi/hostbridge.asl> + #include <southbridge/intel/lynxpoint/acpi/pch.asl> + } +} diff --git a/src/mainboard/asrock/z87_extreme3/gma-mainboard.ads b/src/mainboard/asrock/z87_extreme3/gma-mainboard.ads new file mode 100644 index 0000000..cab2ff7 --- /dev/null +++ b/src/mainboard/asrock/z87_extreme3/gma-mainboard.ads @@ -0,0 +1,17 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (HDMI1, -- DVI-D + HDMI2, -- HDMI + Analog, -- D-SUB + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/asrock/z87_extreme3/gpio.c b/src/mainboard/asrock/z87_extreme3/gpio.c new file mode 100644 index 0000000..54dd668 --- /dev/null +++ b/src/mainboard/asrock/z87_extreme3/gpio.c @@ -0,0 +1,186 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_NATIVE, + .gpio3 = GPIO_MODE_NATIVE, + .gpio4 = GPIO_MODE_NATIVE, + .gpio5 = GPIO_MODE_NATIVE, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_NATIVE, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_NATIVE, + .gpio12 = GPIO_MODE_NATIVE, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_NATIVE, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_NATIVE, + .gpio22 = GPIO_MODE_NATIVE, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_GPIO, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_NATIVE, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio25 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio15 = GPIO_LEVEL_LOW, + .gpio24 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio8 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_NATIVE, + .gpio37 = GPIO_MODE_NATIVE, + .gpio38 = GPIO_MODE_NATIVE, + .gpio39 = GPIO_MODE_NATIVE, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_GPIO, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_NATIVE, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio45 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_OUTPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio55 = GPIO_DIR_OUTPUT, + .gpio57 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, + .gpio33 = GPIO_LEVEL_HIGH, + .gpio35 = GPIO_LEVEL_LOW, + .gpio51 = GPIO_LEVEL_HIGH, + .gpio53 = GPIO_LEVEL_HIGH, + .gpio55 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_NATIVE, + .gpio71 = GPIO_MODE_NATIVE, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_GPIO, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_OUTPUT, + .gpio73 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { + .gpio72 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/asrock/z87_extreme3/hda_verb.c b/src/mainboard/asrock/z87_extreme3/hda_verb.c new file mode 100644 index 0000000..d2232bf --- /dev/null +++ b/src/mainboard/asrock/z87_extreme3/hda_verb.c @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10ec0892, /* Codec Vendor / Device ID: Realtek */ + 0x1849c892, /* Subsystem ID */ + 15, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x1849c892), + AZALIA_PIN_CFG(0, 0x11, 0x411111f0), + AZALIA_PIN_CFG(0, 0x12, 0x411111f0), + AZALIA_PIN_CFG(0, 0x14, 0x01014010), + AZALIA_PIN_CFG(0, 0x15, 0x01011012), + AZALIA_PIN_CFG(0, 0x16, 0x01016011), + AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, 0x01a19840), + AZALIA_PIN_CFG(0, 0x19, 0x02a19850), + AZALIA_PIN_CFG(0, 0x1a, 0x0181304f), + AZALIA_PIN_CFG(0, 0x1b, 0x02214020), + AZALIA_PIN_CFG(0, 0x1c, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, 0x4005e601), + AZALIA_PIN_CFG(0, 0x1e, 0x01452130), + AZALIA_PIN_CFG(0, 0x1f, 0x411111f0), + +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/asrock/z87_extreme3/romstage.c b/src/mainboard/asrock/z87_extreme3/romstage.c new file mode 100644 index 0000000..467be65 --- /dev/null +++ b/src/mainboard/asrock/z87_extreme3/romstage.c @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <stdint.h> +#include <northbridge/intel/haswell/haswell.h> +#include <southbridge/intel/lynxpoint/pch.h> + +void mainboard_config_rcba(void) +{ +} + +/* FIXME: called after romstage_common, remove it if not used */ +void mb_late_romstage_setup(void) +{ +} + +const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS] = { + /* FIXME: Length and Location are computed from IOBP values, may be inaccurate */ + /* Length, Enable, OCn#, Location */ + { 0x0040, 1, 0, USB_PORT_FLEX }, + { 0x0040, 1, 0, USB_PORT_FLEX }, + { 0x0040, 1, 1, USB_PORT_FLEX }, + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_FLEX }, + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_FLEX }, + { 0x0040, 1, 2, USB_PORT_FLEX }, + { 0x0040, 1, 3, USB_PORT_FLEX }, + { 0x0040, 1, 3, USB_PORT_FLEX }, + { 0x0040, 1, 4, USB_PORT_FLEX }, + { 0x0040, 1, 4, USB_PORT_FLEX }, + { 0x0040, 1, 5, USB_PORT_FLEX }, + { 0x0040, 1, 5, USB_PORT_FLEX }, + { 0x0040, 1, 6, USB_PORT_FLEX }, + { 0x0040, 1, 6, USB_PORT_FLEX }, +}; + +const struct usb3_port_config mainboard_usb3_ports[MAX_USB3_PORTS] = { + { 1, 0 }, + { 1, 0 }, + { 1, 1 }, + { 1, 1 }, + { 1, 2 }, + { 1, 2 }, +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/85926?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3c13c068d899588eda80b9957127bcb6ccf8bab0 Gerrit-Change-Number: 85926 Gerrit-PatchSet: 1 Gerrit-Owner: Jan Philipp Groß <jeangrande(a)mailbox.org>

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[L] Change in coreboot[main]: mb/starlabs/lite: Put options in CFR cbtable
by Matt DeVillier (Code Review) 09 Jan '25

09 Jan '25

Attention is currently required from: Sean Rhodes. Matt DeVillier has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/76583?usp=email ) Change subject: mb/starlabs/lite: Put options in CFR cbtable ...................................................................... Patch Set 14: (1 comment) File src/mainboard/starlabs/lite/cfr.c: https://review.coreboot.org/c/coreboot/+/76583/comment/2ce51fb9_6a3aca24?us… : PS14, Line 213: void lb_board(struct lb_header *header) : { : char *current = (char *)lb_new_record(header); : struct lb_cfr *cfr_root = (struct lb_cfr *)current; : : cfr_write_setup_menu(cfr_root, sm_root); : } this should be: ``` void mb_cfr_setup_menu(struct lb_cfr *cfr_root) { cfr_write_setup_menu(cfr_root, sm_root); } ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/76583?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I42ae5b35e6b53b5a13ec3f80180f4955db9b6ce2 Gerrit-Change-Number: 76583 Gerrit-PatchSet: 14 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Comment-Date: Thu, 09 Jan 2025 19:53:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: Documentation/drivers/smmstore: Fix dead link
by Felix Singer (Code Review) 09 Jan '25

09 Jan '25

Attention is currently required from: Werner Zeh. Felix Singer has posted comments on this change by Werner Zeh. ( https://review.coreboot.org/c/coreboot/+/85916?usp=email ) Change subject: Documentation/drivers/smmstore: Fix dead link ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85916?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic6ba341cbd37edec142f8868ffe9ef677736b3dd Gerrit-Change-Number: 85916 Gerrit-PatchSet: 1 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Thu, 09 Jan 2025 19:50:28 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: lint/checkpatch: Do not require an empty line before error injection
by Felix Singer (Code Review) 09 Jan '25

09 Jan '25

Attention is currently required from: Elyes Haouas, Martin L Roth. Felix Singer has posted comments on this change by Elyes Haouas. ( https://review.coreboot.org/c/coreboot/+/81950?usp=email ) Change subject: lint/checkpatch: Do not require an empty line before error injection ...................................................................... Patch Set 2: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/81950/comment/f41afa3e_337314fa?us… : PS2, Line 9: This updates the script to upsteam version 6.8 > `'upsteam' may be misspelled - perhaps 'upstream'?` Please fix. https://review.coreboot.org/c/coreboot/+/81950/comment/a95b7324_199752d6?us… : PS2, Line 10: 2f9dadba5ba02e1510a04ce57ebfb9e08fd872a8 Seems like it's the wrong commit id -- To view, visit https://review.coreboot.org/c/coreboot/+/81950?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I40708185df4036f7aaa1dcb419663c9e54aad44a Gerrit-Change-Number: 81950 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Thu, 09 Jan 2025 19:49:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: lint/checkpatch: Add __aligned to the list of attribute notes
by Felix Singer (Code Review) 09 Jan '25

09 Jan '25

Attention is currently required from: Elyes Haouas, Martin L Roth. Felix Singer has posted comments on this change by Elyes Haouas. ( https://review.coreboot.org/c/coreboot/+/81949?usp=email ) Change subject: lint/checkpatch: Add __aligned to the list of attribute notes ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81949?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9274e8b5ed5ada27c290c462b0c59eccf1b0b60d Gerrit-Change-Number: 81949 Gerrit-PatchSet: 3 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Thu, 09 Jan 2025 19:46:57 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: Documentation: Fix wrong link to commit message guidelines
by Felix Singer (Code Review) 09 Jan '25

09 Jan '25

Attention is currently required from: Martin L Roth, Werner Zeh. Felix Singer has posted comments on this change by Werner Zeh. ( https://review.coreboot.org/c/coreboot/+/85915?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: Documentation: Fix wrong link to commit message guidelines ...................................................................... Patch Set 1: Code-Review+1 (7 comments) Patchset: PS1: Thank you! File Documentation/contributing/gerrit_guidelines.md: https://review.coreboot.org/c/coreboot/+/85915/comment/46b456d6_24ce8512?us… : PS1, Line 445: - Please use asterisks for consistency as it's done for all other places in this document. https://review.coreboot.org/c/coreboot/+/85915/comment/c5091cb8_196d1c2b?us… : PS1, Line 455: gerrit Uppercase ```suggestion - A Change-Id: line to let Gerrit track this logical change``` https://review.coreboot.org/c/coreboot/+/85915/comment/d3c57d1c_50f4fe0e?us… : PS1, Line 456: signed Uppercase ```suggestion - A Signed-off-by: line according to [Signed-off-by policy](#sign-off-procedure)``` https://review.coreboot.org/c/coreboot/+/85915/comment/a6f2a261_c2ff3840?us… : PS1, Line 459: install the commit-msg hook Since there is no reference, it's a bit confusing how to get this thing. I don't have an easy way to solve this without adding much more text. Should we leave it for now and look for a better way later? https://review.coreboot.org/c/coreboot/+/85915/comment/abde82f7_7df7590f?us… : PS1, Line 460: to Typo ```suggestion let the script do it for you. And remember to always use ``` https://review.coreboot.org/c/coreboot/+/85915/comment/a66a8f2f_a416b2e2?us… : PS1, Line 468: she or he Simplification ```suggestion * If anyone involved in coreboot reads your comment in a year or so, they``` -- To view, visit https://review.coreboot.org/c/coreboot/+/85915?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1cd2b13da6fe59697d677c7350d73eda5d486544 Gerrit-Change-Number: 85915 Gerrit-PatchSet: 1 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Thu, 09 Jan 2025 19:43:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: soc/amd/common/psp_gen2: Add config for PSP MBOX offset
by Ana Carolina Cabral (Code Review) 09 Jan '25

09 Jan '25

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier, Naresh Solanki. Ana Carolina Cabral has posted comments on this change by Naresh Solanki. ( https://review.coreboot.org/c/coreboot/+/85626?usp=email ) Change subject: soc/amd/common/psp_gen2: Add config for PSP MBOX offset ...................................................................... Patch Set 1: Code-Review+1 (1 comment) Patchset: PS1: Tested with Birman Plus and it solved the issue for psp timeout Before: [DEBUG] PSP: Notify SMM info... error: PSP command timeout After: [DEBUG] PSP: Notify SMM info... OK -- To view, visit https://review.coreboot.org/c/coreboot/+/85626?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iefcc7d3b75689b43399a7a7b612417c155619211 Gerrit-Change-Number: 85626 Gerrit-PatchSet: 1 Gerrit-Owner: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Reviewer: Ana Carolina Cabral Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 09 Jan 2025 19:34:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: sb/intel/bd82x6x: Drop xhci_overcurrent_mapping
by Keith Hui (Code Review) 09 Jan '25

09 Jan '25

Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85925?usp=email ) Change subject: sb/intel/bd82x6x: Drop xhci_overcurrent_mapping ...................................................................... sb/intel/bd82x6x: Drop xhci_overcurrent_mapping This is now drawn (indirectly) from main usb_port_config. Change-Id: I8c5e9b2016cf56538de06575181a0a6b738c6a28 Signed-off-by: Keith Hui <buurin(a)gmail.com> --- M src/southbridge/intel/bd82x6x/chip.h 1 file changed, 0 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/85925/1 diff --git a/src/southbridge/intel/bd82x6x/chip.h b/src/southbridge/intel/bd82x6x/chip.h index 0ec97bd..14c22b2 100644 --- a/src/southbridge/intel/bd82x6x/chip.h +++ b/src/southbridge/intel/bd82x6x/chip.h @@ -72,8 +72,6 @@ uint32_t xhci_switchable_ports; /* Ports which support SuperSpeed (USB 3.0 additional lanes). */ uint32_t superspeed_capable_ports; - /* Overcurrent Mapping for USB 3.0 Ports */ - uint32_t xhci_overcurrent_mapping; uint32_t spi_uvscc; uint32_t spi_lvscc; -- To view, visit https://review.coreboot.org/c/coreboot/+/85925?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8c5e9b2016cf56538de06575181a0a6b738c6a28 Gerrit-Change-Number: 85925 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com>

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[S] Change in coreboot[main]: mb/*: Drop xhci_overcurrent_map II
by Keith Hui (Code Review) 09 Jan '25

09 Jan '25

Attention is currently required from: Alexander Couzens, Nicholas Chin. Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85924?usp=email ) Change subject: mb/*: Drop xhci_overcurrent_map II ...................................................................... mb/*: Drop xhci_overcurrent_map II This is now copied from USBOCM1 built with main USB port config. Boards to be patched here have mismatched xhci_overcurrent_map and needs manual review and/or testing. Change-Id: Ie60d34cae5ae94d148854b42f77ab4c02e8f49ef Signed-off-by: Keith Hui <buurin(a)gmail.com> --- M src/mainboard/dell/snb_ivb_latitude/variants/e5530/overridetree.cb M src/mainboard/dell/snb_ivb_latitude/variants/e6230/overridetree.cb M src/mainboard/dell/snb_ivb_latitude/variants/e6330/overridetree.cb M src/mainboard/dell/snb_ivb_latitude/variants/e6430/overridetree.cb M src/mainboard/dell/snb_ivb_latitude/variants/e6530/overridetree.cb M src/mainboard/dell/snb_ivb_workstations/variants/baseboard/devicetree.cb M src/mainboard/hp/snb_ivb_desktops/variants/compaq_8300_elite_sff/overridetree.cb M src/mainboard/hp/snb_ivb_desktops/variants/compaq_elite_8300_usdt/overridetree.cb M src/mainboard/hp/snb_ivb_desktops/variants/z220_cmt_workstation/overridetree.cb M src/mainboard/lenovo/t430s/devicetree.cb M src/mainboard/lenovo/t530/devicetree.cb M src/mainboard/lenovo/x131e/devicetree.cb M src/mainboard/lenovo/x230/devicetree.cb 13 files changed, 4 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/85924/1 diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e5530/overridetree.cb b/src/mainboard/dell/snb_ivb_latitude/variants/e5530/overridetree.cb index 85c448d..0fd59a3 100644 --- a/src/mainboard/dell/snb_ivb_latitude/variants/e5530/overridetree.cb +++ b/src/mainboard/dell/snb_ivb_latitude/variants/e5530/overridetree.cb @@ -29,7 +29,6 @@ device ref xhci on register "superspeed_capable_ports" = "0x0000000f" - register "xhci_overcurrent_mapping" = "0x00000c03" register "xhci_switchable_ports" = "0x0000000f" end device ref gbe off end diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6230/overridetree.cb b/src/mainboard/dell/snb_ivb_latitude/variants/e6230/overridetree.cb index 3a0fa72..0f4f924 100644 --- a/src/mainboard/dell/snb_ivb_latitude/variants/e6230/overridetree.cb +++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6230/overridetree.cb @@ -29,7 +29,6 @@ device ref xhci on register "superspeed_capable_ports" = "0x0000000f" - register "xhci_overcurrent_mapping" = "0x00000c03" register "xhci_switchable_ports" = "0x0000000f" end device ref sata1 on diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6330/overridetree.cb b/src/mainboard/dell/snb_ivb_latitude/variants/e6330/overridetree.cb index 4125159..5866828 100644 --- a/src/mainboard/dell/snb_ivb_latitude/variants/e6330/overridetree.cb +++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6330/overridetree.cb @@ -29,7 +29,6 @@ device ref xhci on register "superspeed_capable_ports" = "0x0000000f" - register "xhci_overcurrent_mapping" = "0x00000c03" register "xhci_switchable_ports" = "0x0000000f" end end diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6430/overridetree.cb b/src/mainboard/dell/snb_ivb_latitude/variants/e6430/overridetree.cb index 631f404..3248dad 100644 --- a/src/mainboard/dell/snb_ivb_latitude/variants/e6430/overridetree.cb +++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6430/overridetree.cb @@ -28,7 +28,6 @@ }" device ref xhci on register "superspeed_capable_ports" = "0x0000000f" - register "xhci_overcurrent_mapping" = "0x00000c03" register "xhci_switchable_ports" = "0x0000000f" end end diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6530/overridetree.cb b/src/mainboard/dell/snb_ivb_latitude/variants/e6530/overridetree.cb index 8b9c82f..025b399 100644 --- a/src/mainboard/dell/snb_ivb_latitude/variants/e6530/overridetree.cb +++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6530/overridetree.cb @@ -29,7 +29,7 @@ device ref xhci on register "superspeed_capable_ports" = "0x0000000f" - register "xhci_overcurrent_mapping" = "0x00000c03" + register "xhci_switchable_ports" = "0x0000000f" end end diff --git a/src/mainboard/dell/snb_ivb_workstations/variants/baseboard/devicetree.cb b/src/mainboard/dell/snb_ivb_workstations/variants/baseboard/devicetree.cb index 2ba11b4..b9f5bff 100644 --- a/src/mainboard/dell/snb_ivb_workstations/variants/baseboard/devicetree.cb +++ b/src/mainboard/dell/snb_ivb_workstations/variants/baseboard/devicetree.cb @@ -28,7 +28,6 @@ register "spi_lvscc" = "0x2005" register "spi_uvscc" = "0x2005" register "superspeed_capable_ports" = "0x0000000f" - register "xhci_overcurrent_mapping" = "0x08040201" register "xhci_switchable_ports" = "0x0000000f" register "usb_port_config" = "{ { 1, 6, 0 }, diff --git a/src/mainboard/hp/snb_ivb_desktops/variants/compaq_8300_elite_sff/overridetree.cb b/src/mainboard/hp/snb_ivb_desktops/variants/compaq_8300_elite_sff/overridetree.cb index eb296f3..8f13725 100644 --- a/src/mainboard/hp/snb_ivb_desktops/variants/compaq_8300_elite_sff/overridetree.cb +++ b/src/mainboard/hp/snb_ivb_desktops/variants/compaq_8300_elite_sff/overridetree.cb @@ -8,7 +8,6 @@ register "sata_port_map" = "0xf" register "superspeed_capable_ports" = "0x0000000f" register "xhci_switchable_ports" = "0x0000000f" - register "xhci_overcurrent_mapping" = "0x0000000f" register "usb_port_config" = "{ { 1, 0, 0 }, { 1, 0, 0 }, diff --git a/src/mainboard/hp/snb_ivb_desktops/variants/compaq_elite_8300_usdt/overridetree.cb b/src/mainboard/hp/snb_ivb_desktops/variants/compaq_elite_8300_usdt/overridetree.cb index 3511bbd..b4ab82f 100644 --- a/src/mainboard/hp/snb_ivb_desktops/variants/compaq_elite_8300_usdt/overridetree.cb +++ b/src/mainboard/hp/snb_ivb_desktops/variants/compaq_elite_8300_usdt/overridetree.cb @@ -14,7 +14,6 @@ # 0x1: 2.5", 0x2: DVD, 0x4: mSATA register "sata_port_map" = "0x7" register "superspeed_capable_ports" = "0x0000000f" - register "xhci_overcurrent_mapping" = "0x00000c03" register "xhci_switchable_ports" = "0x0000000f" register "usb_port_config" = "{ { 1, 0, 0 }, diff --git a/src/mainboard/hp/snb_ivb_desktops/variants/z220_cmt_workstation/overridetree.cb b/src/mainboard/hp/snb_ivb_desktops/variants/z220_cmt_workstation/overridetree.cb index a8dcb17..1701159 100644 --- a/src/mainboard/hp/snb_ivb_desktops/variants/z220_cmt_workstation/overridetree.cb +++ b/src/mainboard/hp/snb_ivb_desktops/variants/z220_cmt_workstation/overridetree.cb @@ -8,7 +8,6 @@ register "sata_port_map" = "0x3f" register "superspeed_capable_ports" = "0x0000000f" register "xhci_switchable_ports" = "0x0000000f" - register "xhci_overcurrent_mapping" = "0x0000000f" register "usb_port_config" = "{ { 1, 0, 0 }, { 1, 0, 0 }, diff --git a/src/mainboard/lenovo/t430s/devicetree.cb b/src/mainboard/lenovo/t430s/devicetree.cb index 10a388a..8670ad9 100644 --- a/src/mainboard/lenovo/t430s/devicetree.cb +++ b/src/mainboard/lenovo/t430s/devicetree.cb @@ -43,7 +43,7 @@ # Wire port 4 (wwan usb) to ehci for it lacks superspeed components register "xhci_switchable_ports" = "0x7" register "superspeed_capable_ports" = "0xf" - register "xhci_overcurrent_mapping" = "0x4000201" + # Enable zero-based linear PCIe root port functions register "pcie_port_coalesce" = "true" diff --git a/src/mainboard/lenovo/t530/devicetree.cb b/src/mainboard/lenovo/t530/devicetree.cb index b8dcfd0..9fa81f0 100644 --- a/src/mainboard/lenovo/t530/devicetree.cb +++ b/src/mainboard/lenovo/t530/devicetree.cb @@ -46,7 +46,7 @@ register "xhci_switchable_ports" = "0xf" register "superspeed_capable_ports" = "0xf" - register "xhci_overcurrent_mapping" = "0x04000201" + register "docking_supported" = "1" diff --git a/src/mainboard/lenovo/x131e/devicetree.cb b/src/mainboard/lenovo/x131e/devicetree.cb index b74e78f..6bdc87c 100644 --- a/src/mainboard/lenovo/x131e/devicetree.cb +++ b/src/mainboard/lenovo/x131e/devicetree.cb @@ -42,7 +42,7 @@ register "xhci_switchable_ports" = "0xf" register "superspeed_capable_ports" = "0xf" - register "xhci_overcurrent_mapping" = "0x00000c03" + register "usb_port_config" = "{ {1, 1, 0}, /* P0: USB 3.0 1 (OC0) */ {1, 1, 0}, /* P1: USB 3.0 2 (OC0) */ diff --git a/src/mainboard/lenovo/x230/devicetree.cb b/src/mainboard/lenovo/x230/devicetree.cb index f47e3b7..3067096 100644 --- a/src/mainboard/lenovo/x230/devicetree.cb +++ b/src/mainboard/lenovo/x230/devicetree.cb @@ -44,7 +44,6 @@ # Do not enable xHCI Port 4 since WWAN USB is EHCI-only register "xhci_switchable_ports" = "0x7" register "superspeed_capable_ports" = "0x7" - register "xhci_overcurrent_mapping" = "0x4000201" # Enable zero-based linear PCIe root port functions register "pcie_port_coalesce" = "true" -- To view, visit https://review.coreboot.org/c/coreboot/+/85924?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie60d34cae5ae94d148854b42f77ab4c02e8f49ef Gerrit-Change-Number: 85924 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com>

1 0

[S] Change in coreboot[main]: mb/*: Drop xhci_overcurrent_map I
by Keith Hui (Code Review) 09 Jan '25

09 Jan '25

Attention is currently required from: Alexander Couzens, Kevin Keijzer. Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85923?usp=email ) Change subject: mb/*: Drop xhci_overcurrent_map I ...................................................................... mb/*: Drop xhci_overcurrent_map I This is now copied from USBOCM1 built with main USB port config. Boards patched here have matching EHCI and xHCI overcurrent mappings. Change-Id: I36944e2f2ed265ee492019b75b7dd8b95ca26dbb Signed-off-by: Keith Hui <buurin(a)gmail.com> --- M src/mainboard/asrock/b75m-itx/devicetree.cb M src/mainboard/asrock/b75pro3-m/devicetree.cb M src/mainboard/asrock/h77pro4-m/devicetree.cb M src/mainboard/asus/p8x7x-series/devicetree.cb M src/mainboard/compulab/intense_pc/devicetree.cb M src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/overridetree.cb M src/mainboard/hp/snb_ivb_desktops/variants/z220_sff_workstation/overridetree.cb M src/mainboard/hp/snb_ivb_laptops/variants/2170p/overridetree.cb M src/mainboard/hp/snb_ivb_laptops/variants/2570p/overridetree.cb M src/mainboard/hp/snb_ivb_laptops/variants/8470p/overridetree.cb M src/mainboard/hp/snb_ivb_laptops/variants/8770w/overridetree.cb M src/mainboard/hp/snb_ivb_laptops/variants/folio_9470m/overridetree.cb M src/mainboard/hp/snb_ivb_laptops/variants/revolve_810_g1/overridetree.cb M src/mainboard/lenovo/s230u/devicetree.cb M src/mainboard/lenovo/t430/devicetree.cb M src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb M src/mainboard/roda/rv11/variants/rv11/devicetree.cb M src/mainboard/roda/rv11/variants/rw11/devicetree.cb M src/mainboard/supermicro/x9sae/devicetree.cb 19 files changed, 0 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/85923/1 diff --git a/src/mainboard/asrock/b75m-itx/devicetree.cb b/src/mainboard/asrock/b75m-itx/devicetree.cb index 8ecae25..0c12853 100644 --- a/src/mainboard/asrock/b75m-itx/devicetree.cb +++ b/src/mainboard/asrock/b75m-itx/devicetree.cb @@ -23,7 +23,6 @@ register "sata_interface_speed_support" = "0x3" register "sata_port_map" = "0x3f" register "superspeed_capable_ports" = "0x0000000f" - register "xhci_overcurrent_mapping" = "0x00000c03" register "xhci_switchable_ports" = "0x0000000f" register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" diff --git a/src/mainboard/asrock/b75pro3-m/devicetree.cb b/src/mainboard/asrock/b75pro3-m/devicetree.cb index 1cf5015..c94e5d00 100644 --- a/src/mainboard/asrock/b75pro3-m/devicetree.cb +++ b/src/mainboard/asrock/b75pro3-m/devicetree.cb @@ -35,7 +35,6 @@ register "sata_interface_speed_support" = "0x3" register "sata_port_map" = "0x3f" register "superspeed_capable_ports" = "0x0000000f" - register "xhci_overcurrent_mapping" = "0x00000c03" register "xhci_switchable_ports" = "0x0000000f" register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" diff --git a/src/mainboard/asrock/h77pro4-m/devicetree.cb b/src/mainboard/asrock/h77pro4-m/devicetree.cb index 05cb870..581b9a5 100644 --- a/src/mainboard/asrock/h77pro4-m/devicetree.cb +++ b/src/mainboard/asrock/h77pro4-m/devicetree.cb @@ -19,7 +19,6 @@ register "spi_lvscc" = "0x2005" register "spi_uvscc" = "0x2005" register "superspeed_capable_ports" = "0x0000000f" - register "xhci_overcurrent_mapping" = "0x00000c03" register "xhci_switchable_ports" = "0x0000000f" register "usb_port_config" = "{ { 1, 0, 0 }, diff --git a/src/mainboard/asus/p8x7x-series/devicetree.cb b/src/mainboard/asus/p8x7x-series/devicetree.cb index e9b97bc..b1b3901 100644 --- a/src/mainboard/asus/p8x7x-series/devicetree.cb +++ b/src/mainboard/asus/p8x7x-series/devicetree.cb @@ -25,7 +25,6 @@ register "spi_lvscc" = "0x2005" register "spi_uvscc" = "0x2005" register "superspeed_capable_ports" = "0x0000000f" - register "xhci_overcurrent_mapping" = "0x00000c03" register "xhci_switchable_ports" = "0x0000000f" device ref xhci on end diff --git a/src/mainboard/compulab/intense_pc/devicetree.cb b/src/mainboard/compulab/intense_pc/devicetree.cb index 0c79309..54362d5 100644 --- a/src/mainboard/compulab/intense_pc/devicetree.cb +++ b/src/mainboard/compulab/intense_pc/devicetree.cb @@ -44,7 +44,6 @@ # enable ONLY ports present on stock MintBox/Intense PC #register "sata_port_map" = "0x1d" register "superspeed_capable_ports" = "0x0000000f" - register "xhci_overcurrent_mapping" = "0x00000c03" register "xhci_switchable_ports" = "0x0000000f" register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/overridetree.cb b/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/overridetree.cb index 8c8820d..9f2c197 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/overridetree.cb +++ b/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/overridetree.cb @@ -2,7 +2,6 @@ device domain 0 on chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH device ref mei1 off end - register "xhci_overcurrent_mapping" = "0x00000c03" device ref pcie_rp2 on end device ref pcie_rp3 on device pci 00.0 on # PCI 1969:1091 diff --git a/src/mainboard/hp/snb_ivb_desktops/variants/z220_sff_workstation/overridetree.cb b/src/mainboard/hp/snb_ivb_desktops/variants/z220_sff_workstation/overridetree.cb index 4684b0e..8340489 100644 --- a/src/mainboard/hp/snb_ivb_desktops/variants/z220_sff_workstation/overridetree.cb +++ b/src/mainboard/hp/snb_ivb_desktops/variants/z220_sff_workstation/overridetree.cb @@ -8,7 +8,6 @@ register "sata_port_map" = "0xf" register "superspeed_capable_ports" = "0x0000000f" register "xhci_switchable_ports" = "0x0000000f" - register "xhci_overcurrent_mapping" = "0x0000000f" register "usb_port_config" = "{ { 1, 0, 0 }, { 1, 0, 0 }, diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/2170p/overridetree.cb b/src/mainboard/hp/snb_ivb_laptops/variants/2170p/overridetree.cb index dfd1cce..7955ff3 100644 --- a/src/mainboard/hp/snb_ivb_laptops/variants/2170p/overridetree.cb +++ b/src/mainboard/hp/snb_ivb_laptops/variants/2170p/overridetree.cb @@ -21,7 +21,6 @@ # HDD(0), ODD(1), mSATA(2), eSATA(4) register "sata_port_map" = "0x3f" register "superspeed_capable_ports" = "0x0000000f" - register "xhci_overcurrent_mapping" = "0x00000c03" register "xhci_switchable_ports" = "0x0000000f" register "usb_port_config" = "{ {1, 1, 0}, /* SSP1: dock */ diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/2570p/overridetree.cb b/src/mainboard/hp/snb_ivb_laptops/variants/2570p/overridetree.cb index ab6529e..735e4f3 100644 --- a/src/mainboard/hp/snb_ivb_laptops/variants/2570p/overridetree.cb +++ b/src/mainboard/hp/snb_ivb_laptops/variants/2570p/overridetree.cb @@ -20,7 +20,6 @@ register "pcie_hotplug_map" = "{ 0, 1, 1, 0, 0, 0, 0, 0 }" register "sata_port_map" = "0x33" register "superspeed_capable_ports" = "0x0000000f" - register "xhci_overcurrent_mapping" = "0x00000c03" register "xhci_switchable_ports" = "0x0000000f" register "usb_port_config" = "{ {1, 1, 0}, diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/8470p/overridetree.cb b/src/mainboard/hp/snb_ivb_laptops/variants/8470p/overridetree.cb index b3cc3a9..c6bc747 100644 --- a/src/mainboard/hp/snb_ivb_laptops/variants/8470p/overridetree.cb +++ b/src/mainboard/hp/snb_ivb_laptops/variants/8470p/overridetree.cb @@ -21,7 +21,6 @@ # HDD(0), ODD(1), mSATA(2), eSATA(4) register "sata_port_map" = "0x3f" register "superspeed_capable_ports" = "0x0000000f" - register "xhci_overcurrent_mapping" = "0x00000c03" register "xhci_switchable_ports" = "0x0000000f" register "usb_port_config" = "{ { 1, 1, 0 }, diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/8770w/overridetree.cb b/src/mainboard/hp/snb_ivb_laptops/variants/8770w/overridetree.cb index 771cda0..7bd932c 100644 --- a/src/mainboard/hp/snb_ivb_laptops/variants/8770w/overridetree.cb +++ b/src/mainboard/hp/snb_ivb_laptops/variants/8770w/overridetree.cb @@ -22,7 +22,6 @@ register "pcie_hotplug_map" = "{ 0, 1, 1, 0, 0, 0, 0, 0 }" register "sata_port_map" = "0x1f" register "superspeed_capable_ports" = "0x0000000f" - register "xhci_overcurrent_mapping" = "0x00000c03" register "xhci_switchable_ports" = "0x0000000f" register "usb_port_config" = "{ {1, 1, 0}, /* Dock USB3.0 */ diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/folio_9470m/overridetree.cb b/src/mainboard/hp/snb_ivb_laptops/variants/folio_9470m/overridetree.cb index c16634d..a91da32 100644 --- a/src/mainboard/hp/snb_ivb_laptops/variants/folio_9470m/overridetree.cb +++ b/src/mainboard/hp/snb_ivb_laptops/variants/folio_9470m/overridetree.cb @@ -20,7 +20,6 @@ register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }" register "sata_port_map" = "0x3" register "superspeed_capable_ports" = "0x0000000f" - register "xhci_overcurrent_mapping" = "0x00000c03" register "xhci_switchable_ports" = "0x0000000f" register "usb_port_config" = "{ {1, 1, 0}, /* SSP1: dock */ diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/revolve_810_g1/overridetree.cb b/src/mainboard/hp/snb_ivb_laptops/variants/revolve_810_g1/overridetree.cb index 45a3c3e..772a6aa 100644 --- a/src/mainboard/hp/snb_ivb_laptops/variants/revolve_810_g1/overridetree.cb +++ b/src/mainboard/hp/snb_ivb_laptops/variants/revolve_810_g1/overridetree.cb @@ -20,7 +20,6 @@ register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }" register "sata_port_map" = "0x1" register "superspeed_capable_ports" = "0x0000000f" - register "xhci_overcurrent_mapping" = "0x00000c03" register "xhci_switchable_ports" = "0x0000000f" register "usb_port_config" = "{ { 1, 1, 0 }, diff --git a/src/mainboard/lenovo/s230u/devicetree.cb b/src/mainboard/lenovo/s230u/devicetree.cb index eb832be..21373e5 100644 --- a/src/mainboard/lenovo/s230u/devicetree.cb +++ b/src/mainboard/lenovo/s230u/devicetree.cb @@ -32,7 +32,6 @@ register "sata_interface_speed_support" = "0x3" register "sata_port_map" = "0x5" register "superspeed_capable_ports" = "0x0000000f" - register "xhci_overcurrent_mapping" = "0x00000c03" register "xhci_switchable_ports" = "0x0000000f" register "usb_port_config" = "{ { 1, 1, 0 }, diff --git a/src/mainboard/lenovo/t430/devicetree.cb b/src/mainboard/lenovo/t430/devicetree.cb index f0f7975..b40bf63 100644 --- a/src/mainboard/lenovo/t430/devicetree.cb +++ b/src/mainboard/lenovo/t430/devicetree.cb @@ -34,7 +34,6 @@ # Do not enable xHCI Port 4 since WWAN USB is EHCI-only register "superspeed_capable_ports" = "0x7" register "xhci_switchable_ports" = "0x7" - register "xhci_overcurrent_mapping" = "0x04000201" register "usb_port_config" = "{ { 1, 1, 0 }, { 1, 1, 1 }, diff --git a/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb b/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb index 4abc9c0..84611d0 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb +++ b/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb @@ -42,7 +42,6 @@ register "xhci_switchable_ports" = "0xf" register "superspeed_capable_ports" = "0xf" - register "xhci_overcurrent_mapping" = "0x4000201" register "usb_port_config" = "{ {0, 3, 0 }, /* P00 disconnected */ {1, 1, 1 }, /* P01 left or right */ diff --git a/src/mainboard/roda/rv11/variants/rv11/devicetree.cb b/src/mainboard/roda/rv11/variants/rv11/devicetree.cb index 9f37526..2fa7137 100644 --- a/src/mainboard/roda/rv11/variants/rv11/devicetree.cb +++ b/src/mainboard/roda/rv11/variants/rv11/devicetree.cb @@ -53,7 +53,6 @@ register "pcie_port_coalesce" = "false" register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }" - register "xhci_overcurrent_mapping" = "0x00080401" register "xhci_switchable_ports" = "0x0f" register "superspeed_capable_ports" = "0x0f" register "usb_port_config" = "{ diff --git a/src/mainboard/roda/rv11/variants/rw11/devicetree.cb b/src/mainboard/roda/rv11/variants/rw11/devicetree.cb index 5c3c72b..dadde9f 100644 --- a/src/mainboard/roda/rv11/variants/rw11/devicetree.cb +++ b/src/mainboard/roda/rv11/variants/rw11/devicetree.cb @@ -58,7 +58,6 @@ register "pcie_port_coalesce" = "false" register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 1, 1 }" - register "xhci_overcurrent_mapping" = "0x00000c03" register "xhci_switchable_ports" = "0x0f" register "superspeed_capable_ports" = "0x0f" register "usb_port_config" = "{ diff --git a/src/mainboard/supermicro/x9sae/devicetree.cb b/src/mainboard/supermicro/x9sae/devicetree.cb index acaae83..0284c21 100644 --- a/src/mainboard/supermicro/x9sae/devicetree.cb +++ b/src/mainboard/supermicro/x9sae/devicetree.cb @@ -24,7 +24,6 @@ register "spi_lvscc" = "0x2005" register "spi_uvscc" = "0x2005" register "superspeed_capable_ports" = "0x0000000f" - register "xhci_overcurrent_mapping" = "0x00000c03" register "xhci_switchable_ports" = "0x0000000f" register "usb_port_config" = "{ { 1, 0, 0 }, -- To view, visit https://review.coreboot.org/c/coreboot/+/85923?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I36944e2f2ed265ee492019b75b7dd8b95ca26dbb Gerrit-Change-Number: 85923 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Kevin Keijzer <kevin(a)quietlife.nl> Gerrit-Attention: Kevin Keijzer <kevin(a)quietlife.nl> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu>

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coreboot-gerrit January 2025