coreboot-gerrit January 2025

coreboot-gerrit@coreboot.org

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[XS] Change in coreboot[main]: soc/mediatek/common/dp: Fix `mask` data type in mtk_dp_write_byte
by Yu-Ping Wu (Code Review) 09 Jan '25

09 Jan '25

Attention is currently required from: Hung-Te Lin, Yidi Lin. Yu-Ping Wu has posted comments on this change by Yidi Lin. ( https://review.coreboot.org/c/coreboot/+/85917?usp=email ) Change subject: soc/mediatek/common/dp: Fix `mask` data type in mtk_dp_write_byte ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85917?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2762d6ca024d60663f6dae0db62a959a191adc02 Gerrit-Change-Number: 85917 Gerrit-PatchSet: 1 Gerrit-Owner: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Fri, 10 Jan 2025 01:19:30 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: soc/mediatek/common/dp: Add read/write APIs for DP Phy register
by Yu-Ping Wu (Code Review) 09 Jan '25

09 Jan '25

Attention is currently required from: Hung-Te Lin, Yidi Lin. Yu-Ping Wu has posted comments on this change by Yidi Lin. ( https://review.coreboot.org/c/coreboot/+/85914?usp=email ) Change subject: soc/mediatek/common/dp: Add read/write APIs for DP Phy register ...................................................................... Patch Set 1: (1 comment) File src/soc/mediatek/common/dp/dptx_hal_common.c: https://review.coreboot.org/c/coreboot/+/85914/comment/f9ce26d2_ef221b85?us… : PS1, Line 120: /* : * TODO: modify to clrsetbits32(addr, mask, val); : * There is asserion error when testing assert((val & mask) == val). : */ > Since this is newly added code, could you find where the bug is? We may add `assert(val & mask == va […] I checked all the `mtk_dp_phy_mask` callers, and think the assertion is always valid. `swing_val` and `pre_emphasis` are both 2-bit values, and the masks are set correctly. -- To view, visit https://review.coreboot.org/c/coreboot/+/85914?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5c00d0aa7e35f03cc3c3aef6a58eadd3d334d8ed Gerrit-Change-Number: 85914 Gerrit-PatchSet: 1 Gerrit-Owner: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Fri, 10 Jan 2025 01:18:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com>

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[L] Change in coreboot[main]: mb/asrock: Add Z87 Extreme3 (Haswell)
by Felix Singer (Code Review) 09 Jan '25

09 Jan '25

Attention is currently required from: Angel Pons, Jan Philipp Groß, Keith Hui, Máté Kukri, Nicholas Chin. Felix Singer has posted comments on this change by Jan Philipp Groß. ( https://review.coreboot.org/c/coreboot/+/85926?usp=email ) Change subject: mb/asrock: Add Z87 Extreme3 (Haswell) ...................................................................... Patch Set 1: (2 comments) File src/mainboard/asrock/z87_extreme3/devicetree.cb: https://review.coreboot.org/c/coreboot/+/85926/comment/2aa615cf_8279113f?us… : PS1, Line 15: pci 00.0 > Please use device aliases and remove superfluous comments Never mind. Haswell does not have aliases yet. File src/mainboard/asrock/z87_extreme3/romstage.c: https://review.coreboot.org/c/coreboot/+/85926/comment/ea73bf5f_65e89b0e?us… : PS1, Line 10: : /* FIXME: called after romstage_common, remove it if not used */ : void mb_late_romstage_setup(void) : { : } remove? -- To view, visit https://review.coreboot.org/c/coreboot/+/85926?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3c13c068d899588eda80b9957127bcb6ccf8bab0 Gerrit-Change-Number: 85926 Gerrit-PatchSet: 1 Gerrit-Owner: Jan Philipp Groß <jeangrande(a)mailbox.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Máté Kukri <km(a)mkukri.xyz> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Keith Hui <buurin(a)gmail.com> Gerrit-Attention: Máté Kukri <km(a)mkukri.xyz> Gerrit-Attention: Jan Philipp Groß <jeangrande(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Fri, 10 Jan 2025 01:16:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <service+coreboot-gerrit(a)felixsinger.de>

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[M] Change in coreboot[main]: soc/mediatek/common/dp: Add read/write APIs for DP Phy register
by Yu-Ping Wu (Code Review) 09 Jan '25

09 Jan '25

Attention is currently required from: Hung-Te Lin, Yidi Lin. Yu-Ping Wu has posted comments on this change by Yidi Lin. ( https://review.coreboot.org/c/coreboot/+/85914?usp=email ) Change subject: soc/mediatek/common/dp: Add read/write APIs for DP Phy register ...................................................................... Patch Set 1: (3 comments) File src/soc/mediatek/common/dp/dptx_hal_common.c: https://review.coreboot.org/c/coreboot/+/85914/comment/bcf9b505_1d3afbd6?us… : PS1, Line 73: if (!mtk_dp->phy_regs) { Same here. Use an assertion. https://review.coreboot.org/c/coreboot/+/85914/comment/6a0a44c0_c9fafc8e?us… : PS1, Line 78: if (offset % 4 != 0 || offset > REG_OFFSET_LIMIT) { : printk(BIOS_ERR, "[%s] invalid offset %#x for reg %p\n", : __func__, offset, mtk_dp->regs); : return 0; : } Although existing code is also written this way, I think this should be assertions (instead of run-time errors). Since this is the newly added code for mt8196, can we start using assertions? We may fix `mtk_dp_mask` and other functions in a separate patch. https://review.coreboot.org/c/coreboot/+/85914/comment/7354f221_6d20eb2b?us… : PS1, Line 120: /* : * TODO: modify to clrsetbits32(addr, mask, val); : * There is asserion error when testing assert((val & mask) == val). : */ Since this is newly added code, could you find where the bug is? We may add `assert(val & mask == val)` here. -- To view, visit https://review.coreboot.org/c/coreboot/+/85914?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5c00d0aa7e35f03cc3c3aef6a58eadd3d334d8ed Gerrit-Change-Number: 85914 Gerrit-PatchSet: 1 Gerrit-Owner: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Fri, 10 Jan 2025 01:10:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[L] Change in coreboot[main]: mb/asrock: Add Z87 Extreme3 (Haswell)
by Felix Singer (Code Review) 09 Jan '25

09 Jan '25

Attention is currently required from: Angel Pons, Jan Philipp Groß, Keith Hui, Máté Kukri, Nicholas Chin. Felix Singer has posted comments on this change by Jan Philipp Groß. ( https://review.coreboot.org/c/coreboot/+/85926?usp=email ) Change subject: mb/asrock: Add Z87 Extreme3 (Haswell) ...................................................................... Patch Set 1: Code-Review+1 (3 comments) File src/mainboard/asrock/z87_extreme3/devicetree.cb: https://review.coreboot.org/c/coreboot/+/85926/comment/e3fcc128_4e7fcac9?us… : PS1, Line 15: pci 00.0 Please use device aliases and remove superfluous comments File src/mainboard/asrock/z87_extreme3/dsdt.asl: https://review.coreboot.org/c/coreboot/+/85926/comment/b606f71d_127cb859?us… : PS1, Line 18: /* global NVS and variables. */ Remove superfluous comment File src/mainboard/asrock/z87_extreme3/hda_verb.c: https://review.coreboot.org/c/coreboot/+/85926/comment/f051efd2_e39f0018?us… : PS1, Line 24: remove blank line -- To view, visit https://review.coreboot.org/c/coreboot/+/85926?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3c13c068d899588eda80b9957127bcb6ccf8bab0 Gerrit-Change-Number: 85926 Gerrit-PatchSet: 1 Gerrit-Owner: Jan Philipp Groß <jeangrande(a)mailbox.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Máté Kukri <km(a)mkukri.xyz> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Keith Hui <buurin(a)gmail.com> Gerrit-Attention: Máté Kukri <km(a)mkukri.xyz> Gerrit-Attention: Jan Philipp Groß <jeangrande(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Fri, 10 Jan 2025 01:09:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: soc/mediatek/mt8186/rtc: Remove unused variable "sw"
by Yidi Lin (Code Review) 09 Jan '25

09 Jan '25

Attention is currently required from: Hung-Te Lin, Yu-Ping Wu. Yidi Lin has posted comments on this change by Yu-Ping Wu. ( https://review.coreboot.org/c/coreboot/+/85921?usp=email ) Change subject: soc/mediatek/mt8186/rtc: Remove unused variable "sw" ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85921?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7e282b6ce881f4e8f9d5e1c92803fda363fe28d7 Gerrit-Change-Number: 85921 Gerrit-PatchSet: 2 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Fri, 10 Jan 2025 00:03:52 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: sb/intel/bd82x6x: Apply EHCI mapping to xhci_overcurrent_mapping
by Elyes Haouas (Code Review) 09 Jan '25

09 Jan '25

Attention is currently required from: Keith Hui. Elyes Haouas has posted comments on this change by Keith Hui. ( https://review.coreboot.org/c/coreboot/+/85922?usp=email ) Change subject: sb/intel/bd82x6x: Apply EHCI mapping to xhci_overcurrent_mapping ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/85922?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iab30a07c8df223e4053c5f28df5e5ed926f278f7 Gerrit-Change-Number: 85922 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Keith Hui <buurin(a)gmail.com> Gerrit-Comment-Date: Thu, 09 Jan 2025 23:35:48 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[L] Change in coreboot[main]: mb/asrock: Add Z87 Extreme4 (Haswell)
by Jan Philipp Groß (Code Review) 09 Jan '25

09 Jan '25

Attention is currently required from: Angel Pons, Nicholas Chin. Hello Angel Pons, Nicholas Chin, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84672?usp=email to look at the new patch set (#8). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: mb/asrock: Add Z87 Extreme4 (Haswell) ...................................................................... mb/asrock: Add Z87 Extreme4 (Haswell) This port was done via autoport and subsequent manual tweaking. The board features two socketed DIP-8 SPI flash chips, as well as a BIOS selection via jumper and onboard Power and Reset switches. Working: - Haswell MRC.bin - All four DDR3/DDR3L DIMM slots - HDMI-Out Port - DVI-D Port - RJ-45 Gigabit LAN Port - Both USB 2.0 Ports - All four USB 3.1 Gen1 Ports - All three USB 2.0 headers - Both USB 3.1 Gen1 headers - Vertical Type A USB 3.1 Gen1 (located next to RAM slots and PCH) - All six SATA3 6.0 Gb/s connectors by Intel - All three PCI Express 3.0 x16 slots (tested with NV 1080 Ti dGPU) - Both PCI Express 2.0 x1 slots (tested with TL-WDN4800 WiFi adapter) - HD Audio Jack (Audio output tested only) - Front Audio Jack (Audio output tested only) not (yet) working: - both SATA3 6.0 Gb/s connectors by ASMedia ASM1061 (fix will soon be merged) - Dr. Debug (POST display) - Various LEDs (mostly cosmetical, one however indicates which flash chip is currently being booted from) not (yet) tested: - IR header - COM Port header - DisplayPort - eSATA connector - PS/2 Mouse/Keyboard Port - HDMI-In Port - PCI slots Change-Id: I78791aa9877a3ad79bf8b896c583fedf37e96d9a Signed-off-by: Jan Philipp Groß <jeangrande(a)mailbox.org> --- A src/mainboard/asrock/z87_extreme4/Kconfig A src/mainboard/asrock/z87_extreme4/Kconfig.name A src/mainboard/asrock/z87_extreme4/Makefile.mk A src/mainboard/asrock/z87_extreme4/acpi/ec.asl A src/mainboard/asrock/z87_extreme4/acpi/platform.asl A src/mainboard/asrock/z87_extreme4/acpi/superio.asl A src/mainboard/asrock/z87_extreme4/board_info.txt A src/mainboard/asrock/z87_extreme4/bootblock.c A src/mainboard/asrock/z87_extreme4/data.vbt A src/mainboard/asrock/z87_extreme4/devicetree.cb A src/mainboard/asrock/z87_extreme4/dsdt.asl A src/mainboard/asrock/z87_extreme4/gma-mainboard.ads A src/mainboard/asrock/z87_extreme4/gpio.c A src/mainboard/asrock/z87_extreme4/hda_verb.c A src/mainboard/asrock/z87_extreme4/romstage.c 15 files changed, 538 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/84672/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/84672?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I78791aa9877a3ad79bf8b896c583fedf37e96d9a Gerrit-Change-Number: 84672 Gerrit-PatchSet: 8 Gerrit-Owner: Jan Philipp Groß <jeangrande(a)mailbox.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com>

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[M] Change in coreboot[main]: soc/intel/pantherlake: Add core scaling factors read support
by Jérémy Compostella (Code Review) 09 Jan '25

09 Jan '25

Jérémy Compostella has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/85554?usp=email ) Change subject: soc/intel/pantherlake: Add core scaling factors read support ...................................................................... Patch Set 11: (2 comments) Patchset: PS11: > > Initially, I shared similar concerns when assigned this task. […] This CL utilizes a BIOS mailbox command, a low-level interface not accessible by the Operating System. I believe it should be the responsibility of the IA firmware to provide an accurate hardware description, including performance and efficiency scaling factors. However, I acknowledge that the OS should not rely on BIOS for hardware initialization tasks that fall under the purview of OS device drivers. File src/soc/intel/common/block/acpi/cpu_hybrid.c: https://review.coreboot.org/c/coreboot/+/85554/comment/fc588146_83a86b43?us… : PS11, Line 18: enum cpu_perf_eff_type { : CPU_TYPE_EFF, : CPU_TYPE_PERF, : }; > It is, unfortunately, a bit late to take such a comment into account. Closing as there is nothing we can do about it except reverting the whole thing and redoing the CLs but it seems overkill. -- To view, visit https://review.coreboot.org/c/coreboot/+/85554?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7a8e1e66a02e4bf6b1a41277e83c6dec786fe169 Gerrit-Change-Number: 85554 Gerrit-PatchSet: 11 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Zhixing Ma <zhixing.ma(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Comment-Date: Thu, 09 Jan 2025 21:27:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com>

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[L] Change in coreboot[main]: mb/asrock: Add Z87 Extreme3 (Haswell)
by Jan Philipp Groß (Code Review) 09 Jan '25

09 Jan '25

Attention is currently required from: Angel Pons, Keith Hui, Máté Kukri, Nicholas Chin. Jan Philipp Groß has posted comments on this change by Jan Philipp Groß. ( https://review.coreboot.org/c/coreboot/+/85926?usp=email ) Change subject: mb/asrock: Add Z87 Extreme3 (Haswell) ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: Hey guys, another Z87 board from ASRock, ported to the best of my abilities. Feel free to have a look at it if you got the spare time! Best regards -- To view, visit https://review.coreboot.org/c/coreboot/+/85926?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3c13c068d899588eda80b9957127bcb6ccf8bab0 Gerrit-Change-Number: 85926 Gerrit-PatchSet: 1 Gerrit-Owner: Jan Philipp Groß <jeangrande(a)mailbox.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Máté Kukri <km(a)mkukri.xyz> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Attention: Keith Hui <buurin(a)gmail.com> Gerrit-Attention: Máté Kukri <km(a)mkukri.xyz> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Thu, 09 Jan 2025 21:05:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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coreboot-gerrit January 2025