coreboot-gerrit January 2025

coreboot-gerrit@coreboot.org

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[XS] Change in coreboot[main]: sb/intel/bd82x6x: Apply EHCI mapping to xhci_overcurrent_mapping
by Keith Hui (Code Review) 09 Jan '25

09 Jan '25

Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85922?usp=email ) Change subject: sb/intel/bd82x6x: Apply EHCI mapping to xhci_overcurrent_mapping ...................................................................... sb/intel/bd82x6x: Apply EHCI mapping to xhci_overcurrent_mapping As xHCI ports 1-4 and OC pins 0-3 are all shared with EHCI, xhci_overcurrent_mapping should never deviate from the USB 2 (EHCI) overcurrent mapping specified in the USB port config in the devicetree. Get the mapping from EHCI and free mainboards from specifying it separately. A Ghidra inspection of MRC binary indicates it is doing the same. After this patch xhci_overcurrent_mapping becomes redundant and will be removed in a follow-up. Change-Id: Iab30a07c8df223e4053c5f28df5e5ed926f278f7 Signed-off-by: Keith Hui <buurin(a)gmail.com> --- M src/southbridge/intel/bd82x6x/usb_xhci.c 1 file changed, 3 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/85922/1 diff --git a/src/southbridge/intel/bd82x6x/usb_xhci.c b/src/southbridge/intel/bd82x6x/usb_xhci.c index f71a505..358d107 100644 --- a/src/southbridge/intel/bd82x6x/usb_xhci.c +++ b/src/southbridge/intel/bd82x6x/usb_xhci.c @@ -7,6 +7,7 @@ #include "pch.h" #include <device/pci_ehci.h> #include <device/pci_ops.h> +#include <southbridge/intel/common/rcba.h> #include "chip.h" static void usb_xhci_init(struct device *dev) @@ -16,8 +17,8 @@ printk(BIOS_DEBUG, "XHCI: Setting up controller.. "); - if (config->xhci_overcurrent_mapping) - pci_write_config32(dev, XOCM, config->xhci_overcurrent_mapping); + reg32 = RCBA32(USBOCM1) & 0x0f0f0f0f; + pci_write_config32(dev, XOCM, reg32); /* lock overcurrent map */ pci_or_config32(dev, 0x44, 1); -- To view, visit https://review.coreboot.org/c/coreboot/+/85922?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iab30a07c8df223e4053c5f28df5e5ed926f278f7 Gerrit-Change-Number: 85922 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com>

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[XS] Change in coreboot[main]: mb/google/fatcat: Enable SAGv
by Bora Guvendik (Code Review) 09 Jan '25

09 Jan '25

Attention is currently required from: Pranava Y N, Subrata Banik. Bora Guvendik has posted comments on this change by Bora Guvendik. ( https://review.coreboot.org/c/coreboot/+/85272?usp=email ) Change subject: mb/google/fatcat: Enable SAGv ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: > I am seeing a boot time regression of 55ms w/ this CL. @bora.guvendik@intel. […] sure, created partner bug: 388768865 for boot time regression -- To view, visit https://review.coreboot.org/c/coreboot/+/85272?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I340f4951fd33deadaac53edd30e2cf6bfc2a750b Gerrit-Change-Number: 85272 Gerrit-PatchSet: 2 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Thu, 09 Jan 2025 18:11:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Pranava Y N <pranavayn(a)google.com>

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[XS] Change in coreboot[main]: ec/google/chromeec: Enable ACPI memory mapping for Microchip EC
by Jérémy Compostella (Code Review) 09 Jan '25

09 Jan '25

Jérémy Compostella has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85886?usp=email ) Change subject: ec/google/chromeec: Enable ACPI memory mapping for Microchip EC ...................................................................... ec/google/chromeec: Enable ACPI memory mapping for Microchip EC This commit introduces an automatic linkage between the Microchip EC (EC_GOOGLE_CHROMEEC_MEC) and ACPI memory mapping (EC_GOOGLE_CHROMEEC_ACPI_MEMMAP) options. This linkage is enabled when the Microchip EC is selected. Certain data registers in Microchip ECs cannot be accessed via I/O space. Instead, an indirection mechanism is required for register access. When using such an EC, coreboot must publish ACPI information to access these data registers through ACPI data ports 66h/62h. Analysis of the coreboot codebase has revealed that the EC_GOOGLE_CHROMEEC_MEC and EC_GOOGLE_CHROMEEC_ACPI_MEMMAP options are consistently used together. This commit streamlines this dependency by linking the two options. TEST=/sys/class/power_supply/BAT0/* reports consistent values on fatcat board. Change-Id: Ib4120a6d0ba2f4785e8b07b33943010e58bcbdd3 Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85886 Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Caveh Jalali <caveh(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/ec/google/chromeec/Kconfig M src/mainboard/google/cyan/Kconfig M src/mainboard/google/fatcat/Kconfig M src/mainboard/google/glados/Kconfig M src/mainboard/intel/adlrvp/Kconfig M src/mainboard/intel/kunimitsu/Kconfig M src/mainboard/intel/strago/Kconfig 7 files changed, 1 insertion(+), 7 deletions(-) Approvals: Caveh Jalali: Looks good to me, approved Subrata Banik: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/ec/google/chromeec/Kconfig b/src/ec/google/chromeec/Kconfig index cf3dc9f..a56565c 100644 --- a/src/ec/google/chromeec/Kconfig +++ b/src/ec/google/chromeec/Kconfig @@ -93,6 +93,7 @@ config EC_GOOGLE_CHROMEEC_MEC depends on EC_GOOGLE_CHROMEEC_LPC def_bool n + select EC_GOOGLE_CHROMEEC_ACPI_MEMMAP select EC_GOOGLE_COMMON_MEC help Microchip EC variant for LPC register access. diff --git a/src/mainboard/google/cyan/Kconfig b/src/mainboard/google/cyan/Kconfig index 37832de..2bb6b92 100644 --- a/src/mainboard/google/cyan/Kconfig +++ b/src/mainboard/google/cyan/Kconfig @@ -5,7 +5,6 @@ select ACPI_GNVS_USB_CHARGECTL select BOARD_ROMSIZE_KB_8192 select EC_GOOGLE_CHROMEEC - select EC_GOOGLE_CHROMEEC_ACPI_MEMMAP select EC_GOOGLE_CHROMEEC_BOARDID select EC_GOOGLE_CHROMEEC_LPC select EC_GOOGLE_CHROMEEC_MEC diff --git a/src/mainboard/google/fatcat/Kconfig b/src/mainboard/google/fatcat/Kconfig index 3061004..37ba330 100644 --- a/src/mainboard/google/fatcat/Kconfig +++ b/src/mainboard/google/fatcat/Kconfig @@ -61,13 +61,11 @@ config BOARD_GOOGLE_FATCAT select BOARD_GOOGLE_MODEL_FATCAT - select EC_GOOGLE_CHROMEEC_ACPI_MEMMAP select EC_GOOGLE_CHROMEEC_MEC select MAINBOARD_USES_IFD_EC_REGION config BOARD_GOOGLE_FATCATISH select BOARD_GOOGLE_MODEL_FATCAT - select EC_GOOGLE_CHROMEEC_ACPI_MEMMAP select EC_GOOGLE_CHROMEEC_MEC select MAINBOARD_USES_IFD_EC_REGION diff --git a/src/mainboard/google/glados/Kconfig b/src/mainboard/google/glados/Kconfig index 0bea9e7..57d54d0 100644 --- a/src/mainboard/google/glados/Kconfig +++ b/src/mainboard/google/glados/Kconfig @@ -6,7 +6,6 @@ select DRIVERS_I2C_GENERIC select DRIVERS_I2C_NAU8825 select EC_GOOGLE_CHROMEEC - select EC_GOOGLE_CHROMEEC_ACPI_MEMMAP select EC_GOOGLE_CHROMEEC_BOARDID select EC_GOOGLE_CHROMEEC_LPC select EC_GOOGLE_CHROMEEC_MEC diff --git a/src/mainboard/intel/adlrvp/Kconfig b/src/mainboard/intel/adlrvp/Kconfig index 279a8f9..db5e2d9 100644 --- a/src/mainboard/intel/adlrvp/Kconfig +++ b/src/mainboard/intel/adlrvp/Kconfig @@ -60,7 +60,6 @@ select BOARD_INTEL_ADLRVP_COMMON select DRIVERS_INTEL_MIPI_CAMERA select DRIVERS_INTEL_PMC - select EC_GOOGLE_CHROMEEC_ACPI_MEMMAP select EC_GOOGLE_CHROMEEC_MEC select INTEL_LPSS_UART_FOR_CONSOLE select SOC_INTEL_ALDERLAKE_PCH_P diff --git a/src/mainboard/intel/kunimitsu/Kconfig b/src/mainboard/intel/kunimitsu/Kconfig index e2a16fc..0a84d36 100644 --- a/src/mainboard/intel/kunimitsu/Kconfig +++ b/src/mainboard/intel/kunimitsu/Kconfig @@ -9,7 +9,6 @@ select DRIVERS_I2C_GENERIC select DRIVERS_I2C_NAU8825 select EC_GOOGLE_CHROMEEC - select EC_GOOGLE_CHROMEEC_ACPI_MEMMAP select EC_GOOGLE_CHROMEEC_BOARDID select EC_GOOGLE_CHROMEEC_LPC select EC_GOOGLE_CHROMEEC_MEC diff --git a/src/mainboard/intel/strago/Kconfig b/src/mainboard/intel/strago/Kconfig index 67030e2..3cb99eb 100644 --- a/src/mainboard/intel/strago/Kconfig +++ b/src/mainboard/intel/strago/Kconfig @@ -10,7 +10,6 @@ select EC_GOOGLE_CHROMEEC_BOARDID select EC_GOOGLE_CHROMEEC_LPC select EC_GOOGLE_CHROMEEC_MEC - select EC_GOOGLE_CHROMEEC_ACPI_MEMMAP select ENABLE_BUILTIN_COM1 select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES -- To view, visit https://review.coreboot.org/c/coreboot/+/85886?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib4120a6d0ba2f4785e8b07b33943010e58bcbdd3 Gerrit-Change-Number: 85886 Gerrit-PatchSet: 3 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: mb/google/fatcat: Enable EC ACPI memmap for Microchip EC
by Jérémy Compostella (Code Review) 09 Jan '25

09 Jan '25

Jérémy Compostella has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85874?usp=email ) Change subject: mb/google/fatcat: Enable EC ACPI memmap for Microchip EC ...................................................................... mb/google/fatcat: Enable EC ACPI memmap for Microchip EC This commit enables ACPI memory mapping for fatcat boards featuring a Microchip Embedded Controller (EC). This allows the operating system to access and read various information from the EC. The Microchip EC does not directly map these registers to I/O space, necessitating the use of an indirection mechanism for register access. TEST=/sys/class/power_supply/BAT0/* reports consistent values Change-Id: I6fb1c2ab1418a9d7afaff07404e0a3dcba1d0eba Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85874 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> --- M src/mainboard/google/fatcat/Kconfig 1 file changed, 2 insertions(+), 0 deletions(-) Approvals: Subrata Banik: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/google/fatcat/Kconfig b/src/mainboard/google/fatcat/Kconfig index 37ba330..3061004 100644 --- a/src/mainboard/google/fatcat/Kconfig +++ b/src/mainboard/google/fatcat/Kconfig @@ -61,11 +61,13 @@ config BOARD_GOOGLE_FATCAT select BOARD_GOOGLE_MODEL_FATCAT + select EC_GOOGLE_CHROMEEC_ACPI_MEMMAP select EC_GOOGLE_CHROMEEC_MEC select MAINBOARD_USES_IFD_EC_REGION config BOARD_GOOGLE_FATCATISH select BOARD_GOOGLE_MODEL_FATCAT + select EC_GOOGLE_CHROMEEC_ACPI_MEMMAP select EC_GOOGLE_CHROMEEC_MEC select MAINBOARD_USES_IFD_EC_REGION -- To view, visit https://review.coreboot.org/c/coreboot/+/85874?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6fb1c2ab1418a9d7afaff07404e0a3dcba1d0eba Gerrit-Change-Number: 85874 Gerrit-PatchSet: 3 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-CC: Cliff Huang <cliff.huang(a)intel.com> Gerrit-CC: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-CC: Zhixing Ma <zhixing.ma(a)intel.com>

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[S] Change in coreboot[main]: Makefile: Fix indentation in help_coreboot
by Felix Singer (Code Review) 09 Jan '25

09 Jan '25

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85895?usp=email ) Change subject: Makefile: Fix indentation in help_coreboot ...................................................................... Makefile: Fix indentation in help_coreboot Fix indentation to make it aesthetically more pleasing. Change-Id: I51b052e4d9d358e92c8105cc23997d6d35bc4d8d Signed-off-by: Andy <andy(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85895 Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Reviewed-by: Maximilian Brune <maximilian.brune(a)9elements.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Christian Walter <christian.walter(a)9elements.com> --- M Makefile 1 file changed, 12 insertions(+), 12 deletions(-) Approvals: Felix Singer: Looks good to me, approved Christian Walter: Looks good to me, approved build bot (Jenkins): Verified Maximilian Brune: Looks good to me, approved diff --git a/Makefile b/Makefile index 491e702..5e45e16 100644 --- a/Makefile +++ b/Makefile @@ -88,21 +88,21 @@ help_coreboot help:: @echo '*** coreboot platform targets ***' @echo ' Use "make [target] V=1" for extra build debug information' - @echo ' all - Build coreboot' - @echo ' clean - Remove coreboot build artifacts' - @echo ' distclean - Remove build artifacts and config files' - @echo ' sphinx - Build sphinx documentation for coreboot' - @echo ' sphinx-lint - Build sphinx documentation for coreboot with warnings as errors' - @echo ' filelist - Show files used in current build' - @echo ' printall - Print makefile info for debugging' - @echo ' gitconfig - Set up git to submit patches to coreboot' - @echo ' ctags / ctags-project - Make ctags file for all of coreboot or current board' + @echo ' all - Build coreboot' + @echo ' clean - Remove coreboot build artifacts' + @echo ' distclean - Remove build artifacts and config files' + @echo ' sphinx - Build sphinx documentation for coreboot' + @echo ' sphinx-lint - Build sphinx documentation for coreboot with warnings as errors' + @echo ' filelist - Show files used in current build' + @echo ' printall - Print makefile info for debugging' + @echo ' gitconfig - Set up git to submit patches to coreboot' + @echo ' ctags / ctags-project - Make ctags file for all of coreboot or current board' @echo ' cscope / cscope-project - Make cscope.out file for coreboot or current board' @echo @echo '*** site-local related targets ***' - @echo ' symlink - Create symbolic links from site-local into coreboot tree' - @echo ' clean-symlink - Remove symbolic links created by "make symlink"' - @echo ' cleanall-symlink - Remove all symbolic links in the coreboot tree' + @echo ' symlink - Create symbolic links from site-local into coreboot tree' + @echo ' clean-symlink - Remove symbolic links created by "make symlink"' + @echo ' cleanall-symlink - Remove all symbolic links in the coreboot tree' @echo # This include must come _before_ the pattern rules below! -- To view, visit https://review.coreboot.org/c/coreboot/+/85895?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I51b052e4d9d358e92c8105cc23997d6d35bc4d8d Gerrit-Change-Number: 85895 Gerrit-PatchSet: 3 Gerrit-Owner: Andy Ebrahiem <ahmet.ebrahiem(a)9elements.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: Makefile: Fix indentation in help_coreboot
by Felix Singer (Code Review) 09 Jan '25

09 Jan '25

Attention is currently required from: Andy Ebrahiem, Martin L Roth. Felix Singer has posted comments on this change by Andy Ebrahiem. ( https://review.coreboot.org/c/coreboot/+/85895?usp=email ) Change subject: Makefile: Fix indentation in help_coreboot ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85895?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I51b052e4d9d358e92c8105cc23997d6d35bc4d8d Gerrit-Change-Number: 85895 Gerrit-PatchSet: 2 Gerrit-Owner: Andy Ebrahiem <ahmet.ebrahiem(a)9elements.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Andy Ebrahiem <ahmet.ebrahiem(a)9elements.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Comment-Date: Thu, 09 Jan 2025 17:51:49 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: mb/google/fatcat: Select DRIVER_INTEL_ISH_HAS_MAIN_FW for fatcat
by Jayvik Desai (Code Review) 09 Jan '25

09 Jan '25

Attention is currently required from: Pranava Y N. Jayvik Desai has posted comments on this change by Jayvik Desai. ( https://review.coreboot.org/c/coreboot/+/85920?usp=email ) Change subject: mb/google/fatcat: Select DRIVER_INTEL_ISH_HAS_MAIN_FW for fatcat ...................................................................... Patch Set 4: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/85920/comment/16c568c2_cdd8de45?us… : PS3, Line 7: select > Select ? Acknowledged https://review.coreboot.org/c/coreboot/+/85920/comment/56bdbe08_d311a5b2?us… : PS3, Line 9: This patch selects the ISH main firmware Kconfig to prevent google/fatcat from trying to retrieve a dummy ISH SHIM firmware version, since ISH FW in google/fatcat will be part of the kernel firmware image. > looks to me a wrap up test ? should limit the commit msg < 72 char per line Acknowledged -- To view, visit https://review.coreboot.org/c/coreboot/+/85920?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id24394cb6c6dbaed13c87612da341e47eb69895f Gerrit-Change-Number: 85920 Gerrit-PatchSet: 4 Gerrit-Owner: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Thu, 09 Jan 2025 17:50:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[XS] Change in coreboot[main]: mb/google/fatcat: Select DRIVER_INTEL_ISH_HAS_MAIN_FW for fatcat
by Jayvik Desai (Code Review) 09 Jan '25

09 Jan '25

Attention is currently required from: Jayvik Desai, Pranava Y N. Hello Pranava Y N, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85920?usp=email to look at the new patch set (#5). Change subject: mb/google/fatcat: Select DRIVER_INTEL_ISH_HAS_MAIN_FW for fatcat ...................................................................... mb/google/fatcat: Select DRIVER_INTEL_ISH_HAS_MAIN_FW for fatcat This patch selects the ISH main firmware Kconfig to prevent google/fatcat from trying to retrieve a dummy ISH SHIM firmware version, since ISH FW in google/fatcat will be part of the kernel firmware image. BUG=b:370984186 TEST=Build and boot google/fatcat, config exists in coreboot.config Change-Id: Id24394cb6c6dbaed13c87612da341e47eb69895f Signed-off-by: Jayvik Desai <jayvik(a)google.com> --- M src/mainboard/google/fatcat/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/85920/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/85920?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id24394cb6c6dbaed13c87612da341e47eb69895f Gerrit-Change-Number: 85920 Gerrit-PatchSet: 5 Gerrit-Owner: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com>

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[XS] Change in coreboot[main]: mb/google/fatcat: Select DRIVER_INTEL_ISH_HAS_MAIN_FW for fatcat
by Subrata Banik (Code Review) 09 Jan '25

09 Jan '25

Attention is currently required from: Jayvik Desai, Pranava Y N. Subrata Banik has posted comments on this change by Jayvik Desai. ( https://review.coreboot.org/c/coreboot/+/85920?usp=email ) Change subject: mb/google/fatcat: Select DRIVER_INTEL_ISH_HAS_MAIN_FW for fatcat ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85920?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id24394cb6c6dbaed13c87612da341e47eb69895f Gerrit-Change-Number: 85920 Gerrit-PatchSet: 4 Gerrit-Owner: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Thu, 09 Jan 2025 17:48:15 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XL] Change in coreboot[main]: mb/starlabs/starbook: Add AlderLake-N variant
by Matt DeVillier (Code Review) 09 Jan '25

09 Jan '25

Attention is currently required from: Sean Rhodes. Matt DeVillier has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/85714?usp=email ) Change subject: mb/starlabs/starbook: Add AlderLake-N variant ...................................................................... Patch Set 10: (1 comment) File src/mainboard/starlabs/starbook/variants/adl_n/ramstage.c: https://review.coreboot.org/c/coreboot/+/85714/comment/c9c376d0_03be1f1f?us… : PS10, Line 15: remove extra final newline -- To view, visit https://review.coreboot.org/c/coreboot/+/85714?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id45e31b61046748a57c8104081f689057621bb04 Gerrit-Change-Number: 85714 Gerrit-PatchSet: 10 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Comment-Date: Thu, 09 Jan 2025 17:46:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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coreboot-gerrit January 2025