coreboot-gerrit January 2025

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[L] Change in coreboot[main]: drivers/amd/opensil/mpio: Factor out common MPIO symbols from vendorcode
by Nick Kochlowski (Code Review) 10 Jan '25

10 Jan '25

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Martin L Roth, Martin Roth, Matt DeVillier, Varshit Pandya. Nick Kochlowski has posted comments on this change by Nick Kochlowski. ( https://review.coreboot.org/c/coreboot/+/85632?usp=email ) Change subject: drivers/amd/opensil/mpio: Factor out common MPIO symbols from vendorcode ...................................................................... Patch Set 12: (1 comment) File src/drivers/amd/opensil/mpio/chip.h: https://review.coreboot.org/c/coreboot/+/85632/comment/cd7d2b45_d3938a46?us… : PS11, Line 6: #if CONFIG(OPENSIL_DRIVER) > hmm, why is this needed to get rid of this build error for the EMULATION_QEMU_X86_Q35 config which s […] The Makefile.mk in drivers/amd/opensil/mpio is being included and executed from the base Makefile.mk. The chip.c file compiled here includes the header in which the AMD_OPENSIL_MPIO_CHIP_H_FILE config option isn't defined for those builds. Added the OPENSIL_DRIVER config option as a compilation condition for chip.c as recommended, thanks. -- To view, visit https://review.coreboot.org/c/coreboot/+/85632?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8b1f92f08565216dd93203a06015e3eec1e7bb69 Gerrit-Change-Number: 85632 Gerrit-PatchSet: 12 Gerrit-Owner: Nick Kochlowski <nickkochlowski(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 10 Jan 2025 17:47:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de>

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[L] Change in coreboot[main]: drivers/amd/opensil/mpio: Factor out common MPIO symbols from vendorcode
by Nick Kochlowski (Code Review) 10 Jan '25

10 Jan '25

Attention is currently required from: Fred Reitberger, Jason Glenesk, Martin L Roth, Martin Roth, Matt DeVillier, Nick Kochlowski, Varshit Pandya. Hello Felix Held, Fred Reitberger, Jason Glenesk, Martin L Roth, Matt DeVillier, Varshit Pandya, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85632?usp=email to look at the new patch set (#12). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: drivers/amd/opensil/mpio: Factor out common MPIO symbols from vendorcode ...................................................................... drivers/amd/opensil/mpio: Factor out common MPIO symbols from vendorcode Refactor vendorcode MPIO configuration functions to be invoked from the openSIL driver. Change-Id: I8b1f92f08565216dd93203a06015e3eec1e7bb69 Signed-off-by: Nicolas Kochlowski <nickkochlowski(a)gmail.com> --- M src/drivers/amd/opensil/Makefile.mk A src/drivers/amd/opensil/mpio/Makefile.mk A src/drivers/amd/opensil/mpio/chip.c R src/drivers/amd/opensil/mpio/chip.h M src/drivers/amd/opensil/opensil.h M src/drivers/amd/opensil/ramstage.c M src/mainboard/amd/birman/devicetree_phoenix_opensil.cb M src/mainboard/amd/birman/update_devicetree_phoenix_opensil.c M src/mainboard/amd/onyx_poc/devicetree.cb M src/soc/amd/genoa_poc/chipset.cb M src/soc/amd/phoenix/chipset_opensil.cb M src/vendorcode/amd/opensil/Kconfig M src/vendorcode/amd/opensil/genoa_poc/mpio/chip.c M src/vendorcode/amd/opensil/genoa_poc/mpio/chip.h M src/vendorcode/amd/opensil/genoa_poc/ramstage.c M src/vendorcode/amd/opensil/opensil.h M src/vendorcode/amd/opensil/stub/mpio/chip.c M src/vendorcode/amd/opensil/stub/mpio/chip.h 18 files changed, 200 insertions(+), 163 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/85632/12 -- To view, visit https://review.coreboot.org/c/coreboot/+/85632?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8b1f92f08565216dd93203a06015e3eec1e7bb69 Gerrit-Change-Number: 85632 Gerrit-PatchSet: 12 Gerrit-Owner: Nick Kochlowski <nickkochlowski(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Nick Kochlowski <nickkochlowski(a)gmail.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com>

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[XS] Change in coreboot[main]: mb/google/rauru: Disable modem power
by Yidi Lin (Code Review) 10 Jan '25

10 Jan '25

Yidi Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85663?usp=email ) ( 3 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/google/rauru: Disable modem power ...................................................................... mb/google/rauru: Disable modem power BUG=b:315894234 TEST=Build pass. The actual measurement of the average power over 20 seconds decreased from 6.755W to 6.716W. Change-Id: I71bda7055afc902525501ddf7074f9b2c5550d4a Signed-off-by: Xavier Chang <xavier.chang(a)mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85663 Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Reviewed-by: Yidi Lin <yidilin(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/rauru/romstage.c 1 file changed, 2 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Yidi Lin: Looks good to me, approved Yu-Ping Wu: Looks good to me, approved diff --git a/src/mainboard/google/rauru/romstage.c b/src/mainboard/google/rauru/romstage.c index afd12c6..f4de121 100644 --- a/src/mainboard/google/rauru/romstage.c +++ b/src/mainboard/google/rauru/romstage.c @@ -3,6 +3,7 @@ #include <arch/stages.h> #include <soc/emi.h> #include <soc/irq2axi.h> +#include <soc/modem_power_ctrl.h> #include <soc/mt6316.h> #include <soc/mt6363.h> #include <soc/mt6373.h> @@ -33,6 +34,7 @@ mt6373_init(); mt6685_init(); mtk_dram_init(); + modem_power_down(); if (CONFIG(PCI)) mtk_pcie_deassert_perst(); -- To view, visit https://review.coreboot.org/c/coreboot/+/85663?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I71bda7055afc902525501ddf7074f9b2c5550d4a Gerrit-Change-Number: 85663 Gerrit-PatchSet: 5 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in coreboot[main]: soc/mediatek/mt8196: Add modem power driver to disable unused power
by Yidi Lin (Code Review) 10 Jan '25

10 Jan '25

Yidi Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85651?usp=email ) ( 6 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/mediatek/mt8196: Add modem power driver to disable unused power ...................................................................... soc/mediatek/mt8196: Add modem power driver to disable unused power Disable MT6363 unused power: vbuck5, vcn15, vrf09, vrf12, vrf13, vrf18, vsram_digrf, vsram_mdfe. Disable MT6373 unused power: vant18, vsim1, vsim2. BUG=b:315894234 TEST=Build pass, Check there are no check failed logs. And check logs: Vmodem value: 0x78 (means SPMI_SLAVE_4_750MV) Signed-off-by: Xavier Chang <xavier.chang(a)mediatek.corp-partner.google.com> Change-Id: Ia8808e3500727753e4537017b46ac8ab39d59468 Reviewed-on: https://review.coreboot.org/c/coreboot/+/85651 Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Reviewed-by: Yidi Lin <yidilin(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/mediatek/mt8196/Makefile.mk A src/soc/mediatek/mt8196/include/soc/modem_power_ctrl.h A src/soc/mediatek/mt8196/modem_power_ctrl.c 3 files changed, 112 insertions(+), 0 deletions(-) Approvals: Yu-Ping Wu: Looks good to me, approved build bot (Jenkins): Verified Yidi Lin: Looks good to me, approved diff --git a/src/soc/mediatek/mt8196/Makefile.mk b/src/soc/mediatek/mt8196/Makefile.mk index 9bb31e1..d00159d 100644 --- a/src/soc/mediatek/mt8196/Makefile.mk +++ b/src/soc/mediatek/mt8196/Makefile.mk @@ -30,6 +30,7 @@ romstage-y += ../common/emi.c romstage-y += irq2axi.c romstage-y += l2c_ops.c +romstage-y += modem_power_ctrl.c romstage-y += ../common/memory.c memory.c romstage-y += ../common/memory_test.c romstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c diff --git a/src/soc/mediatek/mt8196/include/soc/modem_power_ctrl.h b/src/soc/mediatek/mt8196/include/soc/modem_power_ctrl.h new file mode 100644 index 0000000..ac729e991 --- /dev/null +++ b/src/soc/mediatek/mt8196/include/soc/modem_power_ctrl.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ + +#ifndef SOC_MEDIATEK_MT8196_MODEM_POWER_CTRL_H +#define SOC_MEDIATEK_MT8196_MODEM_POWER_CTRL_H + +/* Power down modem */ +void modem_power_down(void); + +#endif /* SOC_MEDIATEK_MT8196_MODEM_POWER_CTRL_H */ diff --git a/src/soc/mediatek/mt8196/modem_power_ctrl.c b/src/soc/mediatek/mt8196/modem_power_ctrl.c new file mode 100644 index 0000000..0fc4653 --- /dev/null +++ b/src/soc/mediatek/mt8196/modem_power_ctrl.c @@ -0,0 +1,102 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ + +#include <console/console.h> +#include <soc/addressmap.h> +#include <soc/modem_power_ctrl.h> +#include <soc/mt6363.h> +#include <soc/mt6373.h> +#include <soc/pmif.h> +#include <soc/spm.h> +#include <soc/spmi.h> + +#define SPMI_SLAVE_4_750MV 0x78 +#define MAX_RETRY_COUNT 200 +#define VSRAM_VOSEL 0x24d +#define VMODEM_VOSEL 0x24e +#define MD1_PWR_STA_MASK BIT(0) +#define MD1_PROT_STEP1_0_MASK BIT(0) +#define PWR_ON BIT(2) +#define MD1_PROT_STEP0_0_MASK BIT(29) + +struct mtk_apifrbus_regs { + u32 sleep_protect_en_0; + u32 sleep_protect_en_0_set; + u32 sleep_protect_en_0_clr; + u32 sleep_protect_rdy_sta_0; + u32 reserved0[4]; + u32 sleep_protect_en_1; + u32 sleep_protect_en_1_set; + u32 sleep_protect_en_1_clr; + u32 sleep_protect_rdy_sta_1; +}; + +static struct mtk_apifrbus_regs *const mtk_apifrbus_reg = + (void *)IFRBUS_AO_REG_BUS_BASE; + +static void md_pmic_lowpower_set(void) +{ + mt6363_init_pmif_arb(); + /* Vmodem_vosel = 0x24e, write Vmodem 0.75V */ + mt6363_write8(VMODEM_VOSEL, SPMI_SLAVE_4_750MV); + printk(BIOS_INFO, "Vmodem value: 0x%x\n", mt6363_read8(VMODEM_VOSEL)); +} + +static void disable_pmic_ldo(void) +{ + mt6363_enable_buck5(false); + mt6363_enable_vcn15(false); + mt6363_enable_vrf09(false); + mt6363_enable_vrf12(false); + mt6363_enable_vrf13(false); + mt6363_enable_vrf18(false); + mt6363_enable_vram_digrf(false); + mt6363_enable_vram_mdfe(false); + mt6373_enable_vant18(false); + mt6373_enable_vsim1(false); + mt6373_enable_vsim2(false); +} + +static void spm_mtcmos_ctrl_md1_disable(void) +{ + write32(&mtk_apifrbus_reg->sleep_protect_en_0_set, MD1_PROT_STEP0_0_MASK); + if (!retry(MAX_RETRY_COUNT, + (read32(&mtk_apifrbus_reg->sleep_protect_rdy_sta_1) & + MD1_PROT_STEP0_0_MASK) == MD1_PROT_STEP0_0_MASK)) { + printk(BIOS_ERR, "Check MD1_PROT_STEP0 failed\n"); + } + + write32(&mtk_apifrbus_reg->sleep_protect_en_1_set, MD1_PROT_STEP1_0_MASK); + if (!retry(MAX_RETRY_COUNT, + (read32(&mtk_apifrbus_reg->sleep_protect_rdy_sta_1) & + MD1_PROT_STEP1_0_MASK) == MD1_PROT_STEP1_0_MASK)) { + printk(BIOS_ERR, "Check MD1_PROT_STEP1 failed\n"); + } + + clrbits32(&mtk_spm->md1_pwr_con, PWR_ON); + if (!retry(MAX_RETRY_COUNT, + read32(&mtk_spm->pwr_status) & MD1_PWR_STA_MASK)) { + printk(BIOS_ERR, "Check MD1_PWR_STA failed\n"); + } + + setbits32(&mtk_spm->md_buck_iso_con, 0x3); +} + +static void md_cd_topclkgen_off(void) +{ + setbits32p(CKSYS_BASE, BIT(8) | BIT(9)); +} + +void modem_power_down(void) +{ + /* step 1. drop Vmodem voltage same as Vsram voltage */ + md_pmic_lowpower_set(); + + /* step 2. disable pmic ldo */ + disable_pmic_ldo(); + + /* step 3. power off md mtcmos */ + spm_mtcmos_ctrl_md1_disable(); + + /* step 4. disable MD input 26M&32K */ + md_cd_topclkgen_off(); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/85651?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia8808e3500727753e4537017b46ac8ab39d59468 Gerrit-Change-Number: 85651 Gerrit-PatchSet: 8 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: soc/mediatek/mt8196: Add mt6363_read8 API
by Yidi Lin (Code Review) 10 Jan '25

10 Jan '25

Yidi Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85892?usp=email ) Change subject: soc/mediatek/mt8196: Add mt6363_read8 API ...................................................................... soc/mediatek/mt8196: Add mt6363_read8 API Add mt6363_read8 API for common use. BUG=b:317009620 TEST=Build pass. Change-Id: I3cca4c2e5f6c2537c9661623260b21fb6088eff9 Signed-off-by: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85892 Reviewed-by: Yidi Lin <yidilin(a)google.com> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/mediatek/common/include/soc/mt6363.h M src/soc/mediatek/common/mt6363.c 2 files changed, 11 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Yidi Lin: Looks good to me, approved Yu-Ping Wu: Looks good to me, approved diff --git a/src/soc/mediatek/common/include/soc/mt6363.h b/src/soc/mediatek/common/include/soc/mt6363.h index 4659119..7e06c24 100644 --- a/src/soc/mediatek/common/include/soc/mt6363.h +++ b/src/soc/mediatek/common/include/soc/mt6363.h @@ -109,6 +109,7 @@ void mt6363_enable_vram_mdfe(bool enable); void mt6363_init_pmif_arb(void); u16 mt6363_read16(u32 reg); +u8 mt6363_read8(u32 reg); void mt6363_write8(u32 reg, u8 reg_val); void mt6363_write_field(u32 reg, u32 val, u32 mask, u32 shift); void mt6363_init_setting(void); diff --git a/src/soc/mediatek/common/mt6363.c b/src/soc/mediatek/common/mt6363.c index b16f6b1..a618b6f 100644 --- a/src/soc/mediatek/common/mt6363.c +++ b/src/soc/mediatek/common/mt6363.c @@ -34,6 +34,16 @@ return rdata; } +u8 mt6363_read8(u32 reg) +{ + u32 rdata = 0; + + assert(pmif_arb); + pmif_arb->read(pmif_arb, SPMI_SLAVE_4, reg, &rdata); + + return (u8)rdata; +} + void mt6363_write8(u32 reg, u8 data) { assert(pmif_arb); -- To view, visit https://review.coreboot.org/c/coreboot/+/85892?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3cca4c2e5f6c2537c9661623260b21fb6088eff9 Gerrit-Change-Number: 85892 Gerrit-PatchSet: 4 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in coreboot[main]: drivers/asmedia: Add code to enable AHCI for ASM1061
by Jan Philipp Groß (Code Review) 10 Jan '25

10 Jan '25

Attention is currently required from: Angel Pons, Nicholas Chin. Jan Philipp Groß has posted comments on this change by Nicholas Chin. ( https://review.coreboot.org/c/coreboot/+/85816?usp=email ) Change subject: drivers/asmedia: Add code to enable AHCI for ASM1061 ...................................................................... Patch Set 5: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/85816?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7a1470894261c7d14fadccdcade968f87f78fe23 Gerrit-Change-Number: 85816 Gerrit-PatchSet: 5 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jan Philipp Groß <jeangrande(a)mailbox.org> Gerrit-Reviewer: Riku Viitanen <riku.viitanen(a)protonmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Fri, 10 Jan 2025 14:30:25 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[L] Change in coreboot[main]: mb/asrock: Add Z87 Extreme4 (Haswell)
by Angel Pons (Code Review) 10 Jan '25

10 Jan '25

Attention is currently required from: Jan Philipp Groß, Keith Hui, Máté Kukri, Nicholas Chin. Angel Pons has posted comments on this change by Jan Philipp Groß. ( https://review.coreboot.org/c/coreboot/+/84672?usp=email ) Change subject: mb/asrock: Add Z87 Extreme4 (Haswell) ...................................................................... Patch Set 9: Code-Review+2 (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/84672/comment/ca9d2d94_75894196?us… : PS9, Line 34: - Dr. Debug (POST display) I think vendor firmware turns this off by switching the pin functions, done through a single bit in the Super I/O's global config. https://review.coreboot.org/c/coreboot/+/84672/comment/94129203_31467e93?us… : PS9, Line 35: - Various LEDs (mostly cosmetical, one however indicates which flash : chip is currently being booted from) LED power is likely controlled by a Super I/O GPIO -- To view, visit https://review.coreboot.org/c/coreboot/+/84672?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I78791aa9877a3ad79bf8b896c583fedf37e96d9a Gerrit-Change-Number: 84672 Gerrit-PatchSet: 9 Gerrit-Owner: Jan Philipp Groß <jeangrande(a)mailbox.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Máté Kukri <km(a)mkukri.xyz> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Keith Hui <buurin(a)gmail.com> Gerrit-Attention: Máté Kukri <km(a)mkukri.xyz> Gerrit-Attention: Jan Philipp Groß <jeangrande(a)mailbox.org> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Fri, 10 Jan 2025 14:23:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[L] Change in coreboot[main]: mb/asrock: Add Z87 Extreme3 (Haswell)
by Jan Philipp Groß (Code Review) 10 Jan '25

10 Jan '25

Attention is currently required from: Angel Pons, Felix Singer, Keith Hui, Máté Kukri, Nicholas Chin. Jan Philipp Groß has posted comments on this change by Jan Philipp Groß. ( https://review.coreboot.org/c/coreboot/+/85926?usp=email ) Change subject: mb/asrock: Add Z87 Extreme3 (Haswell) ...................................................................... Patch Set 2: (3 comments) File src/mainboard/asrock/z87_extreme3/dsdt.asl: https://review.coreboot.org/c/coreboot/+/85926/comment/d6c5e4a6_35b140c3?us… : PS1, Line 18: /* global NVS and variables. */ > Remove superfluous comment Done File src/mainboard/asrock/z87_extreme3/hda_verb.c: https://review.coreboot.org/c/coreboot/+/85926/comment/51a8024d_95b11c0f?us… : PS1, Line 24: > remove blank line Done File src/mainboard/asrock/z87_extreme3/romstage.c: https://review.coreboot.org/c/coreboot/+/85926/comment/6f409faa_faca1ab2?us… : PS1, Line 10: : /* FIXME: called after romstage_common, remove it if not used */ : void mb_late_romstage_setup(void) : { : } > remove? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/85926?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3c13c068d899588eda80b9957127bcb6ccf8bab0 Gerrit-Change-Number: 85926 Gerrit-PatchSet: 2 Gerrit-Owner: Jan Philipp Groß <jeangrande(a)mailbox.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Máté Kukri <km(a)mkukri.xyz> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Keith Hui <buurin(a)gmail.com> Gerrit-Attention: Máté Kukri <km(a)mkukri.xyz> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Fri, 10 Jan 2025 14:18:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <service+coreboot-gerrit(a)felixsinger.de>

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[L] Change in coreboot[main]: mb/asrock: Add Z87 Extreme3 (Haswell)
by Jan Philipp Groß (Code Review) 10 Jan '25

10 Jan '25

Attention is currently required from: Angel Pons, Felix Singer, Jan Philipp Groß, Keith Hui, Máté Kukri, Nicholas Chin. Hello Angel Pons, Felix Singer, Keith Hui, Máté Kukri, Nicholas Chin, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85926?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Code-Review+1 by Felix Singer, Verified+1 by build bot (Jenkins) Change subject: mb/asrock: Add Z87 Extreme3 (Haswell) ...................................................................... mb/asrock: Add Z87 Extreme3 (Haswell) This port was done via autoport and subsequent manual tweaking. Working: - Haswell MRC.bin - All four DDR3/DDR3L DIMM slots - S3 suspend and resume - D-Sub Port - DVI-D Port - HDMI Port - RJ-45 Gigabit LAN Port - Both rear USB 2.0 Ports - All four rear USB 3.1 Gen1 Ports - Both USB 2.0 headers - USB 3.1 Gen1 header - All six SATA3 6.0 Gb/s connectors by Intel - Both PCI Express 3.0 x16 slots (Tested with RX 550 PCIe x8 GPU) - PCI Express 2.0 x1 slots (tested with TL-WDN4800 WiFi adapter) - HD Audio Jack (Audio output tested only) - Front Audio Jack (Audio output tested only) not (yet) working: - The PCI Express 3.0 x16 only runs at x8 speed. not (yet) tested: - PCI slots - IR header - COM Port header - eSATA connector - PS/2 Mouse/Keyboard Port - Optical SPDIF Out Port Change-Id: I3c13c068d899588eda80b9957127bcb6ccf8bab0 Signed-off-by: Jan Philipp Groß <jeangrande(a)mailbox.org> --- A src/mainboard/asrock/z87_extreme3/Kconfig A src/mainboard/asrock/z87_extreme3/Kconfig.name A src/mainboard/asrock/z87_extreme3/Makefile.mk A src/mainboard/asrock/z87_extreme3/acpi/ec.asl A src/mainboard/asrock/z87_extreme3/acpi/platform.asl A src/mainboard/asrock/z87_extreme3/acpi/superio.asl A src/mainboard/asrock/z87_extreme3/board_info.txt A src/mainboard/asrock/z87_extreme3/bootblock.c A src/mainboard/asrock/z87_extreme3/data.vbt A src/mainboard/asrock/z87_extreme3/devicetree.cb A src/mainboard/asrock/z87_extreme3/dsdt.asl A src/mainboard/asrock/z87_extreme3/gma-mainboard.ads A src/mainboard/asrock/z87_extreme3/gpio.c A src/mainboard/asrock/z87_extreme3/hda_verb.c A src/mainboard/asrock/z87_extreme3/romstage.c 15 files changed, 528 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/85926/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85926?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3c13c068d899588eda80b9957127bcb6ccf8bab0 Gerrit-Change-Number: 85926 Gerrit-PatchSet: 2 Gerrit-Owner: Jan Philipp Groß <jeangrande(a)mailbox.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Máté Kukri <km(a)mkukri.xyz> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Keith Hui <buurin(a)gmail.com> Gerrit-Attention: Máté Kukri <km(a)mkukri.xyz> Gerrit-Attention: Jan Philipp Groß <jeangrande(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com>

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[L] Change in coreboot[main]: soc/mediatek/mt8196: Add srclken_rc drivers
by Yu-Ping Wu (Code Review) 10 Jan '25

10 Jan '25

Attention is currently required from: Hung-Te Lin, Jarried Lin, ot_song fan. Yu-Ping Wu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85842?usp=email ) Change subject: soc/mediatek/mt8196: Add srclken_rc drivers ...................................................................... Patch Set 8: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85842?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I40f8d2b12027955e6bd57b666e9f04c0116a0a93 Gerrit-Change-Number: 85842 Gerrit-PatchSet: 8 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ot_song fan <ot_song.fan(a)mediatek.corp-partner.google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: ot_song fan <ot_song.fan(a)mediatek.corp-partner.google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Fri, 10 Jan 2025 14:14:22 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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