coreboot-gerrit January 2025

coreboot-gerrit@coreboot.org

1 participants
3269 discussions

[XS] Change in coreboot[main]: util/chromeos/crosfirmware: Improve matching when scanning manifest file
by Matt DeVillier (Code Review) 10 Jan '25

10 Jan '25

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85935?usp=email ) Change subject: util/chromeos/crosfirmware: Improve matching when scanning manifest file ...................................................................... util/chromeos/crosfirmware: Improve matching when scanning manifest file To ensure we find the correct firmware image, match against `$BOARD":` rather than just `$BOARD`. This fixes an issue where another board (b1) using the same firmware build or name as the one we are searching for, causes the grep matching to return empty strings. TEST=successfully extract the firmware image for CAREENA, which previously failed. Change-Id: I2f2a71f0b033938aafc1fd27e2996fe319614b3c Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M util/chromeos/crosfirmware.sh 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/85935/1 diff --git a/util/chromeos/crosfirmware.sh b/util/chromeos/crosfirmware.sh index ee87329..ab03cf6 100755 --- a/util/chromeos/crosfirmware.sh +++ b/util/chromeos/crosfirmware.sh @@ -108,8 +108,8 @@ _bios_image=$(grep "IMAGE_MAIN" $_unpacked/models/$_board/setvars.sh | cut -f2 -d\") elif [ -f "$_unpacked/manifest.json" ]; then - _version=$(grep -m1 -A1 "$BOARD" "$_unpacked/manifest.json" | grep "host" | cut -f12 -d'"') - _bios_image=$(grep -m1 -A3 "$BOARD" "$_unpacked/manifest.json" | grep "image" | cut -f4 -d'"') + _version=$(grep -m1 -A1 "$BOARD\":" "$_unpacked/manifest.json" | grep "host" | cut -f12 -d'"') + _bios_image=$(grep -m1 -A3 "$BOARD\":" "$_unpacked/manifest.json" | grep "image" | cut -f4 -d'"') else _version=$(cat $_unpacked/VERSION | grep BIOS\ version: | cut -f2 -d: | tr -d \ ) -- To view, visit https://review.coreboot.org/c/coreboot/+/85935?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2f2a71f0b033938aafc1fd27e2996fe319614b3c Gerrit-Change-Number: 85935 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com>

1 0

[S] Change in coreboot[main]: drivers/option: Add CBFS file based option backend
by Julius Werner (Code Review) 10 Jan '25

10 Jan '25

Attention is currently required from: Nicholas Chin. Julius Werner has posted comments on this change by Nicholas Chin. ( https://review.coreboot.org/c/coreboot/+/85905?usp=email ) Change subject: drivers/option: Add CBFS file based option backend ...................................................................... Patch Set 2: (3 comments) Patchset: PS2: BTW I think it would be another useful change if `cbfstool add-int` would automatically replace the old file if it already exists (right now it errors out and you have to call `cbfstool remove` manually), since it's specifically designed to manipulate these sorts of small option files. File src/drivers/option/cbfs_file_option.c: https://review.coreboot.org/c/coreboot/+/85905/comment/62aae95a_2d06dd96?us… : PS2, Line 11: cbfs_map Note that when using boards with CONFIG_VBOOT, this will read from the current slot (RO/RW_A/RW_B). This creates all kinds of complications that are probably not helpful for this (e.g. need to pass `-r FW_MAIN_A` or something like that to cbfstool every time, different stages could be using different option values, RW CBFSes need to be resigned each time after running cbfstool). Since people with manual flash access who'd be using this can usually reflash the RO section anyway, I think it would probably make more sense here to use `cbfs_ro_map()` and just always read this file from RO. https://review.coreboot.org/c/coreboot/+/85905/comment/58731a3b_274e588f?us… : PS2, Line 11: name Since the option names are all over the place, should we group them under a prefix in CBFS (e.g. `option/<optionname>`) to give it a bit more structure? -- To view, visit https://review.coreboot.org/c/coreboot/+/85905?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifc0439ee42f13f49ae54d4855d1d9333c39b01f5 Gerrit-Change-Number: 85905 Gerrit-PatchSet: 2 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Sat, 11 Jan 2025 00:21:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

1 0

[M] Change in coreboot[main]: drivers/amd/opensil/romstage.c: Implement cbmem_top_chipset in driver
by Felix Held (Code Review) 10 Jan '25

10 Jan '25

Attention is currently required from: Martin Roth, Nick Kochlowski. Felix Held has posted comments on this change by Nick Kochlowski. ( https://review.coreboot.org/c/coreboot/+/85635?usp=email ) Change subject: drivers/amd/opensil/romstage.c: Implement cbmem_top_chipset in driver ...................................................................... Patch Set 12: (2 comments) Patchset: PS12: rest looks good File src/vendorcode/amd/opensil/opensil.h: https://review.coreboot.org/c/coreboot/+/85635/comment/c930c52f_da26baae?us… : PS12, Line 16: uintptr_t uintptr_t needs the include defining that; not sure if inttypes.h or types.h would be the better one to include in this file -- To view, visit https://review.coreboot.org/c/coreboot/+/85635?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibc79456b0429cdd3d8e3fa5c224799a05add8359 Gerrit-Change-Number: 85635 Gerrit-PatchSet: 12 Gerrit-Owner: Nick Kochlowski <nickkochlowski(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Nick Kochlowski <nickkochlowski(a)gmail.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Fri, 10 Jan 2025 22:05:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

1 0

[L] Change in coreboot[main]: drivers/amd/opensil/mpio: Factor out common MPIO symbols from vendorcode
by Felix Held (Code Review) 10 Jan '25

10 Jan '25

Attention is currently required from: Fred Reitberger, Jason Glenesk, Martin L Roth, Martin Roth, Matt DeVillier, Nick Kochlowski, Varshit Pandya. Felix Held has posted comments on this change by Nick Kochlowski. ( https://review.coreboot.org/c/coreboot/+/85632?usp=email ) Change subject: drivers/amd/opensil/mpio: Factor out common MPIO symbols from vendorcode ...................................................................... Patch Set 12: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85632?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8b1f92f08565216dd93203a06015e3eec1e7bb69 Gerrit-Change-Number: 85632 Gerrit-PatchSet: 12 Gerrit-Owner: Nick Kochlowski <nickkochlowski(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Nick Kochlowski <nickkochlowski(a)gmail.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Fri, 10 Jan 2025 21:22:13 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

1 0

[M] Change in coreboot[main]: drivers/amd/nova: Add Nova Card common driver
by Felix Held (Code Review) 10 Jan '25

10 Jan '25

Attention is currently required from: Ana Carolina Cabral. Felix Held has posted comments on this change by Ana Carolina Cabral. ( https://review.coreboot.org/c/coreboot/+/84776?usp=email ) Change subject: drivers/amd/nova: Add Nova Card common driver ...................................................................... Patch Set 10: (1 comment) File src/drivers/amd/nova/chip.h: https://review.coreboot.org/c/coreboot/+/84776/comment/14f21ab6_951d7f5a?us… : PS7, Line 10: #define NOVA_CARD_EEPROM_I2C_BUS 2 : #define NOVA_CARD_EEPROM_I2C_ADDRESS 0x55 > I put it there as a "default" value, but each board can use a different setup when calling the funct […] i'd move those to the mainboard-specific code, since at least the bus number doesn't depend on the nova card design at all. not sure if the address pins of the eeprom on the nova card are hardwired on the card or at least one address bit can be configured via the level of one pin on the nova card socket on the board -- To view, visit https://review.coreboot.org/c/coreboot/+/84776?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5e9ded2090d6a5865e3330408f490e59fbf480f4 Gerrit-Change-Number: 84776 Gerrit-PatchSet: 10 Gerrit-Owner: Ana Carolina Cabral Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-CC: Anand Vaikar <a.vaikar2021(a)gmail.com> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ana Carolina Cabral Gerrit-Comment-Date: Fri, 10 Jan 2025 20:57:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Ana Carolina Cabral Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de>

1 0

[XS] Change in coreboot[main]: intel/common/rtd3: Allow emitting PSD0 Method for PCH Root Ports
by Cliff Huang (Code Review) 10 Jan '25

10 Jan '25

1 0

[XS] Change in coreboot[main]: intel/common/rtd3: Allow emitting PSD0 Method for PCH Root Ports
by Cliff Huang (Code Review) 10 Jan '25

10 Jan '25

Attention is currently required from: Matt DeVillier, Sean Rhodes. Cliff Huang has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/85696?usp=email ) Change subject: intel/common/rtd3: Allow emitting PSD0 Method for PCH Root Ports ...................................................................... Patch Set 7: (1 comment) File src/soc/intel/common/block/pcie/rtd3/rtd3.c: https://review.coreboot.org/c/coreboot/+/85696/comment/7f324be1_e25cc58b?us… : PS5, Line 437: if (rp_type != PCIE_RP_PCH) { > At the time, only PCH RP has power control for root port PHY. […] Modphy gatting is supported only for PCIe root port under PCH in rtd3.c. The CPU PCIe root ports in older archecture like Tiger Lake Alder lake do not have this support. However, In the recent SoC architecture, all PCIe Root ports in PCD (i.e. PCIE_RP_PCH) and therefore, modPHY gating is supported for all RP ports. Please see src/soc/intel/common/block/pcie/rtd3/chip.h for the comments regarding of ext_pm_support. -- To view, visit https://review.coreboot.org/c/coreboot/+/85696?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia34cc1f9099ca88fa16a83174ec90ca14f43ab56 Gerrit-Change-Number: 85696 Gerrit-PatchSet: 7 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Comment-Date: Fri, 10 Jan 2025 20:07:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Cliff Huang <cliff.huang(a)intel.com> Comment-In-Reply-To: Sean Rhodes <sean(a)starlabs.systems> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com>

1 0

[L] Change in coreboot[main]: mb/asrock: Add Z87 Extreme4 (Haswell)
by Angel Pons (Code Review) 10 Jan '25

10 Jan '25

Attention is currently required from: Jan Philipp Groß, Keith Hui, Máté Kukri, Nicholas Chin. Angel Pons has posted comments on this change by Jan Philipp Groß. ( https://review.coreboot.org/c/coreboot/+/84672?usp=email ) Change subject: mb/asrock: Add Z87 Extreme4 (Haswell) ...................................................................... Patch Set 10: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84672?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I78791aa9877a3ad79bf8b896c583fedf37e96d9a Gerrit-Change-Number: 84672 Gerrit-PatchSet: 10 Gerrit-Owner: Jan Philipp Groß <jeangrande(a)mailbox.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Máté Kukri <km(a)mkukri.xyz> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Keith Hui <buurin(a)gmail.com> Gerrit-Attention: Máté Kukri <km(a)mkukri.xyz> Gerrit-Attention: Jan Philipp Groß <jeangrande(a)mailbox.org> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Fri, 10 Jan 2025 19:59:38 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

1 0

[L] Change in coreboot[main]: mb/asrock: Add Z87 Extreme3 (Haswell)
by Jan Philipp Groß (Code Review) 10 Jan '25

10 Jan '25

Attention is currently required from: Angel Pons, Felix Singer, Keith Hui, Máté Kukri, Nicholas Chin. Hello Angel Pons, Felix Singer, Keith Hui, Máté Kukri, Nicholas Chin, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85926?usp=email to look at the new patch set (#3). Change subject: mb/asrock: Add Z87 Extreme3 (Haswell) ...................................................................... mb/asrock: Add Z87 Extreme3 (Haswell) This port was done via autoport and subsequent manual tweaking. Working: - Haswell MRC.bin - All four DDR3/DDR3L DIMM slots - S3 suspend and resume - D-Sub Port - DVI-D Port - HDMI Port - RJ-45 Gigabit LAN Port - Both rear USB 2.0 Ports - All four rear USB 3.1 Gen1 Ports - Both USB 2.0 headers - USB 3.1 Gen1 header - All six SATA3 6.0 Gb/s connectors by Intel - Both PCI Express 3.0 x16 slots (Tested with RX 550 PCIe x8 GPU) - PCI Express 2.0 x1 slots (tested with TL-WDN4800 WiFi adapter) - HD Audio Jack (Audio output tested only) - Front Audio Jack (Audio output tested only) not (yet) tested: - PCI slots - IR header - COM Port header - eSATA connector - PS/2 Mouse/Keyboard Port - Optical SPDIF Out Port Change-Id: I3c13c068d899588eda80b9957127bcb6ccf8bab0 Signed-off-by: Jan Philipp Groß <jeangrande(a)mailbox.org> --- A src/mainboard/asrock/z87_extreme3/Kconfig A src/mainboard/asrock/z87_extreme3/Kconfig.name A src/mainboard/asrock/z87_extreme3/Makefile.mk A src/mainboard/asrock/z87_extreme3/acpi/ec.asl A src/mainboard/asrock/z87_extreme3/acpi/platform.asl A src/mainboard/asrock/z87_extreme3/acpi/superio.asl A src/mainboard/asrock/z87_extreme3/board_info.txt A src/mainboard/asrock/z87_extreme3/bootblock.c A src/mainboard/asrock/z87_extreme3/data.vbt A src/mainboard/asrock/z87_extreme3/devicetree.cb A src/mainboard/asrock/z87_extreme3/dsdt.asl A src/mainboard/asrock/z87_extreme3/gma-mainboard.ads A src/mainboard/asrock/z87_extreme3/gpio.c A src/mainboard/asrock/z87_extreme3/hda_verb.c A src/mainboard/asrock/z87_extreme3/romstage.c 15 files changed, 528 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/85926/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/85926?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3c13c068d899588eda80b9957127bcb6ccf8bab0 Gerrit-Change-Number: 85926 Gerrit-PatchSet: 3 Gerrit-Owner: Jan Philipp Groß <jeangrande(a)mailbox.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Máté Kukri <km(a)mkukri.xyz> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Keith Hui <buurin(a)gmail.com> Gerrit-Attention: Máté Kukri <km(a)mkukri.xyz> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com>

1 0

[L] Change in coreboot[main]: mb/asrock: Add Z87 Extreme4 (Haswell)
by Jan Philipp Groß (Code Review) 10 Jan '25

10 Jan '25

Attention is currently required from: Angel Pons, Jan Philipp Groß, Keith Hui, Máté Kukri, Nicholas Chin. Hello Angel Pons, Keith Hui, Máté Kukri, Nicholas Chin, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84672?usp=email to look at the new patch set (#10). The following approvals got outdated and were removed: Code-Review+2 by Angel Pons, Verified+1 by build bot (Jenkins) The change is no longer submittable: Code-Review and Verified are unsatisfied now. Change subject: mb/asrock: Add Z87 Extreme4 (Haswell) ...................................................................... mb/asrock: Add Z87 Extreme4 (Haswell) This port was done via autoport and subsequent manual tweaking. The board features two socketed DIP-8 SPI flash chips, as well as a BIOS selection via jumper and onboard Power and Reset switches. Working: - Haswell MRC.bin - All four DDR3/DDR3L DIMM slots - S3 suspend and resume - HDMI-Out Port - DVI-D Port - RJ-45 Gigabit LAN Port - Both USB 2.0 Ports - All four USB 3.1 Gen1 Ports - All three USB 2.0 headers - Both USB 3.1 Gen1 headers - Vertical Type A USB 3.1 Gen1 (located next to RAM slots and PCH) - All six SATA3 6.0 Gb/s connectors by Intel - All three PCI Express 3.0 x16 slots (tested with NV 1080 Ti dGPU) - Both PCI Express 2.0 x1 slots (tested with TL-WDN4800 WiFi adapter) - HD Audio Jack (Audio output tested only) - Front Audio Jack (Audio output tested only) not (yet) working: - both SATA3 6.0 Gb/s connectors by ASMedia ASM1061 (fix will soon be merged) - POST code display and LEDs do not turn off after a successful boot not (yet) tested: - IR header - COM Port header - DisplayPort - eSATA connector - PS/2 Mouse/Keyboard Port - HDMI-In Port - PCI slots Change-Id: I78791aa9877a3ad79bf8b896c583fedf37e96d9a Signed-off-by: Jan Philipp Groß <jeangrande(a)mailbox.org> --- A src/mainboard/asrock/z87_extreme4/Kconfig A src/mainboard/asrock/z87_extreme4/Kconfig.name A src/mainboard/asrock/z87_extreme4/Makefile.mk A src/mainboard/asrock/z87_extreme4/acpi/ec.asl A src/mainboard/asrock/z87_extreme4/acpi/platform.asl A src/mainboard/asrock/z87_extreme4/acpi/superio.asl A src/mainboard/asrock/z87_extreme4/board_info.txt A src/mainboard/asrock/z87_extreme4/bootblock.c A src/mainboard/asrock/z87_extreme4/data.vbt A src/mainboard/asrock/z87_extreme4/devicetree.cb A src/mainboard/asrock/z87_extreme4/dsdt.asl A src/mainboard/asrock/z87_extreme4/gma-mainboard.ads A src/mainboard/asrock/z87_extreme4/gpio.c A src/mainboard/asrock/z87_extreme4/hda_verb.c A src/mainboard/asrock/z87_extreme4/romstage.c 15 files changed, 535 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/84672/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/84672?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I78791aa9877a3ad79bf8b896c583fedf37e96d9a Gerrit-Change-Number: 84672 Gerrit-PatchSet: 10 Gerrit-Owner: Jan Philipp Groß <jeangrande(a)mailbox.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Máté Kukri <km(a)mkukri.xyz> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Keith Hui <buurin(a)gmail.com> Gerrit-Attention: Máté Kukri <km(a)mkukri.xyz> Gerrit-Attention: Jan Philipp Groß <jeangrande(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com>

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit January 2025