coreboot-gerrit January 2025

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[XS] Change in coreboot[main]: arch/x86/cpu: Mark fill_cpu_cache_info as weak
by Angel Pons (Code Review) 11 Jan '25

11 Jan '25

Attention is currently required from: Felix Held, Jérémy Compostella, Maximilian Brune, Naresh Solanki. Angel Pons has posted comments on this change by Naresh Solanki. ( https://review.coreboot.org/c/coreboot/+/85638?usp=email ) Change subject: arch/x86/cpu: Mark fill_cpu_cache_info as weak ...................................................................... Patch Set 1: Code-Review+1 (1 comment) File src/arch/x86/cpu_common.c: https://review.coreboot.org/c/coreboot/+/85638/comment/9e2318c2_fd93abf0?us… : PS1, Line 224: struct cpuid_result cache_info_res = cpuid_ext(leaf, level); : : info->type = CPUID_CACHE_TYPE(cache_info_res); : info->level = CPUID_CACHE_LEVEL(cache_info_res); : info->num_ways = CPUID_CACHE_WAYS_OF_ASSOC(cache_info_res) + 1; : info->num_sets = CPUID_CACHE_NO_OF_SETS(cache_info_res) + 1; : info->line_size = CPUID_CACHE_COHER_LINE(cache_info_res) + 1; : info->physical_partitions = CPUID_CACHE_PHYS_LINE(cache_info_res) + 1; : info->num_cores_shared = CPUID_CACHE_SHARING_CACHE(cache_info_res) + 1; : info->fully_associative = CPUID_CACHE_FULL_ASSOC(cache_info_res); : info->size = get_cache_size(info); : Looking at follow-ups, would it make sense to extract this part into a helper function? -- To view, visit https://review.coreboot.org/c/coreboot/+/85638?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I60707de4c8242a8fbda8cb5b791a1db762d94449 Gerrit-Change-Number: 85638 Gerrit-PatchSet: 1 Gerrit-Owner: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Sat, 11 Jan 2025 13:36:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: soc/amd/glinda/cpu: smbios: update external clock
by Angel Pons (Code Review) 11 Jan '25

11 Jan '25

Attention is currently required from: Felix Held, Naresh Solanki. Angel Pons has posted comments on this change by Naresh Solanki. ( https://review.coreboot.org/c/coreboot/+/85636?usp=email ) Change subject: soc/amd/glinda/cpu: smbios: update external clock ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/85636?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I99f73695019612d58b0c78c6985370d23c78b729 Gerrit-Change-Number: 85636 Gerrit-PatchSet: 2 Gerrit-Owner: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Sat, 11 Jan 2025 13:31:51 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: mb/*: Drop xhci_overcurrent_map II
by Keith Hui (Code Review) 11 Jan '25

11 Jan '25

Attention is currently required from: Alexander Couzens, Nicholas Chin, Patrick Rudolph. Keith Hui has posted comments on this change by Keith Hui. ( https://review.coreboot.org/c/coreboot/+/85924?usp=email ) Change subject: mb/*: Drop xhci_overcurrent_map II ...................................................................... Patch Set 1: (2 comments) Patchset: PS1: Did find quite a few leftovers from CB:81882, including some 6-series boards which aren't affected (weren't hit) by this train. A new patch is being prepared to clean them out. PS1: > Apparently you broke it in https://review.coreboot.org/c/coreboot/+/81882/7 […] This is the kind of manual review I'm talking about. I am checking the values in usb_port_config in devicetree and overridetree against this value and manually calculate what should have been there. Turs out the usb_port_configs for T530 are in the overridetree of the variants, and they do match. A new patch for t530 is being prepared nad other reviews are ongoing. These reviews would be much easier if xhci_overcurrent_mapping and usb_port_config are in the same file. -- To view, visit https://review.coreboot.org/c/coreboot/+/85924?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie60d34cae5ae94d148854b42f77ab4c02e8f49ef Gerrit-Change-Number: 85924 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Sat, 11 Jan 2025 13:29:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com>

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[M] Change in coreboot[main]: soc/mediatek/mt8196: Initialize MCUPM
by Jarried Lin (Code Review) 11 Jan '25

11 Jan '25

Attention is currently required from: Hung-Te Lin, Jarried Lin. Hello Hung-Te Lin, Yidi Lin, Yu-Ping Wu, agogo, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85888?usp=email to look at the new patch set (#3). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/mediatek/mt8196: Initialize MCUPM ...................................................................... soc/mediatek/mt8196: Initialize MCUPM Load MCUPM firmware and boot up MCUPM in ramstage. It takes 54 ms to load mcupm.bin. coreboot logs: CBFS: Found 'mcupm.bin' @0x37a80 size 0xdbda in mcache @0xfffdd308 mtk_init_mcu: Loaded (and reset) mcupm.bin in 54 msecs (486931 bytes) TEST=Build pass and we can see the mcupm logs after reset releases. BUG=b:317009620 Change-Id: I223f245d384f32d54f6170a28b29573638f77296 Signed-off-by: agogo.huang <agogo.huang(a)mediatek.corp-partner.google.com> --- M src/soc/mediatek/mt8196/Kconfig M src/soc/mediatek/mt8196/Makefile.mk M src/soc/mediatek/mt8196/include/soc/addressmap.h A src/soc/mediatek/mt8196/include/soc/mcupm_plat.h A src/soc/mediatek/mt8196/mcupm.c M src/soc/mediatek/mt8196/soc.c 6 files changed, 239 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/85888/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/85888?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I223f245d384f32d54f6170a28b29573638f77296 Gerrit-Change-Number: 85888 Gerrit-PatchSet: 3 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: agogo <agogo.huang(a)mediatek.corp-partner.google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com>

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[S] Change in coreboot[main]: soc/intel/xeon_sp: Allow OS to control LTR and AER
by Patrick Rudolph (Code Review) 11 Jan '25

11 Jan '25

Patrick Rudolph has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85561?usp=email ) Change subject: soc/intel/xeon_sp: Allow OS to control LTR and AER ...................................................................... soc/intel/xeon_sp: Allow OS to control LTR and AER There's no reason to tell the OS to disable LTR. On UEFI and on coreboot's GNR LTR is allowed, thus allow it for all Xeon-SP. There's no SMM (RAS) code that is able to parse AER structures, thus let the OS always control AER. On coreboot's GNR AER is also always granted to the OS. TEST: Run code on ocp/tiogapass and observed dmesg: The OS now prints: acpi PNP0A08:04: _OSC: OS now controls [PCIeHotplug PME AER PCIeCapability LTR] Change-Id: I7c4176a4df898cee28f6319c6684763e825d9c46 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85561 Reviewed-by: Shuo Liu <shuo.liu(a)intel.com> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Marvin Drees <marvin.drees(a)9elements.com> --- M src/soc/intel/xeon_sp/acpi/gen1/iiostack.asl M src/soc/intel/xeon_sp/spr/acpi/cxl_resource.asl M src/soc/intel/xeon_sp/spr/acpi/pci_resource.asl 3 files changed, 9 insertions(+), 3 deletions(-) Approvals: Angel Pons: Looks good to me, approved build bot (Jenkins): Verified Shuo Liu: Looks good to me, approved Marvin Drees: Looks good to me, but someone else must approve diff --git a/src/soc/intel/xeon_sp/acpi/gen1/iiostack.asl b/src/soc/intel/xeon_sp/acpi/gen1/iiostack.asl index ffe692d..0095aa5 100644 --- a/src/soc/intel/xeon_sp/acpi/gen1/iiostack.asl +++ b/src/soc/intel/xeon_sp/acpi/gen1/iiostack.asl @@ -32,8 +32,10 @@ Method (_OSC, 4, NotSerialized) \ { \ Return (\_SB.POSC(Arg0, Arg1, Arg2, Arg3, \ - (PCIE_CAP_STRUCTURE_CONTROL| \ + (PCIE_LTR_CONTROL| \ + PCIE_CAP_STRUCTURE_CONTROL| \ PCIE_PME_CONTROL| \ + PCIE_AER_CONTROL| \ PCIE_NATIVE_HOTPLUG_CONTROL), 0 , 0)) \ } \ } diff --git a/src/soc/intel/xeon_sp/spr/acpi/cxl_resource.asl b/src/soc/intel/xeon_sp/spr/acpi/cxl_resource.asl index bf02766..3ff3635 100644 --- a/src/soc/intel/xeon_sp/spr/acpi/cxl_resource.asl +++ b/src/soc/intel/xeon_sp/spr/acpi/cxl_resource.asl @@ -39,8 +39,10 @@ Method (_OSC, 4, NotSerialized) { Return (\_SB.POSC(Arg0, Arg1, Arg2, Arg3, - (PCIE_CAP_STRUCTURE_CONTROL| + (PCIE_LTR_CONTROL| + PCIE_CAP_STRUCTURE_CONTROL| PCIE_PME_CONTROL| + PCIE_AER_CONTROL| PCIE_NATIVE_HOTPLUG_CONTROL), 1, CXL_ERROR_REPORTING_CONTROL)) } diff --git a/src/soc/intel/xeon_sp/spr/acpi/pci_resource.asl b/src/soc/intel/xeon_sp/spr/acpi/pci_resource.asl index a81f28a..83a6efa 100644 --- a/src/soc/intel/xeon_sp/spr/acpi/pci_resource.asl +++ b/src/soc/intel/xeon_sp/spr/acpi/pci_resource.asl @@ -37,8 +37,10 @@ Method (_OSC, 4, NotSerialized) { Return (\_SB.POSC(Arg0, Arg1, Arg2, Arg3, - (PCIE_CAP_STRUCTURE_CONTROL| + (PCIE_LTR_CONTROL| + PCIE_CAP_STRUCTURE_CONTROL| PCIE_PME_CONTROL| + PCIE_AER_CONTROL| PCIE_NATIVE_HOTPLUG_CONTROL), 0 , 0)) } } -- To view, visit https://review.coreboot.org/c/coreboot/+/85561?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7c4176a4df898cee28f6319c6684763e825d9c46 Gerrit-Change-Number: 85561 Gerrit-PatchSet: 8 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <tanleansheng(a)outlook.com> Gerrit-Reviewer: Marvin Drees <marvin.drees(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in coreboot[main]: soc/intel/xeon_sp: Use \_SB.POSC on all platforms
by Patrick Rudolph (Code Review) 11 Jan '25

11 Jan '25

Patrick Rudolph has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85559?usp=email ) Change subject: soc/intel/xeon_sp: Use \_SB.POSC on all platforms ...................................................................... soc/intel/xeon_sp: Use \_SB.POSC on all platforms Reduce ACPI code size by using the existing \_SB.POSC instead of duplicating the method in every PCI/CXL host bridge. TEST: On ocp/tiogapass the OS still gets granted the PCIe capabilities as previously through _OSC. Reduces DSDT size by 1366 bytes. On ibm/sbp1 the OS still gets granted the PCIe capabilities as previously through _OSC. Change-Id: I2f25ffbde9b83d286c568202fcffb75ffb07286c Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85559 Reviewed-by: Shuo Liu <shuo.liu(a)intel.com> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/xeon_sp/acpi/gen1/iiostack.asl M src/soc/intel/xeon_sp/spr/acpi/cxl_resource.asl M src/soc/intel/xeon_sp/spr/acpi/pci_resource.asl M src/soc/intel/xeon_sp/spr/acpi/uncore.asl 4 files changed, 20 insertions(+), 139 deletions(-) Approvals: Shuo Liu: Looks good to me, approved build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/soc/intel/xeon_sp/acpi/gen1/iiostack.asl b/src/soc/intel/xeon_sp/acpi/gen1/iiostack.asl index 735197a..ffe692d 100644 --- a/src/soc/intel/xeon_sp/acpi/gen1/iiostack.asl +++ b/src/soc/intel/xeon_sp/acpi/gen1/iiostack.asl @@ -1,5 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <soc/intel/xeon_sp/acpi/iiostack.asl> +#include <soc/acpi.h> + #define MAKE_IIO_DEV(id,rt,pxm) \ Device (PC##id) \ { \ @@ -25,50 +28,14 @@ } \ Return (\_SB_.PR##rt) \ } \ - Name (SUPP, 0x00) \ - Name (CTRL, 0x00) \ Name (_PXM, pxm) /* _PXM: Device Proximity */ \ Method (_OSC, 4, NotSerialized) \ { \ - CreateDWordField (Arg3, 0x00, CDW1) \ - If ((Arg0 == ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */)) \ - { \ - If (Arg2 < 0x03) \ - { \ - CDW1 |= 0x02 /* Unknown failure */ \ - Return (Arg3) \ - } \ - CreateDWordField (Arg3, 0x04, CDW2) \ - CreateDWordField (Arg3, 0x08, CDW3) \ - SUPP = CDW2 \ - CTRL = CDW3 \ - If ((SUPP & 0x16) != 0x16) \ - { \ - CTRL &= 0x1E \ - } \ - /* Never allow SHPC (no SHPC controller in system) */ \ - CTRL &= 0x1D \ - /* Disable Native PCIe AER handling from OS */ \ - CTRL &= 0x17 \ - If ((Arg1 != 1)) /* unknown revision */ \ - { \ - CDW1 |= 0x08 \ - } \ - If ((CDW3 != CTRL)) /* capabilities bits were masked */ \ - { \ - CDW1 |= 0x10 \ - } \ - CDW3 = CTRL \ - Return (Arg3) \ - } \ - Else \ - { \ - /* indicate unrecognized UUID */ \ - CDW1 |= 0x04 \ - DBG0 = 0xEE \ - Return (Arg3) \ - } \ - } \ + Return (\_SB.POSC(Arg0, Arg1, Arg2, Arg3, \ + (PCIE_CAP_STRUCTURE_CONTROL| \ + PCIE_PME_CONTROL| \ + PCIE_NATIVE_HOTPLUG_CONTROL), 0 , 0)) \ + } \ } // Keep in sync with iio_domain_set_acpi_name()! diff --git a/src/soc/intel/xeon_sp/spr/acpi/cxl_resource.asl b/src/soc/intel/xeon_sp/spr/acpi/cxl_resource.asl index 7676a3f..bf02766 100644 --- a/src/soc/intel/xeon_sp/spr/acpi/cxl_resource.asl +++ b/src/soc/intel/xeon_sp/spr/acpi/cxl_resource.asl @@ -36,63 +36,12 @@ { Return (\_SB.PRTID) } - Name (SUPP, 0x00) // PCI _OSC Support Field Value - Name (CTRL, 0x00) // PCI _OSC Control Field Value - Name (SUPC, 0x00) // CXL _OSC Support Field Value - Name (CTRC, 0x00) // CXL _OSC Control Field Value - Name (_PXM, 0x00) /* _PXM: Device Proximity */ Method (_OSC, 4, NotSerialized) { - CreateDWordField (Arg3, 0x00, CDW1) - If (Arg0 == ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */ - || Arg0 == ToUUID ("68f2d50b-c469-4d8a-bd3d-941a103fd3fc")) /* CXL 2.0 */ - { - If (Arg2 < 0x03) /* Number of DWORDs in Arg3 must be at least 3 */ - { - CDW1 |= 0x02 /* Unknown failure */ - Return (Arg3) - } - CreateDWordField (Arg3, 0x04, CDW2) - CreateDWordField (Arg3, 0x08, CDW3) - - SUPP = CDW2 - CTRL = CDW3 - If (Arg0 == ToUUID ("68f2d50b-c469-4d8a-bd3d-941a103fd3fc")) /* CXL 2.0 */ - { - CreateDWordField (Arg3, 0x0C, CDW4) - CreateDWordField (Arg3, 0x10, CDW5) - SUPC = CDW4 - CTRC = CDW5 - } - If (SUPP & 0x16 != 0x16) - { - CTRL &= 0x1E - } - /* Never allow SHPC (no SHPC controller in system) */ - CTRL &= 0x1D - /* Disable Native PCIe AER handling from OS */ - CTRL &= 0x17 - If (Arg1 != 1) /* unknown revision */ - { - CDW1 |= 0x08 - } - If (CDW3 != CTRL) /* capabilities bits were masked */ - { - CDW1 |= 0x10 - } - CDW3 = CTRL - If (Arg0 == ToUUID ("68f2d50b-c469-4d8a-bd3d-941a103fd3fc")) /* CXL 2.0 */ - { - CDW5 = CTRC - } - Return (Arg3) - } - Else - { - /* indicate unrecognized UUID */ - CDW1 |= 0x04 - IO80 = 0xEE - Return (Arg3) - } + Return (\_SB.POSC(Arg0, Arg1, Arg2, Arg3, + (PCIE_CAP_STRUCTURE_CONTROL| + PCIE_PME_CONTROL| + PCIE_NATIVE_HOTPLUG_CONTROL), 1, + CXL_ERROR_REPORTING_CONTROL)) } } diff --git a/src/soc/intel/xeon_sp/spr/acpi/pci_resource.asl b/src/soc/intel/xeon_sp/spr/acpi/pci_resource.asl index a2cc03f..a81f28a 100644 --- a/src/soc/intel/xeon_sp/spr/acpi/pci_resource.asl +++ b/src/soc/intel/xeon_sp/spr/acpi/pci_resource.asl @@ -32,50 +32,13 @@ { Return (\_SB.PRTID) } - Name (SUPP, 0x00) - Name (CTRL, 0x00) Name (_PXM, SOCKET) /* _PXM: Device Proximity */ + Method (_OSC, 4, NotSerialized) { - CreateDWordField (Arg3, 0x00, CDW1) - If (Arg0 == ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */) - { - If (Arg2 < 0x03) /* Number of DWORDs in Arg3 must be at least 3 */ - { - CDW1 |= 0x02 /* Unknown failure */ - Return (Arg3) - } - CreateDWordField (Arg3, 0x04, CDW2) - CreateDWordField (Arg3, 0x08, CDW3) - - SUPP = CDW2 - CTRL = CDW3 - If (SUPP & 0x16 != 0x16) - { - CTRL &= 0x1E - } - /* Never allow SHPC (no SHPC controller in system) */ - CTRL &= 0x1D - /* Disable Native PCIe AER handling from OS */ - CTRL &= 0x17 - - If (Arg1 != 1) /* unknown revision */ - { - CDW1 |= 0x08 - } - If (CDW3 != CTRL) /* capabilities bits were masked */ - { - CDW1 |= 0x10 - } - CDW3 = CTRL - Return (Arg3) - } - Else - { - /* indicate unrecognized UUID */ - CDW1 |= 0x04 - IO80 = 0xEE - Return (Arg3) - } + Return (\_SB.POSC(Arg0, Arg1, Arg2, Arg3, + (PCIE_CAP_STRUCTURE_CONTROL| + PCIE_PME_CONTROL| + PCIE_NATIVE_HOTPLUG_CONTROL), 0 , 0)) } } diff --git a/src/soc/intel/xeon_sp/spr/acpi/uncore.asl b/src/soc/intel/xeon_sp/spr/acpi/uncore.asl index f6fbe96..ab2c3eb 100644 --- a/src/soc/intel/xeon_sp/spr/acpi/uncore.asl +++ b/src/soc/intel/xeon_sp/spr/acpi/uncore.asl @@ -2,6 +2,7 @@ #include <intelblocks/itss.h> #include <intelblocks/pcr.h> +#include <soc/acpi.h> #include <soc/iomap.h> #include <soc/irq.h> #include <soc/pcr_ids.h> @@ -9,6 +10,7 @@ Scope (\_SB) { #include "uncore_irq.asl" + #include <soc/intel/xeon_sp/acpi/iiostack.asl> // Keep in sync with iio_domain_set_acpi_name()! #define SOCKET 0 -- To view, visit https://review.coreboot.org/c/coreboot/+/85559?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2f25ffbde9b83d286c568202fcffb75ffb07286c Gerrit-Change-Number: 85559 Gerrit-PatchSet: 9 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <tanleansheng(a)outlook.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: soc/intel/xeon_sp: Guard function prototypes
by Patrick Rudolph (Code Review) 11 Jan '25

11 Jan '25

Patrick Rudolph has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85595?usp=email ) Change subject: soc/intel/xeon_sp: Guard function prototypes ...................................................................... soc/intel/xeon_sp: Guard function prototypes Guard function prototypes to allow the header to be used in ACPI ASL code. The defines will be used in the next commit. Change-Id: Id6c361155c914f168577833279b4b7cc317b2eec Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85595 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Shuo Liu <shuo.liu(a)intel.com> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/xeon_sp/include/soc/acpi.h 1 file changed, 9 insertions(+), 7 deletions(-) Approvals: Shuo Liu: Looks good to me, approved build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/soc/intel/xeon_sp/include/soc/acpi.h b/src/soc/intel/xeon_sp/include/soc/acpi.h index 0e93dc2..d35b0fe 100644 --- a/src/soc/intel/xeon_sp/include/soc/acpi.h +++ b/src/soc/intel/xeon_sp/include/soc/acpi.h @@ -3,6 +3,7 @@ #ifndef _SOC_ACPI_H_ #define _SOC_ACPI_H_ +#ifndef __ACPI__ #include <acpi/acpi.h> #define MAX_SRAT_MEM_ENTRIES_PER_IMC 8 @@ -23,6 +24,14 @@ void iio_domain_set_acpi_name(struct device *dev, const char *prefix); +void acpigen_write_OSC_pci_domain_fixed_caps(const struct device *domain, + const uint32_t granted_pcie_features, + const bool is_cxl_domain, + const uint32_t granted_cxl_features); +void acpigen_write_pci_root_port(const struct device *rp); +void acpigen_write_PRT_pre_routed(const struct device *br); +#endif + #define PCIE_NATIVE_HOTPLUG_CONTROL 0x01 #define SHPC_NATIVE_HOTPLUG_CONTROL 0x02 #define PCIE_PME_CONTROL 0x04 @@ -33,11 +42,4 @@ #define CXL_ERROR_REPORTING_CONTROL 0x01 -void acpigen_write_OSC_pci_domain_fixed_caps(const struct device *domain, - const uint32_t granted_pcie_features, - const bool is_cxl_domain, - const uint32_t granted_cxl_features); -void acpigen_write_pci_root_port(const struct device *rp); -void acpigen_write_PRT_pre_routed(const struct device *br); - #endif /* _SOC_ACPI_H_ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/85595?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id6c361155c914f168577833279b4b7cc317b2eec Gerrit-Change-Number: 85595 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <tanleansheng(a)outlook.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[L] Change in coreboot[main]: mb/starlabs/starbook: Put options in CFR cbtable
by Angel Pons (Code Review) 11 Jan '25

11 Jan '25

Attention is currently required from: Christian Walter, Sean Rhodes. Angel Pons has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/74743?usp=email ) Change subject: mb/starlabs/starbook: Put options in CFR cbtable ...................................................................... Patch Set 35: Code-Review+1 (1 comment) File src/mainboard/starlabs/starbook/cfr.c: https://review.coreboot.org/c/coreboot/+/74743/comment/eacb6633_465f7ac6?us… : PS35, Line 380: void lb_board(struct lb_header *header) : { : char *current = (char *)lb_new_record(header); : struct lb_cfr *cfr_root = (struct lb_cfr *)current; : : cfr_write_setup_menu(cfr_root, sm_root); : } : > should be: […] ```suggestion void mb_cfr_setup_menu(struct lb_cfr *cfr_root) { cfr_write_setup_menu(cfr_root, sm_root); } ``` I think something broke code blocks / suggestions in Gerrit, at least for me: newlines disappear for no reason when saving. -- To view, visit https://review.coreboot.org/c/coreboot/+/74743?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I816893e5c2663ed55ae9fa5dd662489b27332aa6 Gerrit-Change-Number: 74743 Gerrit-PatchSet: 35 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Lean Sheng Tan <tanleansheng(a)outlook.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Comment-Date: Sat, 11 Jan 2025 09:29:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com>

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[L] Change in coreboot[main]: mb/*: Remove old USB configurations from SNB/bd82x6x boards
by Patrick Rudolph (Code Review) 11 Jan '25

11 Jan '25

Patrick Rudolph has posted comments on this change by Keith Hui. ( https://review.coreboot.org/c/coreboot/+/81882?usp=email ) Change subject: mb/*: Remove old USB configurations from SNB/bd82x6x boards ...................................................................... Patch Set 7: (1 comment) Patchset: PS7: Some boards still have the `const struct southbridge_usb_port mainboard_usb_ports[] = {` in mainboard code, which is now unused, but are missing entries in devicetree.cb. Please fix. -- To view, visit https://review.coreboot.org/c/coreboot/+/81882?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie1cd21077136998a6e90050c95263f2efed68a67 Gerrit-Change-Number: 81882 Gerrit-PatchSet: 7 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Reviewer: Kevin Keijzer <kevin(a)quietlife.nl> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Sat, 11 Jan 2025 09:10:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: mb/*: Drop xhci_overcurrent_map II
by Patrick Rudolph (Code Review) 11 Jan '25

11 Jan '25

Attention is currently required from: Alexander Couzens, Keith Hui, Nicholas Chin. Patrick Rudolph has posted comments on this change by Keith Hui. ( https://review.coreboot.org/c/coreboot/+/85924?usp=email ) Change subject: mb/*: Drop xhci_overcurrent_map II ...................................................................... Patch Set 1: Code-Review-1 (1 comment) Patchset: PS1: > I used t530 as an example and the USB OC config matches. […] Apparently you broke it in https://review.coreboot.org/c/coreboot/+/81882/7 const struct southbridge_usb_port mainboard_usb_ports is now unused and usb_port_config is missing on those board listed here. Please fix https://review.coreboot.org/c/coreboot/+/81882 first. -- To view, visit https://review.coreboot.org/c/coreboot/+/85924?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie60d34cae5ae94d148854b42f77ab4c02e8f49ef Gerrit-Change-Number: 85924 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Attention: Keith Hui <buurin(a)gmail.com> Gerrit-Comment-Date: Sat, 11 Jan 2025 09:08:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com>

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