coreboot-gerrit January 2025

coreboot-gerrit@coreboot.org

1 participants
3269 discussions

[L] Change in coreboot[main]: mb/starlabs/starbook: Put options in CFR cbtable
by Matt DeVillier (Code Review) 11 Jan '25

11 Jan '25

Attention is currently required from: Christian Walter, Sean Rhodes. Matt DeVillier has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/74743?usp=email ) Change subject: mb/starlabs/starbook: Put options in CFR cbtable ...................................................................... Patch Set 35: (1 comment) File src/mainboard/starlabs/starbook/cfr.c: https://review.coreboot.org/c/coreboot/+/74743/comment/751cb28f_239e7dd0?us… : PS35, Line 380: void lb_board(struct lb_header *header) : { : char *current = (char *)lb_new_record(header); : struct lb_cfr *cfr_root = (struct lb_cfr *)current; : : cfr_write_setup_menu(cfr_root, sm_root); : } : > ```suggestion […] looks fine to me? -- To view, visit https://review.coreboot.org/c/coreboot/+/74743?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I816893e5c2663ed55ae9fa5dd662489b27332aa6 Gerrit-Change-Number: 74743 Gerrit-PatchSet: 35 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Lean Sheng Tan <tanleansheng(a)outlook.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Comment-Date: Sat, 11 Jan 2025 14:58:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com>

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[M] Change in coreboot[main]: soc/mediatek/mt8196: Initialize MCUPM
by Yidi Lin (Code Review) 11 Jan '25

11 Jan '25

Attention is currently required from: Hung-Te Lin, Jarried Lin, Yu-Ping Wu, agogo. Yidi Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85888?usp=email ) Change subject: soc/mediatek/mt8196: Initialize MCUPM ...................................................................... Patch Set 3: (8 comments) File src/soc/mediatek/mt8196/include/soc/addressmap.h: https://review.coreboot.org/c/coreboot/+/85888/comment/0963a059_79713c19?us… : PS3, Line 44: APIFRBUS_AO_BASE remove File src/soc/mediatek/mt8196/include/soc/mcupm_plat.h: https://review.coreboot.org/c/coreboot/+/85888/comment/fc72990a_2c16862d?us… : PS3, Line 27: APIFRBUS_AO_BASE IFRBUS_AO_REG_BUS_BASE https://review.coreboot.org/c/coreboot/+/85888/comment/e9b895d1_86a07851?us… : PS3, Line 30: APIFRBUS_AO_BASE IFRBUS_AO_REG_BUS_BASE https://review.coreboot.org/c/coreboot/+/85888/comment/ccfb518d_0231aaf0?us… : PS3, Line 83: #define SRAM_SLOT_NUM 0x00000014 /* 0x14 = 20 slots = 20*4Bytes = 80 Bytes */ ``` /* 0x14 = 20 slots = 20 * 4 Bytes = 80 Bytes */ #define SRAM_SLOT_NUM 0x00000014 ``` File src/soc/mediatek/mt8196/mcupm.c: https://review.coreboot.org/c/coreboot/+/85888/comment/42385aff_72712c58?us… : PS3, Line 59: 1 true https://review.coreboot.org/c/coreboot/+/85888/comment/798dfbbd_94fa2134?us… : PS3, Line 59: { not needed https://review.coreboot.org/c/coreboot/+/85888/comment/de7431c5_a9c55901?us… : PS3, Line 64: 0 false https://review.coreboot.org/c/coreboot/+/85888/comment/f431ac4f_fe066706?us… : PS3, Line 64: { not needed -- To view, visit https://review.coreboot.org/c/coreboot/+/85888?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I223f245d384f32d54f6170a28b29573638f77296 Gerrit-Change-Number: 85888 Gerrit-PatchSet: 3 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: agogo <agogo.huang(a)mediatek.corp-partner.google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: agogo <agogo.huang(a)mediatek.corp-partner.google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Sat, 11 Jan 2025 14:57:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: util/cbfstool: Refine type and signatures
by Ariel Otilibili (Code Review) 11 Jan '25

11 Jan '25

Attention is currently required from: Elyes Haouas, Maximilian Brune, Shuo Liu. Hello Maximilian Brune, Shuo Liu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85786?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Code-Review+1 by Shuo Liu, Code-Review+2 by Maximilian Brune, Verified+1 by build bot (Jenkins) The change is no longer submittable: Code-Review and Verified are unsatisfied now. Change subject: util/cbfstool: Refine type and signatures ...................................................................... util/cbfstool: Refine type and signatures As suggested by the linter: > Prefer 'unsigned long' over 'unsigned long int' as the int is > unnecessary In fmap_bsearch(), offset being negative, changed its type to 'long', and the return value of to 'long'. fmap_find() uses the return value of fmap_bsearch(); and is declared as 'long int'. Per the linter warnings, replaced 'long int' by 'long'. > Prefer 'long' over 'long int' as the int is unnecessary Link: https://qa.coreboot.org/job/coreboot-untested-files/lastSuccessfulBuild/art… Cc: Nico Huber <nico.h(a)gmx.de> Cc: Julius Werner <jwerner(a)chromium.org> Cc: "Jérémy Compostella" <jeremy.compostella(a)intel.com> Cc: Ron Minnich <rminnich(a)gmail.com> Cc: Shuo Liu <shuo.liu(a)intel.com> Cc: Arthur Heymans <arthur(a)aheymans.xyz> Cc: Patrick Georgi <patrick(a)coreboot.org> Cc: Elyes Haouas <ehaouas(a)noos.fr> Change-Id: If94e70778d0302552f151c31d3073524162faf9e Signed-off-by: Ariel Otilibili <otilibil(a)eurecom.fr> --- M util/cbfstool/cbfstool.c M util/cbfstool/flashmap/fmap.c 2 files changed, 9 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/85786/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85786?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If94e70778d0302552f151c31d3073524162faf9e Gerrit-Change-Number: 85786 Gerrit-PatchSet: 2 Gerrit-Owner: Ariel Otilibili Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Patrick Georgi <patrick(a)coreboot.org> Gerrit-CC: Shuo Liu <shuo.liu(a)intel.com> Gerrit-CC: ron minnich <rminnich(a)gmail.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr>

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[S] Change in coreboot[main]: util/cbfstool: Replace 'unsigned long int' by 'unsigned long'
by Ariel Otilibili (Code Review) 11 Jan '25

11 Jan '25

Attention is currently required from: Elyes Haouas. Ariel Otilibili has posted comments on this change by Ariel Otilibili. ( https://review.coreboot.org/c/coreboot/+/85786?usp=email ) Change subject: util/cbfstool: Replace 'unsigned long int' by 'unsigned long' ...................................................................... Patch Set 1: (1 comment) File util/cbfstool/flashmap/fmap.c: https://review.coreboot.org/c/coreboot/+/85786/comment/83ac4744_c01d5a5c?us… : PS1, Line 99: unsigned long offset = -1; > If it is unsigned, how it is = -1 ? Indeed, Elyes; thanks for the feedback. I am pushing a new version, improving on your comment. -- To view, visit https://review.coreboot.org/c/coreboot/+/85786?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If94e70778d0302552f151c31d3073524162faf9e Gerrit-Change-Number: 85786 Gerrit-PatchSet: 1 Gerrit-Owner: Ariel Otilibili Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Patrick Georgi <patrick(a)coreboot.org> Gerrit-CC: ron minnich <rminnich(a)gmail.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Sat, 11 Jan 2025 14:54:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Elyes Haouas <ehaouas(a)noos.fr>

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[XS] Change in coreboot[main]: intel/fsp1_1: Replace 'unsigned long int' by 'unsigned long'
by Ariel Otilibili (Code Review) 11 Jan '25

11 Jan '25

Ariel Otilibili has posted comments on this change by Ariel Otilibili. ( https://review.coreboot.org/c/coreboot/+/85783?usp=email ) Change subject: intel/fsp1_1: Replace 'unsigned long int' by 'unsigned long' ...................................................................... Patch Set 1: (1 comment) File src/drivers/intel/fsp1_1/raminit.c: https://review.coreboot.org/c/coreboot/+/85783/comment/ca64144c_d6a87c42?us… : PS1, Line 131: } > Wondering if this cast is needed Hello Elyes, Thanks for having looked the patch. It seems so, fsp_reserved_bytes was declared as u32 [1], and depending the host, unsigned long and u32 may have different lengths [2]. [1] https://github.com/coreboot/coreboot/blob/aba7f44ecd3925c91f4249e03024af134… [2] https://michas.eu/blog/c_ints.php?lang=en -- To view, visit https://review.coreboot.org/c/coreboot/+/85783?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I940528dc4f8cb9b2d441d0f0d181cccebd315255 Gerrit-Change-Number: 85783 Gerrit-PatchSet: 1 Gerrit-Owner: Ariel Otilibili Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 11 Jan 2025 14:52:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Elyes Haouas <ehaouas(a)noos.fr>

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[M] Change in coreboot[main]: soc/mediatek/mt8196: Initialize MCUPM
by Yidi Lin (Code Review) 11 Jan '25

11 Jan '25

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[M] Change in coreboot[main]: soc/mediatek/mt8196: Initialize MCUPM
by Jarried Lin (Code Review) 11 Jan '25

11 Jan '25

Attention is currently required from: Hung-Te Lin, Yidi Lin, Yu-Ping Wu, agogo. Jarried Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85888?usp=email ) Change subject: soc/mediatek/mt8196: Initialize MCUPM ...................................................................... Patch Set 3: (14 comments) File src/soc/mediatek/mt8196/include/soc/mcupm_plat.h: https://review.coreboot.org/c/coreboot/+/85888/comment/b9b9e21f_ea077392?us… : PS2, Line 42: 1b > What does this mean? Done https://review.coreboot.org/c/coreboot/+/85888/comment/986ddc02_dcc92cd4?us… : PS2, Line 70: REPLACE_15 > Please define a meaningful name. […] Done https://review.coreboot.org/c/coreboot/+/85888/comment/4574c315_221df424?us… : PS2, Line 84: SIZE > Is this supposed to be `NUM`? From the comment, this is the number of slots, not the size of a slot. Done https://review.coreboot.org/c/coreboot/+/85888/comment/afd41235_aece24fb?us… : PS2, Line 93: 0x1000BC7C > What does this stand for? Done File src/soc/mediatek/mt8196/mcupm.c: https://review.coreboot.org/c/coreboot/+/85888/comment/62ae361f_d53a9d4f?us… : PS1, Line 9: #include <stdlib.h> > `#include <console/console. […] Done https://review.coreboot.org/c/coreboot/+/85888/comment/e346dca3_1b59fdbf?us… : PS1, Line 39: /* set CPUEB_STATE_VALID = 1 */ : setbits32p(SPM_MCUPM_SPMC_CON, CPUEB_STATE_VALID); : : /* polling CPUEB_STATE_FINISH_ACK = 1 */ : if (!retry(POLLING_ACK_TIME, : (read32p(SPM_MCUPM_SPMC_CON) & CPUEB_STATE_FINISH_ACK) == : CPUEB_STATE_FINISH_ACK, udelay(1))) { : printk(BIOS_WARNING, : "[EB_SPMC] Polling ACK timeout, %#x\n", : read32p(SPM_MCUPM_SPMC_CON)); : return -1; : } : : /* set CPUEB_STATE_VALID = 0 */ : clrbits32p(SPM_MCUPM_SPMC_CON, CPUEB_STATE_VALID); : : /* polling CPUEB_STATE_FINISH_ACK = 0 */ : if (!retry(POLLING_ACK_TIME, : (read32p(SPM_MCUPM_SPMC_CON) & CPUEB_STATE_FINISH_ACK) != : CPUEB_STATE_FINISH_ACK, udelay(1))) { : printk(BIOS_WARNING, : "[EB_SPMC] Polling ACK timeout, %#x\n", : read32p(SPM_MCUPM_SPMC_CON)); : return -1; : } > How about […] Done File src/soc/mediatek/mt8196/mcupm.c: https://review.coreboot.org/c/coreboot/+/85888/comment/243f71f1_bd09745f?us… : PS2, Line 16: Polling > Poll Done https://review.coreboot.org/c/coreboot/+/85888/comment/a388b897_87df8b4c?us… : PS2, Line 20: WARNING > Should this be `ERR`? Done https://review.coreboot.org/c/coreboot/+/85888/comment/d79eb647_30635d5e?us… : PS2, Line 46: WARNING > ERR? Same below. Done https://review.coreboot.org/c/coreboot/+/85888/comment/a73266cb_c8727081?us… : PS2, Line 65: eb_sleep_protect > return eb_sleep_protect(); Done https://review.coreboot.org/c/coreboot/+/85888/comment/555bcc64_7706e476?us… : PS2, Line 81: %s: > Let's use `[EB_SPMC]` for consistency. Done https://review.coreboot.org/c/coreboot/+/85888/comment/3fcbf8fe_24161611?us… : PS2, Line 85: %s > remove Done https://review.coreboot.org/c/coreboot/+/85888/comment/eb0c0eb7_99b2ae8c?us… : PS2, Line 124: %s() > `%s:` Done https://review.coreboot.org/c/coreboot/+/85888/comment/3ff97bef_691e3ba1?us… : PS2, Line 127: %s() > `%s:` Done -- To view, visit https://review.coreboot.org/c/coreboot/+/85888?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I223f245d384f32d54f6170a28b29573638f77296 Gerrit-Change-Number: 85888 Gerrit-PatchSet: 3 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: agogo <agogo.huang(a)mediatek.corp-partner.google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: agogo <agogo.huang(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Sat, 11 Jan 2025 14:12:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: agogo <agogo.huang(a)mediatek.corp-partner.google.com> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com>

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[XS] Change in coreboot[main]: qualcomm/common: Remove dead code
by Ariel Otilibili (Code Review) 11 Jan '25

11 Jan '25

Ariel Otilibili has posted comments on this change by Ariel Otilibili. ( https://review.coreboot.org/c/coreboot/+/85778?usp=email ) Change subject: qualcomm/common: Remove dead code ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: Hello, any news on the patch? -- To view, visit https://review.coreboot.org/c/coreboot/+/85778?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I40cffcf3714decfc54f2bbce9d4a867a9313d72e Gerrit-Change-Number: 85778 Gerrit-PatchSet: 2 Gerrit-Owner: Ariel Otilibili Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Reviewer: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 11 Jan 2025 14:08:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[M] Change in coreboot[main]: soc/amd/glinda/cpu: Update cache info
by Angel Pons (Code Review) 11 Jan '25

11 Jan '25

Attention is currently required from: Jérémy Compostella, Naresh Solanki. Angel Pons has posted comments on this change by Naresh Solanki. ( https://review.coreboot.org/c/coreboot/+/85640?usp=email ) Change subject: soc/amd/glinda/cpu: Update cache info ...................................................................... Patch Set 3: Code-Review+1 (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/85640/comment/247c5d2e_09e7d9fd?us… : PS3, Line 8: Could you please describe why this had to be updated? I'm not familiar with the cache hierarchy on this platform. File src/soc/amd/glinda/cpu.c: https://review.coreboot.org/c/coreboot/+/85640/comment/b0ba9548_1dc6eb7a?us… : PS3, Line 66: memcpy(info, &info_list[0], sizeof(*info)); Out of curiosity, is this copy necessary? -- To view, visit https://review.coreboot.org/c/coreboot/+/85640?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I46947e8ac62c903036a81642e03201e353c3dac6 Gerrit-Change-Number: 85640 Gerrit-PatchSet: 3 Gerrit-Owner: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Comment-Date: Sat, 11 Jan 2025 13:36:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: arch/x86/cpu: Add element id to struct cpu_cache_info
by Angel Pons (Code Review) 11 Jan '25

11 Jan '25

Attention is currently required from: Jérémy Compostella, Naresh Solanki. Angel Pons has posted comments on this change by Naresh Solanki. ( https://review.coreboot.org/c/coreboot/+/85639?usp=email ) Change subject: arch/x86/cpu: Add element id to struct cpu_cache_info ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/85639?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I29002931b559a05756419e0c4ec5c78586d3c3a5 Gerrit-Change-Number: 85639 Gerrit-PatchSet: 1 Gerrit-Owner: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Comment-Date: Sat, 11 Jan 2025 13:36:26 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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coreboot-gerrit January 2025