coreboot-gerrit January 2025

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[S] Change in coreboot[main]: mb/*: Drop xhci_overcurrent_map II
by Patrick Rudolph (Code Review) 11 Jan '25

11 Jan '25

Attention is currently required from: Alexander Couzens, Keith Hui, Nicholas Chin. Patrick Rudolph has posted comments on this change by Keith Hui. ( https://review.coreboot.org/c/coreboot/+/85924?usp=email ) Change subject: mb/*: Drop xhci_overcurrent_map II ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: I used t530 as an example and the USB OC config matches. How did you test if there's a mismatch? -- To view, visit https://review.coreboot.org/c/coreboot/+/85924?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie60d34cae5ae94d148854b42f77ab4c02e8f49ef Gerrit-Change-Number: 85924 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Attention: Keith Hui <buurin(a)gmail.com> Gerrit-Comment-Date: Sat, 11 Jan 2025 09:02:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: sb/intel/bd82x6x: Apply EHCI mapping to xhci_overcurrent_mapping
by Patrick Rudolph (Code Review) 11 Jan '25

11 Jan '25

Attention is currently required from: Keith Hui. Patrick Rudolph has posted comments on this change by Keith Hui. ( https://review.coreboot.org/c/coreboot/+/85922?usp=email ) Change subject: sb/intel/bd82x6x: Apply EHCI mapping to xhci_overcurrent_mapping ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85922?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iab30a07c8df223e4053c5f28df5e5ed926f278f7 Gerrit-Change-Number: 85922 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Keith Hui <buurin(a)gmail.com> Gerrit-Comment-Date: Sat, 11 Jan 2025 08:56:52 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: Makefile: Add ctags target in Makefile
by Name of user not set (Code Review) 11 Jan '25

11 Jan '25

Attention is currently required from: Martin L Roth. Hello Martin L Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85936?usp=email to look at the new patch set (#2). Change subject: Makefile: Add ctags target in Makefile ...................................................................... Makefile: Add ctags target in Makefile Add 'ctags' target. we can see that 'make help' says ... ctags / ctags-project ... ... but, Makefile have only 'ctags-project' target. Change-Id: Ie554892bcb072d773babf745d7756630327d2975 Signed-off-by: melongmelong <knw0507(a)naver.com> --- M Makefile 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/85936/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85936?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie554892bcb072d773babf745d7756630327d2975 Gerrit-Change-Number: 85936 Gerrit-PatchSet: 2 Gerrit-Owner: Name of user not set #1005756 Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com>

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[XS] Change in coreboot[main]: Makefile: Add ctags target in Makefile
by Name of user not set (Code Review) 11 Jan '25

11 Jan '25

Name of user not set #1005756 has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85936?usp=email ) Change subject: Makefile: Add ctags target in Makefile ...................................................................... Makefile: Add ctags target in Makefile Add 'ctags' target. we can see that 'make help' says ... ctags / ctags-project - Make ctags file for all of coreboot or current board ... but, Makefile have only 'ctags-project' target. Change-Id: Ie554892bcb072d773babf745d7756630327d2975 Signed-off-by: melongmelong <knw0507(a)naver.com> --- M Makefile 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/85936/1 diff --git a/Makefile b/Makefile index 5e45e16..49c19cb 100644 --- a/Makefile +++ b/Makefile @@ -486,6 +486,9 @@ cat $(obj)/project_filelist.txt | \ xargs ctags -o tags +ctags: + ctags -R + cscope-project: clean-cscope $(obj)/project_filelist.txt cat $(obj)/project_filelist.txt | xargs cscope -b -- To view, visit https://review.coreboot.org/c/coreboot/+/85936?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie554892bcb072d773babf745d7756630327d2975 Gerrit-Change-Number: 85936 Gerrit-PatchSet: 1 Gerrit-Owner: Name of user not set #1005756

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[XS] Change in coreboot[main]: soc/mediatek/mt8186/rtc: Remove unused variable "sw"
by Yidi Lin (Code Review) 11 Jan '25

11 Jan '25

Yidi Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85921?usp=email ) Change subject: soc/mediatek/mt8186/rtc: Remove unused variable "sw" ...................................................................... soc/mediatek/mt8186/rtc: Remove unused variable "sw" The function rtc_get_frequency_meter() already uses the wait_us() macro, so the stopwatch variable "sw" is not needed. Change-Id: I7e282b6ce881f4e8f9d5e1c92803fda363fe28d7 Signed-off-by: Yu-Ping Wu <yupingso(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85921 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yidi Lin <yidilin(a)google.com> --- M src/soc/mediatek/mt8186/rtc.c 1 file changed, 0 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Yidi Lin: Looks good to me, approved diff --git a/src/soc/mediatek/mt8186/rtc.c b/src/soc/mediatek/mt8186/rtc.c index 056c65c..7bf5bc8 100644 --- a/src/soc/mediatek/mt8186/rtc.c +++ b/src/soc/mediatek/mt8186/rtc.c @@ -77,7 +77,6 @@ { u16 bbpu, osc32con; u16 fqmtr_busy, fqmtr_data, fqmtr_rst, fqmtr_tcksel; - struct stopwatch sw; rtc_read(RTC_BBPU, &bbpu); rtc_write(RTC_BBPU, bbpu | RTC_BBPU_KEY | RTC_BBPU_RELOAD); @@ -120,7 +119,6 @@ rtc_write(PMIC_RG_FQMTR_CON0, fqmtr_tcksel | PMIC_FQMTR_CON0_FQMTR_EN); udelay(100); - stopwatch_init_usecs_expire(&sw, FQMTR_TIMEOUT_US); /* FQMTR read until ready */ if (!wait_us(FQMTR_TIMEOUT_US, rtc_read(PMIC_RG_FQMTR_CON0, &fqmtr_busy) == 0 && -- To view, visit https://review.coreboot.org/c/coreboot/+/85921?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7e282b6ce881f4e8f9d5e1c92803fda363fe28d7 Gerrit-Change-Number: 85921 Gerrit-PatchSet: 3 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: mb/google/rauru: Initialize clkbuf and srclken in romstage
by Yidi Lin (Code Review) 11 Jan '25

11 Jan '25

Yidi Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85843?usp=email ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/google/rauru: Initialize clkbuf and srclken in romstage ...................................................................... mb/google/rauru: Initialize clkbuf and srclken in romstage BUG=b:317009620 TEST=Build pass. Check boot log: srclken: [INFO ] RG_CENTRAL_CFG1 : 0x104014e5 [INFO ] RG_CENTRAL_CFG2 : 0x1011 [INFO ] RG_CENTRAL_CFG3 : 0x400f [INFO ] RG_CENTRAL_CFG5 : 0x3bfc1761 [INFO ] RG_CENTRAL_CFG6_1 : 0xffffffff [INFO ] RG_CENTRAL_CFG6_2 : 0x110e clkbuf: [INFO ] clk_buf_dump_clkbuf_log: xo_buf_cw(0x79A ~ 0x7A6): [INFO ] 0xb9/0xb9/0x30/0x30/0x30/0x10/0x9/0x10/0x10/0x10/0x10/0x10/0x10 [INFO ] clk_buf_dump_clkbuf_log: xo_buf_vote(0x54C ~ 0x565): [INFO ] 0x1/0x280/0x0/0x0/0x0/0x0/0x2000/0x0/0x0/0x0/0x0/0x0/0x0/ Change-Id: I9a6f93d3ec27944bea72bbadf95a03a54a8a0662 Signed-off-by: ot_song fan <ot_song.fan(a)mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85843 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- M src/mainboard/google/rauru/romstage.c 1 file changed, 4 insertions(+), 0 deletions(-) Approvals: Yu-Ping Wu: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/google/rauru/romstage.c b/src/mainboard/google/rauru/romstage.c index f4de121..d82e152 100644 --- a/src/mainboard/google/rauru/romstage.c +++ b/src/mainboard/google/rauru/romstage.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <arch/stages.h> +#include <soc/clkbuf_ctl.h> #include <soc/emi.h> #include <soc/irq2axi.h> #include <soc/modem_power_ctrl.h> @@ -12,6 +13,7 @@ #include <soc/pcie.h> #include <soc/pll.h> #include <soc/pmif.h> +#include <soc/srclken_rc.h> static void raise_little_cpu_freq(void) { @@ -33,6 +35,8 @@ raise_little_cpu_freq(); mt6373_init(); mt6685_init(); + srclken_rc_init(); + clk_buf_init(); mtk_dram_init(); modem_power_down(); -- To view, visit https://review.coreboot.org/c/coreboot/+/85843?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9a6f93d3ec27944bea72bbadf95a03a54a8a0662 Gerrit-Change-Number: 85843 Gerrit-PatchSet: 6 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ot_song fan <ot_song.fan(a)mediatek.corp-partner.google.com>

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[L] Change in coreboot[main]: soc/mediatek/mt8196: Add srclken_rc drivers
by Yidi Lin (Code Review) 11 Jan '25

11 Jan '25

Yidi Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85842?usp=email ) Change subject: soc/mediatek/mt8196: Add srclken_rc drivers ...................................................................... soc/mediatek/mt8196: Add srclken_rc drivers MT8196 uses new RC mode with clk_buf driver, and needs srclken_rc to send PMRC_EN. PMRC_EN will collect the requirements of all users, such as MD, GPS, PCIE, NFC. TEST=Build pass. BUG=b:317009620 Signed-off-by: ot_song fan <ot_song.fan(a)mediatek.corp-partner.google.com> Change-Id: I40f8d2b12027955e6bd57b666e9f04c0116a0a93 Reviewed-on: https://review.coreboot.org/c/coreboot/+/85842 Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yidi Lin <yidilin(a)google.com> --- M src/soc/mediatek/mt8196/Makefile.mk M src/soc/mediatek/mt8196/include/soc/addressmap.h A src/soc/mediatek/mt8196/include/soc/srclken_rc.h A src/soc/mediatek/mt8196/srclken_rc.c 4 files changed, 801 insertions(+), 0 deletions(-) Approvals: Yidi Lin: Looks good to me, approved Yu-Ping Wu: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/mediatek/mt8196/Makefile.mk b/src/soc/mediatek/mt8196/Makefile.mk index 6ca25f9..a287949 100644 --- a/src/soc/mediatek/mt8196/Makefile.mk +++ b/src/soc/mediatek/mt8196/Makefile.mk @@ -44,6 +44,7 @@ romstage-y += ../common/pmif_clk.c pmif_clk.c romstage-y += ../common/pmif.c pmif_init.c romstage-y += pmif_spmi.c +romstage-y += srclken_rc.c ramstage-$(CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE) += ../common/bl31.c ramstage-y += ../common/dpm_v2.c diff --git a/src/soc/mediatek/mt8196/include/soc/addressmap.h b/src/soc/mediatek/mt8196/include/soc/addressmap.h index 3790c02..1ec3c86 100644 --- a/src/soc/mediatek/mt8196/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8196/include/soc/addressmap.h @@ -150,6 +150,7 @@ SPM_BASE = IO_PHYS + 0x0C004000, SPM_PBUS_BASE = IO_PHYS + 0x0C00D000, RGU_BASE = IO_PHYS + 0x0C010000, + RC_BASE = IO_PHYS + 0x0C011000, GPT_BASE = IO_PHYS + 0x0C015000, VLP_CKSYS_BASE = IO_PHYS + 0x0C016000, PMIF_SPMI_P_BASE = IO_PHYS + 0x0C018000, diff --git a/src/soc/mediatek/mt8196/include/soc/srclken_rc.h b/src/soc/mediatek/mt8196/include/soc/srclken_rc.h new file mode 100644 index 0000000..af880d7 --- /dev/null +++ b/src/soc/mediatek/mt8196/include/soc/srclken_rc.h @@ -0,0 +1,244 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ + +#ifndef __SOC_MEDIATEK_MT8196_INCLUDE_SOC_SRCLKEN_RC_H__ +#define __SOC_MEDIATEK_MT8196_INCLUDE_SOC_SRCLKEN_RC_H__ + +/* Channel id: Update this enum for porting */ +enum chn_id { + CHN_SUSPEND = 0, + CHN_MD1, + CHN_MD2, + CHN_MD3, + CHN_MDRF, + CHN_MMWAVE, + CHN_GPS, + CHN_PCIE_CONN1, + CHN_VCORE, + CHN_CONN_MCU, + CHN_COANT, + CHN_NFC_CONN2, + CHN_SUSPEND2, + CHN_UFS_VREQ, + CHN_DCXO_L, + CHN_DCXO_H, + CHN_UFS_2, + CHN_PCIE_2, + CHN_NFC_2, + CHN_EXT1, + CHN_EXT2, + CHN_EXT3, + CHN_T900, + CHN_RSV1, + CHN_RSV2, + CHN_RSV3, + CHN_RSV4, + CHN_RSV5, + CHN_RSV6, + CHN_RSV7, + CHN_RSV8, + CHN_RSV9, + MAX_CHN_NUM, +}; + +struct mtk_rc_regs { + u32 srclken_rc_cfg; + u32 rc_central_cfg1; + u32 rc_central_cfg2; + u32 rc_cmd_arb_cfg; + u32 rc_pmic_rcen_addr; + u32 rc_pmic_rcen_set_clr_addr; + u32 rc_dcxo_fpm_cfg; + u32 rc_central_cfg3; + u32 reserved1[14]; + u32 srclken_sw_con_cfg; + u32 rc_central_cfg4; + u32 reserved2; + u32 rc_debug_cfg; + u32 reserved3; + u32 reserved4; + u32 rc_central_cfg5; + u32 rc_central_cfg6; + u32 rcen_mt_m_cfg_0; + u32 rcen_mt_m_cfg_1; + u32 rcen_mt_p_cfg_0; + u32 rcen_mt_p_cfg_1; + u32 rcen_mt_cfg_0; + u32 reserved5[32]; + u32 rc_spi_sta_0; + u32 rc_pi_po_sta; + u32 reserved6[139]; + u32 central_cfg4_1; + u32 central_cfg6_1; + u32 central_cfg6_2; + u32 reserved7[39]; + u32 subsys_intf_cfg_fpm; + u32 reserved8[5]; + u32 src_pmrc_starter_bypass_cfg; + u32 src_pmrc_starter_disable_cfg; + u32 src_pmrc_multi_master_cfg; + u32 src_pmrc_starter_mask_cfg; + u32 src_pmrc_starter_turn_on_cnt_size; + u32 src_pmrc_starter_turn_off_cnt_size; + u32 reserved9[58]; + u32 rc_mxx_srclken_cfg[MAX_CHN_NUM]; + u32 rc_mxx_req_sta_0[MAX_CHN_NUM]; +}; + +check_member(mtk_rc_regs, rc_spi_sta_0, 0x10c); + +DEFINE_BIT(SW_RESET, 0) +DEFINE_BITFIELD(CG_32K_EN, 3, 1) +DEFINE_BIT(CG_FCLK_EN, 2) +DEFINE_BIT(CG_FCLK_FR_EN, 3) +DEFINE_BIT(MUX_FCLK_FR, 4) +DEFINE_BIT(RC_32K_DCM, 8) +DEFINE_BIT(SRCLKEN_RC_EN, 0) +DEFINE_BIT(RCEN_ISSUE_M, 1) +DEFINE_BIT(RC_SPI_ACTIVE, 2) +DEFINE_BIT(SRCLKEN_RC_EN_SEL, 3) +DEFINE_BITFIELD(VCORE_SETTLE_T, 7, 5) +DEFINE_BITFIELD(ULPOSC_SETTLE_T, 11, 8) +DEFINE_BITFIELD(NON_DCXO_SETTLE_T, 21, 12) +DEFINE_BITFIELD(DCXO_SETTLE_T, 31, 22) +DEFINE_BITFIELD(SRCVOLTEN_CTRL, 3, 0) +DEFINE_BITFIELD(VREQ_CTRL, 7, 4) +DEFINE_BIT(SRCVOLTEN_VREQ_SEL, 8) +DEFINE_BIT(SRCVOLTEN_VREQ_M, 9) +DEFINE_BIT(FORCE_SRCVOLTEN_OFF, 10) +DEFINE_BIT(FORCE_SRCVOLTEN_ON, 11) +DEFINE_BITFIELD(ULPOSC_CTRL_M, 15, 12) +DEFINE_BIT(FORCE_VCORE_RDY, 16) +DEFINE_BIT(FORCE_ULPOSC2ON, 17) +DEFINE_BIT(FORCE_ULPOSC_CLK_EN, 18) +DEFINE_BIT(FORCE_ULPOSC_ON, 19) +DEFINE_BIT(DIS_ULPOSC_RDY_CHK, 20) +DEFINE_BIT(PWRAP_SLP_CTRL_M, 21) +DEFINE_BIT(PWRAP_SLP_MUX_SEL, 25) +DEFINE_BIT(FORCE_PWRAP_ON, 26) +DEFINE_BIT(FORCE_PWRAP_AWK, 27) +DEFINE_BIT(NON_DCXO_REQ_FORCEON, 28) +DEFINE_BIT(NON_DCXO_REQ_FORCEOFF, 29) +DEFINE_BIT(DCXO_REQ_FORCEON, 30) +DEFINE_BIT(DCXO_REQ_FORCEOFF, 31) + +DEFINE_BITFIELD(SW_RC_EN, 12, 0) +DEFINE_BITFIELD(SW_RCEN_EN, 25, 13) +DEFINE_BIT(SW_DCXO_M_EN, 28) +DEFINE_BITFIELD(SW_DCXO_M, 31, 29) + +DEFINE_BITFIELD(DCXO_FPM_CTRL_M, 3, 0) +DEFINE_BIT(SRCVOLTEN_FPM_MSK_B, 4) +DEFINE_BITFIELD(SUB_SRCLKEN_FPM_MSK_B, 28, 16) + +DEFINE_BIT(TO_LPM_SETTLE_EN, 0) +DEFINE_BIT(BLK_SCP_DXCO_MD_TARGET, 1) +DEFINE_BIT(BLK_COANT_DXCO_MD_TARGET, 2) +DEFINE_BIT(TO_BBLPM_SETTLE_EN, 3) +DEFINE_BIT(TO_BBLPM_SETTLE_ND_EN, 4) +DEFINE_BITFIELD(TO_LPM_SETTLE_T, 21, 12) + +DEFINE_BIT(DCXO_SETTLE_BLK_EN, 1) +DEFINE_BIT(BYPASS_CMD_EN, 2) +DEFINE_BIT(SW_SRCLKEN_RC, 3) +DEFINE_BIT(SW_SRCLKEN_FPM, 4) +DEFINE_BIT(SW_SRCLKEN_BBLPM, 5) +DEFINE_BIT(XO_SOC_LINKAGE_EN, 6) +DEFINE_BIT(REQ_ACK_LOW_IMD_EN, 7) +DEFINE_BIT(SRCLKEN_TRACK_M_EN, 8) +DEFINE_BITFIELD(CNT_PRD_STEP, 11, 10) +DEFINE_BITFIELD(XO_STABLE_PRD, 21, 12) +DEFINE_BITFIELD(DCXO_STABLE_PRD, 31, 22) + +DEFINE_BIT(TACE_EN, 0) +DEFINE_BITFIELD(TIE_SYS_RDY, 4, 1) + +DEFINE_BITFIELD(KEEP_RC_SPI_ACTIVE, 12, 0) +DEFINE_BIT(PWRAP_VLD_FORCE, 16) +DEFINE_BIT(SLEEP_VLD_MODE, 17) +DEFINE_BIT(SCP_SLEEP_REQ_MODE, 18) +DEFINE_BIT(SLEEP_REQ_MODE, 20) +DEFINE_BIT(BYPASS_PMIF_M, 24) +DEFINE_BIT(BYPASS_PMIF_P, 25) + +DEFINE_BIT(TRACE_MODE_EN, 24) +DEFINE_BIT(DBG_STOP_PROT_EN, 28) + +DEFINE_BIT(SPMI_CMD_BYTE_CNT, 0) +DEFINE_BITFIELD(SPMI_M_SLV_ID, 8, 5) +DEFINE_BITFIELD(SPMI_P_SLV_ID, 12, 9) +DEFINE_BIT(SPMI_M_PMIF_ID, 17) +DEFINE_BIT(SPMI_P_PMIF_ID, 18) +DEFINE_BITFIELD(SPMI_M_CMD_TYPE, 21, 19) +DEFINE_BITFIELD(SPMI_P_CMD_TYPE, 22, 21) +DEFINE_BIT(SPMI_M_WRITE_EN, 23) +DEFINE_BIT(SPMI_P_WRITE_EN, 24) +DEFINE_BIT(BROADCAST_MODE_EN, 25) +DEFINE_BIT(MULTI_CMD_MODE_EN, 26) +DEFINE_BIT(DCXO_ENCODE, 27) +DEFINE_BIT(SPMI_M_FIRST, 28) +DEFINE_BIT(SPMI_BYTE_NUM, 29) +DEFINE_BITFIELD(REQ_TO_DCXO_MASK, 15, 0) +DEFINE_BITFIELD(PMIC_M_COUNTER_VAL, 3, 0) +DEFINE_BITFIELD(PMIC_P_COUNTER_VAL, 7, 4) +DEFINE_BITFIELD(SRCLKEN_FPM_MASK_B, 13, 0) +DEFINE_BITFIELD(SRCLKEN_BBLPM_MASK_B, 29, 16) +DEFINE_BIT(FPM_ACK, 1) +DEFINE_BIT(BBLPM_ACK, 3) +DEFINE_BITFIELD(BYPASS_DCXO_VOTE_H, 31, 16) +DEFINE_BITFIELD(BYPASS_DCXO_VOTE_L, 15, 0) + +enum { + SW_SRCLKEN_FPM_MSK = 0x1, + SW_SRCLKEN_BBLPM_MSK = 0x1, +}; + +/* RC_CENTRAL_CFG2[8] */ +#define SRCLKENAO_MODE 0 +#define VREQ_MODE 1 + +/* RC_CENTRAL_CFG2[25] */ +#define RC_32K 0 +#define RC_ULPOSC1 1 + +/* Signal Control Mode */ +#define MERGE_OR_MODE 0x0 +#define BYPASS_MODE 0x1 +#define MERGE_AND_MODE BIT(1) +#define BYPASS_RC_MODE (0x2 << 1) +#define BYPASS_OR_MODE 0x3 +#define BYPASS_OTHER_MODE (0x3 << 1) +#define ASYNC_MODE BIT(3) + +#define NO_REQ 0 +#define FPM_REQ BIT(4) +#define BBLPM_REQ BIT(5) + +enum rc_ctrl_m { + HW_MODE = 0, + SW_MODE = 1, +}; + +enum { + SRLCKEN_RC_BRINGUP = 0, + SRCLKEN_RC_DISABLE, + SRCLKEN_RC_ENABLE, + SRCLKEN_RC_SKIP, +}; + +struct subsys_rc_con { + u32 dcxo_prd; + u32 xo_prd; + u32 cnt_step; + u32 track_en; + u32 req_ack_imd_en; + u32 xo_soc_link_en; + u32 sw_bblpm; + u32 sw_fpm; + u32 sw_rc; + u32 bypass_cmd; + u32 dcxo_settle_blk_en; +}; + +int srclken_rc_init(void); + +#endif diff --git a/src/soc/mediatek/mt8196/srclken_rc.c b/src/soc/mediatek/mt8196/srclken_rc.c new file mode 100644 index 0000000..412858c --- /dev/null +++ b/src/soc/mediatek/mt8196/srclken_rc.c @@ -0,0 +1,555 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ + +#include <assert.h> +#include <console/console.h> +#include <delay.h> +#include <device/mmio.h> +#include <soc/addressmap.h> +#include <soc/clkbuf_ctl.h> +#include <soc/pmif.h> +#include <soc/pmif_common.h> +#include <soc/spmi.h> +#include <soc/srclken_rc.h> +#include <timer.h> + +static struct mtk_rc_regs *rc_regs = (struct mtk_rc_regs *)RC_BASE; + +#define ACK_DELAY_US 10 +#define ACK_DELAY_TIMES 200 + +/* RC_CENTRAL_CFG1 setting */ +#define RC_CENTRAL_ENABLE_VAL 1 +#define RC_CENTRAL_DISABLE_VAL 0 + +/* register direct write */ +#define IS_SPI2PMIC_SET_CLR_VAL 0 +#define KEEP_RC_SPI_ACTIVE_VAL 1 +#define SRCLKEN_RC_EN_SEL_VAL 0 + +/* RC_CENTRAL_CFG1 settle time setting */ +#define VCORE_SETTLE_TIME_VAL 0x7 /* ~= 200us */ +#define ULPOSC_SETTLE_TIME_VAL 0x4 /* ~= ? 150us */ +#define NON_DCXO_SETTLE_TIME_VAL 0x1 /* 2^(step+5)*0x33*30.77ns ~= 400us */ +#define DCXO_SETTLE_TIME_VAL 0x41 /* 2^(step+5)*0x87*30.77ns ~= 1063us */ + +/* RC_CENTRAL_CFG2 setting */ +/* use srlckenao to set vcore */ +#define SPI_TRIG_MODE SRCLKENAO_MODE +/* release vcore when spi request done */ +#define IS_SPI_DONE_RELEASE 0 +/* pmic spec under 200us */ +#define SPI_CLK_SRC RC_32K +/* RC_CENTRAL_CFG2 control mode */ +/* merge with spm */ +#define SRCLKENO_0_CTRL_M BYPASS_MODE +/* merge with vreq */ +#define VREQ_CTRL_M BYPASS_MODE +/* merge with ulposc */ +#define ULPOSC_CTRL_M_VAL BYPASS_MODE +/* merge with pwrap_scp */ +#define PWRAP_CTRL_M MERGE_OR_MODE + +/* RC_DCXO_FPM_CFG*/ +#define MD0_SRCLKENO_0_MASK_B 0 /* md0 control by pmrc */ +#define FULL_SET_HW_MODE 0 /* dcxo mode use pmrc_en */ +/* RC_DCXO_FPM_CFG control mode*/ +/* merge with spm */ +#define DCXO_FPM_CTRL_MODE (MERGE_OR_MODE | ASYNC_MODE) + +/* RC_CENTRAL_CFG5 */ +#define RC_SPMI_BYTE_LEN 0x1 /* 0: 2bytes, 1: 2 * 2bytes */ +#define PMIC_GROUP_ID 0xB + +/* pmrc_en address */ +/* default use this reg direct write */ +#define PMRC_CON0 0x190 +#define PMRC_CON0_SET 0x198 +#define PMRC_CON0_CLR 0x19A + +enum { + SW_BBLPM_LOW, + SW_BBLPM_HIGH, +}; + +enum { + SW_FPM_LOW, + SW_FPM_HIGH, +}; + +enum { + DXCO_SETTLE_BLK_DIS, + DXCO_SETTLE_BLK_EN, +}; + +enum { + REQ_ACK_IMD_DIS, + REQ_ACK_IMD_EN, +}; + +#define SUB_CTRL_CON(_id, _dcxo_prd, _xo_prd, \ + _sw_bblpm, _sw_fpm, _sw_rc, \ + _req_ack_imd_en, _bypass_cmd, \ + _dcxo_settle_blk_en) \ + [_id] = { \ + .dcxo_prd = _dcxo_prd, \ + .xo_prd = _xo_prd, \ + .cnt_step = CENTROL_CNT_STEP, \ + .track_en = 0, \ + .req_ack_imd_en = _req_ack_imd_en, \ + .xo_soc_link_en = 0, \ + .sw_bblpm = _sw_bblpm, \ + .sw_fpm = _sw_fpm, \ + .sw_rc = _sw_rc, \ + .bypass_cmd = _bypass_cmd, \ + .dcxo_settle_blk_en = _dcxo_settle_blk_en, \ + } + +/* Init as SW FPM mode */ +#define SUB_CTRL_CON_INIT(_id, _dcxo_prd, _xo_prd, \ + _req_ack_imd_en, _bypass_cmd, \ + _dcxo_settle_blk_en) \ + SUB_CTRL_CON(_id, _dcxo_prd, _xo_prd, \ + SW_BBLPM_LOW, SW_FPM_HIGH, SW_MODE, \ + _req_ack_imd_en, _bypass_cmd, \ + _dcxo_settle_blk_en) + +/* Init as SW LPM mode */ +#define SUB_CTRL_CON_NO_INIT(_id, _dcxo_prd, _xo_prd, \ + _req_ack_imd_en, _bypass_cmd, \ + _dcxo_settle_blk_en) \ + SUB_CTRL_CON(_id, _dcxo_prd, _xo_prd, \ + SW_BBLPM_LOW, SW_FPM_LOW, SW_MODE, \ + _req_ack_imd_en, _bypass_cmd, \ + _dcxo_settle_blk_en) + +/* Normal init, SW FPM mode */ +#define SUB_CTRL_CON_EN(_id, _xo_prd, _req_ack_imd_en) \ + SUB_CTRL_CON_INIT(_id, \ + DCXO_STABLE_TIME, _xo_prd, \ + _req_ack_imd_en, 0, DXCO_SETTLE_BLK_EN) + +/* XO/DCXO settle time=0, bypass cmd */ +#define SUB_CTRL_CON_DIS(_id) \ + SUB_CTRL_CON_INIT(_id, \ + DCXO_STABLE_TIME, 0, REQ_ACK_IMD_EN, \ + 0x1, DXCO_SETTLE_BLK_DIS) + +/* Normal init, SW LPM mode */ +#define SUB_CTRL_CON_UNUSE(_id) \ + SUB_CTRL_CON_NO_INIT(_id, \ + DCXO_STABLE_TIME, XO_DEFAULT_STABLE_TIME, \ + REQ_ACK_IMD_EN, 0, DXCO_SETTLE_BLK_EN) + +/* Porting starting from here */ +/* MXX_SRCLKEN_CFG settle time setting */ +#define CENTROL_CNT_STEP 0x3 /* Fix in 3 */ +#define DCXO_STABLE_TIME 0x70 /* ~= 700us */ +#define XO_DEFAULT_STABLE_TIME 0x29 /* ~= 400us */ +#define XO_MD0_STABLE_TIME 0x15 /* ~= 200us */ +#define XO_MD1_STABLE_TIME 0x15 /* ~= 200us */ +#define XO_MD2_STABLE_TIME 0x33 /* ~= 500us */ +#define XO_MDRF_STABLE_TIME 0x3D /* ~= 600us */ +#define VCORE_STABLE_TIME 0x15 /* ~= 200us */ + +/* SUBSYS_INTF_CFG_FPM */ +#define SUB_FPM_SET (BIT(CHN_SUSPEND) | BIT(CHN_MD1) | \ + BIT(CHN_MD2) | BIT(CHN_MD3) | \ + BIT(CHN_MDRF) | BIT(CHN_MMWAVE) | \ + BIT(CHN_GPS) | BIT(CHN_PCIE_CONN1) | \ + BIT(CHN_VCORE) | BIT(CHN_CONN_MCU) | \ + BIT(CHN_COANT) | BIT(CHN_NFC_CONN2) | \ + BIT(CHN_SUSPEND2) | BIT(CHN_UFS_VREQ)) + +/* CFG6_1, all 1 means RC M & P used */ +#define REQ_TO_SPMI_P_SUBSYS 0xFFFFFFFF +/* subsys 8-vcore on/off & subsys 11-pmic power not join DCXO vote*/ +#define SUBSYS_EN_L 0x110E +#define SUBSYS_EN_H 0x0000 + +/* First try to switch fpm. After polling ack done, switch to HW mode */ +static const struct { + bool disabled; + bool lpm; + bool hw_mode; +} rc_config[MAX_CHN_NUM] = { + [CHN_SUSPEND] = { .lpm = false, .hw_mode = true }, + [CHN_MD1] = { .lpm = false, .hw_mode = true }, + [CHN_MD2] = { .lpm = false, .hw_mode = true }, + [CHN_MD3] = { .lpm = false, .hw_mode = true }, + [CHN_MDRF] = { .lpm = false, .hw_mode = true }, + [CHN_MMWAVE] = { .lpm = false, .hw_mode = true }, + [CHN_GPS] = { .lpm = true, .hw_mode = true }, + [CHN_PCIE_CONN1] = { .lpm = false, .hw_mode = true }, + [CHN_VCORE] = { .lpm = true, .hw_mode = false }, + [CHN_CONN_MCU] = { .lpm = true, .hw_mode = true }, + [CHN_COANT] = { .lpm = true, .hw_mode = true }, + [CHN_NFC_CONN2] = { .lpm = true, .hw_mode = true }, + [CHN_SUSPEND2] = { .lpm = false, .hw_mode = true }, + [CHN_UFS_VREQ] = { .lpm = false, .hw_mode = true }, + [CHN_DCXO_L] = { .disabled = true }, + [CHN_DCXO_H] = { .disabled = true }, + [CHN_UFS_2] = {}, + [CHN_PCIE_2] = {}, + [CHN_NFC_2] = {}, + [CHN_EXT1] = {}, + [CHN_EXT2] = {}, + [CHN_EXT3] = {}, + [CHN_T900] = {}, + [CHN_RSV1] = {}, + [CHN_RSV2] = {}, + [CHN_RSV3] = {}, + [CHN_RSV4] = {}, + [CHN_RSV5] = {}, + [CHN_RSV6] = {}, + [CHN_RSV7] = {}, + [CHN_RSV8] = {}, + [CHN_RSV9] = {}, +}; + +static const struct subsys_rc_con rc_ctrl[MAX_CHN_NUM] = { + SUB_CTRL_CON_EN(CHN_SUSPEND, XO_DEFAULT_STABLE_TIME, REQ_ACK_IMD_EN), + /* CFG[2] = 0x1 for bypass waiting DCXO settle time */ + /* Usually also need to set CFG6_2 not involve FPM vote */ + SUB_CTRL_CON_INIT(CHN_MD1, DCXO_STABLE_TIME, XO_MD0_STABLE_TIME, REQ_ACK_IMD_EN, + 0x1, DXCO_SETTLE_BLK_EN), + SUB_CTRL_CON_INIT(CHN_MD2, DCXO_STABLE_TIME, XO_MD1_STABLE_TIME, REQ_ACK_IMD_EN, + 0x1, DXCO_SETTLE_BLK_EN), + SUB_CTRL_CON_INIT(CHN_MD3, DCXO_STABLE_TIME, XO_MD2_STABLE_TIME, REQ_ACK_IMD_EN, + 0x1, DXCO_SETTLE_BLK_EN), + SUB_CTRL_CON_EN(CHN_MDRF, XO_MDRF_STABLE_TIME, REQ_ACK_IMD_EN), + SUB_CTRL_CON_EN(CHN_MMWAVE, XO_DEFAULT_STABLE_TIME, REQ_ACK_IMD_EN), + SUB_CTRL_CON_EN(CHN_GPS, XO_DEFAULT_STABLE_TIME, REQ_ACK_IMD_EN), + SUB_CTRL_CON_EN(CHN_PCIE_CONN1, XO_DEFAULT_STABLE_TIME, REQ_ACK_IMD_EN), + SUB_CTRL_CON_INIT(CHN_VCORE, DCXO_STABLE_TIME, VCORE_STABLE_TIME, REQ_ACK_IMD_EN, + 0x1, DXCO_SETTLE_BLK_EN), + SUB_CTRL_CON_EN(CHN_CONN_MCU, XO_DEFAULT_STABLE_TIME, REQ_ACK_IMD_EN), + SUB_CTRL_CON_DIS(CHN_COANT), + SUB_CTRL_CON_EN(CHN_NFC_CONN2, XO_DEFAULT_STABLE_TIME, REQ_ACK_IMD_EN), + SUB_CTRL_CON_INIT(CHN_SUSPEND2, DCXO_STABLE_TIME, VCORE_STABLE_TIME, REQ_ACK_IMD_EN, + 0x1, DXCO_SETTLE_BLK_EN), + SUB_CTRL_CON_EN(CHN_UFS_VREQ, XO_DEFAULT_STABLE_TIME, REQ_ACK_IMD_EN), + SUB_CTRL_CON_DIS(CHN_DCXO_L), + SUB_CTRL_CON_DIS(CHN_DCXO_H), + SUB_CTRL_CON_UNUSE(CHN_UFS_2), + SUB_CTRL_CON_UNUSE(CHN_PCIE_2), + SUB_CTRL_CON_UNUSE(CHN_NFC_2), + SUB_CTRL_CON_UNUSE(CHN_EXT1), + SUB_CTRL_CON_UNUSE(CHN_EXT2), + SUB_CTRL_CON_UNUSE(CHN_EXT3), + SUB_CTRL_CON_UNUSE(CHN_T900), + SUB_CTRL_CON_UNUSE(CHN_RSV1), + SUB_CTRL_CON_UNUSE(CHN_RSV2), + SUB_CTRL_CON_UNUSE(CHN_RSV3), + SUB_CTRL_CON_UNUSE(CHN_RSV4), + SUB_CTRL_CON_UNUSE(CHN_RSV5), + SUB_CTRL_CON_UNUSE(CHN_RSV6), + SUB_CTRL_CON_UNUSE(CHN_RSV7), + SUB_CTRL_CON_UNUSE(CHN_RSV8), + SUB_CTRL_CON_UNUSE(CHN_RSV9) +}; + +static void rc_dump_reg_info(void) +{ + u32 ch; + + printk(BIOS_INFO, "RG_DEBUG_CFG[24] : %#lx\n", + (read32(&rc_regs->rc_debug_cfg) & BIT(24)) >> 24); + printk(BIOS_INFO, "RG_SRCLKEN_RC_CFG : %#x\n", read32(&rc_regs->srclken_rc_cfg)); + + for (ch = 0; ch < MAX_CHN_NUM; ch++) { + if (rc_config[ch].disabled) + continue; + printk(BIOS_INFO, "RG_M0%d_SRCLKEN_CFG : %#x\n", + ch, read32(&rc_regs->rc_mxx_srclken_cfg[ch])); + } + + printk(BIOS_INFO, "RG_SRCLKEN_SW_CON_CFG : %#x\n", + read32(&rc_regs->srclken_sw_con_cfg)); + printk(BIOS_INFO, "RG_PMIC_RCEN_ADDR : %#x\n", read32(&rc_regs->rc_pmic_rcen_addr)); + printk(BIOS_INFO, "RG_PMIC_RCEN_SET_CLR_ADDR : %#x\n", + read32(&rc_regs->rc_pmic_rcen_set_clr_addr)); + printk(BIOS_INFO, "RG_CMD_ARB_CFG : %#x\n", read32(&rc_regs->rc_cmd_arb_cfg)); + printk(BIOS_INFO, "RG_CENTRAL_CFG1 : %#x\n", read32(&rc_regs->rc_central_cfg1)); + printk(BIOS_INFO, "RG_CENTRAL_CFG2 : %#x\n", read32(&rc_regs->rc_central_cfg2)); + printk(BIOS_INFO, "RG_CENTRAL_CFG3 : %#x\n", read32(&rc_regs->rc_central_cfg3)); + printk(BIOS_INFO, "RG_CENTRAL_CFG5 : %#x\n", read32(&rc_regs->rc_central_cfg5)); + printk(BIOS_INFO, "RG_CENTRAL_CFG6_1 : %#x\n", read32(&rc_regs->central_cfg6_1)); + printk(BIOS_INFO, "RG_CENTRAL_CFG6_2 : %#x\n", read32(&rc_regs->central_cfg6_2)); + printk(BIOS_INFO, "RG_DCXO_FPM_CFG : %#x\n", read32(&rc_regs->rc_dcxo_fpm_cfg)); + printk(BIOS_INFO, "SUBSYS_INTF_CFG_FPM : %#x\n", + read32(&rc_regs->subsys_intf_cfg_fpm)); + printk(BIOS_INFO, "RG_CENTRAL_CFG4 : %#x\n", read32(&rc_regs->rc_central_cfg4)); + printk(BIOS_INFO, "RG_CENTRAL_CFG4_1 : %#x\n", read32(&rc_regs->central_cfg4_1)); + printk(BIOS_INFO, "RG_SRC_PMIC_MULTI_MASTER_CFG : %#x\n", + read32(&rc_regs->src_pmrc_multi_master_cfg)); + printk(BIOS_INFO, "RG_SRC_PMRC_STARTER_DISABLE_CFG : %#x\n", + read32(&rc_regs->src_pmrc_starter_disable_cfg)); + printk(BIOS_INFO, "RG_SRC_PMRC_STARTER_MASK_CFG : %#x\n", + read32(&rc_regs->src_pmrc_starter_mask_cfg)); + printk(BIOS_INFO, "RG_SRC_PMRC_STARTER_BYPASS_CFG : %#x\n", + read32(&rc_regs->src_pmrc_starter_bypass_cfg)); + printk(BIOS_INFO, "RG_SRC_PMRC_STARTER_TURN_ON_CNT_SIZE : %#x\n", + read32(&rc_regs->src_pmrc_starter_turn_on_cnt_size)); + printk(BIOS_INFO, "RG_SRC_PMRC_STARTER_TURN_OFF_CNT_SIZE : %#x\n", + read32(&rc_regs->src_pmrc_starter_turn_off_cnt_size)); + printk(BIOS_INFO, "RC_SPI_STA_0:%#x\n", read32(&rc_regs->rc_spi_sta_0)); + printk(BIOS_INFO, "RC_PI_PO_STA:%#x\n", read32(&rc_regs->rc_pi_po_sta)); +} + +/* RC initial flow and relative setting */ +static void rc_ctrl_mode_switch(enum chn_id id, enum rc_ctrl_m mode) +{ + assert(id < MAX_CHN_NUM); + + switch (mode) { + case SW_MODE: + SET32_BITFIELDS(&rc_regs->rc_mxx_srclken_cfg[id], SW_SRCLKEN_RC, 1); + break; + case HW_MODE: + SET32_BITFIELDS(&rc_regs->rc_mxx_srclken_cfg[id], SW_SRCLKEN_RC, 0); + break; + default: + return; + } + + printk(BIOS_INFO, "M0%d: %#x\n", id, read32(&rc_regs->rc_mxx_srclken_cfg[id])); +} + +/* RC subsys FPM control*/ +static void rc_ctrl_fpm_switch(enum chn_id id, u32 mode) +{ + assert(id < MAX_CHN_NUM); + assert(mode == SW_FPM_HIGH || mode == SW_FPM_LOW); + + int fpm = (mode == SW_FPM_HIGH) ? 1 : 0; + SET32_BITFIELDS(&rc_regs->rc_mxx_srclken_cfg[id], SW_SRCLKEN_FPM, fpm); + + printk(BIOS_INFO, "M0%d FPM SWITCH: %#x\n", id, + read32(&rc_regs->rc_mxx_srclken_cfg[id])); +} + +static void rc_ctrl_mode_init(void) +{ + u32 ch; + const struct subsys_rc_con *rc_ctrl_ch; + + for (ch = 0; ch < MAX_CHN_NUM; ch++) { + if (rc_config[ch].disabled) + continue; + rc_ctrl_ch = &rc_ctrl[ch]; + SET32_BITFIELDS(&rc_regs->rc_mxx_srclken_cfg[ch], + DCXO_SETTLE_BLK_EN, rc_ctrl_ch->dcxo_settle_blk_en, + BYPASS_CMD_EN, rc_ctrl_ch->bypass_cmd, + SW_SRCLKEN_RC, rc_ctrl_ch->sw_rc, + SW_SRCLKEN_FPM, rc_ctrl_ch->sw_fpm, + SW_SRCLKEN_BBLPM, rc_ctrl_ch->sw_bblpm, + XO_SOC_LINKAGE_EN, rc_ctrl_ch->xo_soc_link_en, + REQ_ACK_LOW_IMD_EN, rc_ctrl_ch->req_ack_imd_en, + SRCLKEN_TRACK_M_EN, rc_ctrl_ch->track_en, + CNT_PRD_STEP, rc_ctrl_ch->cnt_step, + XO_STABLE_PRD, rc_ctrl_ch->xo_prd, + DCXO_STABLE_PRD, rc_ctrl_ch->dcxo_prd); + } +} + +static void rc_init_subsys_lpm(void) +{ + u32 ch; + + for (ch = 0; ch < MAX_CHN_NUM; ch++) { + if (rc_config[ch].disabled) + continue; + if (rc_config[ch].lpm) + rc_ctrl_fpm_switch(ch, SW_FPM_LOW); + } +} + +static void rc_init_subsys_hw_mode(void) +{ + u32 ch; + + for (ch = 0; ch < MAX_CHN_NUM; ch++) { + if (rc_config[ch].disabled) + continue; + if (rc_config[ch].hw_mode) + rc_ctrl_mode_switch(ch, HW_MODE); + } +} + +static int polling_rc_chn_ack(enum chn_id id, u32 mask, u32 value) +{ + if (!retry(ACK_DELAY_TIMES, + (read32(&rc_regs->rc_mxx_req_sta_0[id]) & mask) == value, + udelay(ACK_DELAY_US))) { + printk(BIOS_ERR, "%s: polling M%u status fail(R:%#x)(C:%#x)(PMRC:%#x)\n", + __func__, id, read32(&rc_regs->rc_mxx_req_sta_0[id]), + read32(&rc_regs->rc_mxx_srclken_cfg[id]), clk_buf_get_pmrc_en0()); + return -1; + } + + return 0; +} + +int srclken_rc_init(void) +{ + u32 ch; + u32 fpm; + u32 state; + u32 mask; + + /* Enable srclken_rc debug trace */ + SET32_BITFIELDS(&rc_regs->rc_debug_cfg, TRACE_MODE_EN, 0x1); + + /* Set SW RESET 1 */ + SET32_BITFIELDS(&rc_regs->srclken_rc_cfg, SW_RESET, 0x1); + udelay(100); + + /* Set SW CG 1 */ + SET32_BITFIELDS(&rc_regs->srclken_rc_cfg, CG_32K_EN, 0x7); + udelay(100); + + /* Set Clock Mux*/ + SET32_BITFIELDS(&rc_regs->srclken_rc_cfg, MUX_FCLK_FR, 0x1); + + /* Set req_filter m00~m13 as default SW_FPM */ + rc_ctrl_mode_init(); + + /* Enable sw trace & pmrc_o0 sel */ + SET32_BITFIELDS(&rc_regs->srclken_sw_con_cfg, TACE_EN, 0x1); + SET32_BITFIELDS(&rc_regs->srclken_sw_con_cfg, TIE_SYS_RDY, 0x1); + + /* Set PMIC addr for SPI CMD */ + write32(&rc_regs->rc_pmic_rcen_addr, PMRC_CON0); + + write32(&rc_regs->rc_pmic_rcen_set_clr_addr, PMRC_CON0); + + write32(&rc_regs->rc_cmd_arb_cfg, 0); + + /* CFG1 setting for spi cmd config */ + WRITE32_BITFIELDS(&rc_regs->rc_central_cfg1, + DCXO_SETTLE_T, DCXO_SETTLE_TIME_VAL, + NON_DCXO_SETTLE_T, NON_DCXO_SETTLE_TIME_VAL, + ULPOSC_SETTLE_T, ULPOSC_SETTLE_TIME_VAL, + VCORE_SETTLE_T, VCORE_SETTLE_TIME_VAL, + SRCLKEN_RC_EN_SEL, SRCLKEN_RC_EN_SEL_VAL, + RC_SPI_ACTIVE, KEEP_RC_SPI_ACTIVE_VAL, + RCEN_ISSUE_M, IS_SPI2PMIC_SET_CLR_VAL, + SRCLKEN_RC_EN, RC_CENTRAL_DISABLE_VAL); + + /* CFG2 setting for signal mode of each control mux */ + WRITE32_BITFIELDS(&rc_regs->rc_central_cfg2, + PWRAP_SLP_MUX_SEL, SPI_CLK_SRC, + PWRAP_SLP_CTRL_M, PWRAP_CTRL_M, + ULPOSC_CTRL_M, ULPOSC_CTRL_M_VAL, + SRCVOLTEN_VREQ_M, IS_SPI_DONE_RELEASE, + SRCVOLTEN_VREQ_SEL, SPI_TRIG_MODE, + VREQ_CTRL, VREQ_CTRL_M, + SRCVOLTEN_CTRL, SRCLKENO_0_CTRL_M); + + WRITE32_BITFIELDS(&rc_regs->rc_central_cfg3, + TO_LPM_SETTLE_T, 0x4, + TO_BBLPM_SETTLE_EN, 0x1, + BLK_COANT_DXCO_MD_TARGET, 0x1, + BLK_SCP_DXCO_MD_TARGET, 0x1, + TO_LPM_SETTLE_EN, 0x1); + + /* Broadcast/multi-cmd setting */ + WRITE32_BITFIELDS(&rc_regs->rc_central_cfg5, + SPMI_CMD_BYTE_CNT, RC_SPMI_BYTE_LEN, + SPMI_M_SLV_ID, PMIC_GROUP_ID, + SPMI_P_SLV_ID, PMIC_GROUP_ID, + SPMI_P_PMIF_ID, 0x1, + SPMI_M_CMD_TYPE, 0x3, /* SPMI Burst write */ + SPMI_P_CMD_TYPE, 0x3, /* SPMI Burst write */ + SPMI_M_WRITE_EN, 0x1, + SPMI_P_WRITE_EN, 0x1, + BROADCAST_MODE_EN, 0x1, + DCXO_ENCODE, 0x1, /* DCXO 3bits --> 2bits */ + SPMI_M_FIRST, 0x1, + SPMI_BYTE_NUM, 0x1); /* Setting: [29:30] = 1 means send 2 bytes to pmif*/ + + /* CFG6-1 = 0x11111111 */ + write32(&rc_regs->central_cfg6_1, REQ_TO_SPMI_P_SUBSYS); + + /* CFG6-2 = 0x00001100 */ + WRITE32_BITFIELDS(&rc_regs->central_cfg6_2, + BYPASS_DCXO_VOTE_L, SUBSYS_EN_L, + BYPASS_DCXO_VOTE_H, SUBSYS_EN_H); + + /* Set srclkeno_0/conn_bt as factor to allow dcxo change to FPM */ + WRITE32_BITFIELDS(&rc_regs->rc_dcxo_fpm_cfg, + SUB_SRCLKEN_FPM_MSK_B, FULL_SET_HW_MODE, + SRCVOLTEN_FPM_MSK_B, MD0_SRCLKENO_0_MASK_B, + DCXO_FPM_CTRL_M, DCXO_FPM_CTRL_MODE); + + /* Set fpm channel */ + WRITE32_BITFIELDS(&rc_regs->subsys_intf_cfg_fpm, + SRCLKEN_FPM_MASK_B, SUB_FPM_SET); + + /* Trigger srclken_rc enable */ + SET32_BITFIELDS(&rc_regs->rc_central_cfg1, SRCLKEN_RC_EN, 0x1); + + /* Use PMIF_M + PMIF_P */ + WRITE32_BITFIELDS(&rc_regs->rc_central_cfg4, + SLEEP_VLD_MODE, 0x1, + PWRAP_VLD_FORCE, 0x1); + + /* CFG4_1: extension CFG4[0:15] */ + WRITE32_BITFIELDS(&rc_regs->central_cfg4_1, + KEEP_RC_SPI_ACTIVE, 0x800); + udelay(100); + + /* Set SW RESET 0 */ + SET32_BITFIELDS(&rc_regs->srclken_rc_cfg, SW_RESET, 0); + udelay(100); + + /* Set SW CG 0 */ + SET32_BITFIELDS(&rc_regs->srclken_rc_cfg, CG_32K_EN, 0); + udelay(500); + + /* Set req_filter m00~m31 FPM to LPM, hack original rc_ctrl[]*/ + rc_init_subsys_lpm(); + + /* Polling ACK of Initial Subsys Input */ + for (ch = 0; ch < MAX_CHN_NUM; ch++) { + if (rc_config[ch].disabled) + continue; + + fpm = rc_ctrl[ch].sw_fpm; + if (rc_config[ch].lpm) + fpm = SW_FPM_LOW; + + mask = SW_SRCLKEN_FPM_MSK << 1 | SW_SRCLKEN_BBLPM_MSK << 3; + state = (fpm & SW_SRCLKEN_FPM_MSK) << 1 | + (rc_ctrl[ch].sw_bblpm & SW_SRCLKEN_BBLPM_MSK) << 3; + + if (polling_rc_chn_ack(ch, mask, state)) + die("%s() failed to polling rc_chn %d\n", __func__, ch); + } + + /* Set req_filter m00~m31 */ + rc_init_subsys_hw_mode(); + + /* [1] = 1 means pmrc7,11,13 mux choose non multi master */ + write32(&rc_regs->src_pmrc_multi_master_cfg, 0x00000002); + + /* [0] = 1 means disable pmic starter */ + write32(&rc_regs->src_pmrc_starter_disable_cfg, 0x00000001); + write32(&rc_regs->src_pmrc_starter_mask_cfg, 0x00000000); + + /* pmrc8 & pmrc12 : bypass trigger pmic starter */ + write32(&rc_regs->src_pmrc_starter_bypass_cfg, 0x00001100); + + /* 92E ---> 90us */ + write32(&rc_regs->src_pmrc_starter_turn_on_cnt_size, 0x0000092E); + + /* 92E ---> 90us */ + write32(&rc_regs->src_pmrc_starter_turn_off_cnt_size, 0x0000092E); + + /* Write 0 to release force pmic req signal */ + SET32_BITFIELDS(&rc_regs->rc_central_cfg4, PWRAP_VLD_FORCE, 0); + + rc_dump_reg_info(); + + return 0; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/85842?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I40f8d2b12027955e6bd57b666e9f04c0116a0a93 Gerrit-Change-Number: 85842 Gerrit-PatchSet: 9 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ot_song fan <ot_song.fan(a)mediatek.corp-partner.google.com>

1 0

[L] Change in coreboot[main]: soc/mediatek/mt8196: Add clk_buf drivers
by Yidi Lin (Code Review) 11 Jan '25

11 Jan '25

Yidi Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85841?usp=email ) ( 6 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/mediatek/mt8196: Add clk_buf drivers ...................................................................... soc/mediatek/mt8196: Add clk_buf drivers MT8196 uses MT6685 clk_buf, and will use new RC mode with srclken_rc. The clk_buf will provide several 26M clocks, and these clocks can be independently turned on. RC mode will determine which clocks to be turned on based on users' requests, which is collected into PMRC_EN register by srclken_rc. TEST=Build pass. BUG=b:317009620 Signed-off-by: ot_song fan <ot_song.fan(a)mediatek.corp-partner.google.com> Change-Id: Ie18bfbb2f3354ba3645799857061dc20de7f6d84 Reviewed-on: https://review.coreboot.org/c/coreboot/+/85841 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Reviewed-by: Yidi Lin <yidilin(a)google.com> --- M src/soc/mediatek/mt8196/Makefile.mk A src/soc/mediatek/mt8196/clkbuf_ctl.c A src/soc/mediatek/mt8196/include/soc/clkbuf_ctl.h 3 files changed, 874 insertions(+), 0 deletions(-) Approvals: Yidi Lin: Looks good to me, approved build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved diff --git a/src/soc/mediatek/mt8196/Makefile.mk b/src/soc/mediatek/mt8196/Makefile.mk index d00159d..6ca25f9 100644 --- a/src/soc/mediatek/mt8196/Makefile.mk +++ b/src/soc/mediatek/mt8196/Makefile.mk @@ -24,6 +24,7 @@ bootblock-y += ../common/wdt.c ../common/wdt_req.c wdt.c romstage-y += ../common/cbmem.c +romstage-y += clkbuf_ctl.c romstage-y += ../common/dram_init.c romstage-y += ../common/dramc_param.c romstage-$(CONFIG_PCI) += ../common/early_init.c ../common/pcie.c diff --git a/src/soc/mediatek/mt8196/clkbuf_ctl.c b/src/soc/mediatek/mt8196/clkbuf_ctl.c new file mode 100644 index 0000000..04aa2f7 --- /dev/null +++ b/src/soc/mediatek/mt8196/clkbuf_ctl.c @@ -0,0 +1,374 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ + +#include <assert.h> +#include <soc/addressmap.h> +#include <soc/clkbuf_ctl.h> +#include <soc/mt6685.h> +#include <timer.h> + +#define XO_RC_MODE 0x1 +#define XO_DISABLE_MODE 0x0 + +#define XO_EN_MODE_MASK 0x7 +#define XO_EN_MODE_SHIFT 0 + +/* Impedance mask/shift, may need update for PMIC which is not 6685 */ +#define XO_IMPEDANCE_MASK 0x7 +#define XO_IMPEDANCE_SHIFT 3 + +#define XO_DRIVING_MASK 0x3 +#define XO_DRIVING_SHIFT 6 + +#define DCXO_DBG_AUXOUT_1 124 +#define DCXO_DBG_AUXOUT_2 125 +#define DCXO_DBG_AUXOUT_3 126 +#define DCXO_DBG_AUXOUT_4 127 + +/* Voting table */ +#define SOC_VOTER_L_MASK 0x01 +#define SOC_VOTER_H_MASK 0x00 + +#define CONN_PCIE_VOTER_L_MASK 0x80 +#define CONN_PCIE_VOTER_H_MASK 0x02 + +#define CONN_GPS_VOTER_L_MASK 0x40 +#define CONN_GPS_VOTER_H_MASK 0x00 + +#define MMWAVE_VOTER_L_MASK 0x00 +#define MMWAVE_VOTER_H_MASK 0x00 + +#define NFC_VOTER_L_MASK 0x00 +#define NFC_VOTER_H_MASK 0x08 + +#define RFMD_2A_VOTER_L_MASK 0x10 +#define RFMD_2A_VOTER_H_MASK 0x00 + +#define UFS_VOTER_L_MASK 0x00 +#define UFS_VOTER_H_MASK 0x20 + +static const struct ox_cfg ox[] = { + [XO_BBCK1] = { + .reg = XO_BBCK1_MODE_ADDR, + .mode = BBCK_BUF1_STATUS_PMIC, + .impedance = BBCK_BUF1_OUTPUT_IMPEDANCE, + .driving = BBCK_BUF1_DRIVING_STRENGTH, + .voter_mask = { /* 0x0001 */ + .low_byte = SOC_VOTER_L_MASK, + .high_byte = SOC_VOTER_H_MASK, + }, + }, + [XO_BBCK2] = { + .reg = XO_BBCK2_MODE_ADDR, + .mode = BBCK_BUF2_STATUS_PMIC, + .impedance = BBCK_BUF2_OUTPUT_IMPEDANCE, + .driving = BBCK_BUF2_DRIVING_STRENGTH, + .voter_mask = { /* 0x0280 */ + .low_byte = CONN_PCIE_VOTER_L_MASK, + .high_byte = CONN_PCIE_VOTER_H_MASK, + }, + }, + [XO_BBCK3] = { + .reg = XO_BBCK3_MODE_ADDR, + .mode = BBCK_BUF3_STATUS_PMIC, + .impedance = BBCK_BUF3_OUTPUT_IMPEDANCE, + .driving = BBCK_BUF3_DRIVING_STRENGTH, + .voter_mask = { /* 0x0000 */ + .low_byte = 0x0, + .high_byte = 0x0, + }, + }, + [XO_BBCK4] = { + .reg = XO_BBCK4_MODE_ADDR, + .mode = BBCK_BUF4_STATUS_PMIC, + .impedance = BBCK_BUF4_OUTPUT_IMPEDANCE, + .driving = BBCK_BUF4_DRIVING_STRENGTH, + .voter_mask = { /* 0x0800 */ + .low_byte = NFC_VOTER_L_MASK, + .high_byte = NFC_VOTER_H_MASK, + }, + }, + [XO_BBCK5] = { + .reg = XO_BBCK5_MODE_ADDR, + .mode = BBCK_BUF5_STATUS_PMIC, + .impedance = BBCK_BUF5_OUTPUT_IMPEDANCE, + .driving = BBCK_BUF5_DRIVING_STRENGTH, + .voter_mask = { /* 0x0000 */ + .low_byte = 0x0, + .high_byte = 0x0, + }, + }, + [XO_RFCK1A] = { + .reg = XO_RFCK1A_MODE_ADDR, + .mode = RFCK_BUF1A_STATUS_PMIC, + .impedance = RFCK_BUF1A_OUTPUT_IMPEDANCE, + .driving = 0, + .voter_mask = { /* 0x0000 */ + .low_byte = MMWAVE_VOTER_L_MASK, + .high_byte = MMWAVE_VOTER_H_MASK, + }, + }, + [XO_RFCK1B] = { + .reg = XO_RFCK1B_MODE_ADDR, + .mode = RFCK_BUF1B_STATUS_PMIC, + .impedance = RFCK_BUF1B_OUTPUT_IMPEDANCE, + .driving = 0, + .voter_mask = { /* 0x2000 */ + .low_byte = UFS_VOTER_L_MASK, + .high_byte = UFS_VOTER_H_MASK, + }, + }, + [XO_RFCK1C] = { + .reg = XO_RFCK1C_MODE_ADDR, + .mode = CLOCK_BUFFER_DISABLE, + }, + [XO_RFCK2A] = { + .reg = XO_RFCK2A_MODE_ADDR, + .mode = RFCK_BUF2A_STATUS_PMIC, + .impedance = RFCK_BUF2A_OUTPUT_IMPEDANCE, + .driving = 0, + .voter_mask = { /* 0x0010 */ + .low_byte = RFMD_2A_VOTER_L_MASK, + .high_byte = RFMD_2A_VOTER_H_MASK, + }, + }, + [XO_RFCK2B] = { + .reg = XO_RFCK2B_MODE_ADDR, + .mode = RFCK_BUF2B_STATUS_PMIC, + .impedance = RFCK_BUF2B_OUTPUT_IMPEDANCE, + .driving = 0, + .voter_mask = { /* 0x0040 */ + .low_byte = CONN_GPS_VOTER_L_MASK, + .high_byte = CONN_GPS_VOTER_H_MASK, + }, + }, + [XO_RFCK2C] = { + .reg = XO_RFCK2C_MODE_ADDR, + .mode = CLOCK_BUFFER_DISABLE, + }, + [XO_CONCK1] = { + .reg = XO_CONCK1_MODE_ADDR, + .mode = CLOCK_BUFFER_DISABLE, + }, + [XO_CONCK2] = { + .reg = XO_CONCK2_MODE_ADDR, + .mode = CLOCK_BUFFER_DISABLE, + }, +}; + +_Static_assert(ARRAY_SIZE(ox) == XO_NUMBER, "Wrong array size of ox"); + +static u16 mt6685_read_low_high(u32 low_reg, u32 high_reg) +{ + u16 data = mt6685_read8(low_reg); + data |= mt6685_read8(high_reg) << 8; + return data; +} + +u16 clk_buf_get_pmrc_en0(void) +{ + return mt6685_read_low_high(MT6685_PMRC_CON0, MT6685_PMRC_CON1); +} + +static void clk_buf_dump_dws_log(void) +{ + int i; + + printk(BIOS_INFO, "%s: DWS_CLKBUF_STA BBCK1/2/3/4/5=", __func__); + for (i = XO_BBCK1; i <= XO_BBCK5; ++i) + printk(BIOS_INFO, "%u/", ox[i].mode); + + printk(BIOS_INFO, "\nRFCK1A/1B/1C/2A/2B/2C="); + for (i = XO_RFCK1A; i <= XO_RFCK2C; ++i) + printk(BIOS_INFO, "%u/", ox[i].mode); + + printk(BIOS_INFO, "\nCONCK1/2="); + for (i = XO_CONCK1; i <= XO_CONCK2; ++i) + printk(BIOS_INFO, "%u/", ox[i].mode); + + printk(BIOS_INFO, "\n"); + + printk(BIOS_INFO, "%s: DWS_CLK_BUF_IMPEDANCE BBCK1/2/3/4/5=", __func__); + for (i = XO_BBCK1; i <= XO_BBCK5; ++i) + printk(BIOS_INFO, "%u/", ox[i].impedance); + + printk(BIOS_INFO, "\nRFCK1A/1B/1C/2A/2B/2C="); + for (i = XO_RFCK1A; i <= XO_RFCK2C; ++i) + printk(BIOS_INFO, "%u/", ox[i].impedance); + + printk(BIOS_INFO, "\nCONCK1/2="); + for (i = XO_CONCK1; i <= XO_CONCK2; ++i) + printk(BIOS_INFO, "%u/", ox[i].impedance); + + printk(BIOS_INFO, "\n"); + + printk(BIOS_INFO, "%s: DWS_CLK_BUF_DRIVING BBCK1/2/3/4/5=", __func__); + for (i = XO_BBCK1; i <= XO_BBCK5; ++i) + printk(BIOS_INFO, "%u/", ox[i].driving); + + printk(BIOS_INFO, "\n"); +} + +static void dump_clkbuf_log(void) +{ + u8 xo_buf_cw[XO_NUMBER]; + u16 xo_buf_vote[XO_NUMBER]; + u8 dig_manctrl_cw1; + u8 bblpm_cw0; + u32 dig26m_div2; + int i; + + _Static_assert(MT6685_XO_BUF_CTL0_L + 2 * (XO_NUMBER - 1) == MT6685_XO_BUF_CTL12_L, + "Wrong reg for MT6685_XO_BUF_CTL12_L"); + _Static_assert(MT6685_XO_BUF_CTL0_H + 2 * (XO_NUMBER - 1) == MT6685_XO_BUF_CTL12_H, + "Wrong reg for MT6685_XO_BUF_CTL12_H"); + + for (i = 0; i < XO_NUMBER; i++) { + xo_buf_cw[i] = mt6685_read8(MT6685_DCXO_EXTBUF1_CW0 + i); + xo_buf_vote[i] = mt6685_read_low_high(MT6685_XO_BUF_CTL0_L + (2 * i), + MT6685_XO_BUF_CTL0_H + (2 * i)); + } + + dig_manctrl_cw1 = mt6685_read8(MT6685_DCXO_DIG_MANCTRL_CW1); + bblpm_cw0 = mt6685_read8(MT6685_DCXO_BBLPM_CW0); + + dig26m_div2 = mt6685_read_field(RG_XO_DIG26M_DIV2_ADDR, + RG_XO_DIG26M_DIV2_MASK, + RG_XO_DIG26M_DIV2_SHIFT); + + printk(BIOS_INFO, "[clkbuf] xo_buf_cw(%#X ~ %#X):\n", + MT6685_DCXO_EXTBUF1_CW0, MT6685_DCXO_EXTBUF13_CW0); + for (i = 0; i < XO_NUMBER; ++i) + printk(BIOS_INFO, "%#x/", xo_buf_cw[i]); + printk(BIOS_INFO, "\n"); + + printk(BIOS_INFO, "[clkbuf] xo_buf_vote(%#X ~ %#X):\n", + MT6685_XO_BUF_CTL0_L, MT6685_XO_BUF_CTL12_H); + + for (i = 0; i < XO_NUMBER; ++i) + printk(BIOS_INFO, "%#x/", xo_buf_vote[i]); + printk(BIOS_INFO, "\n"); + + printk(BIOS_INFO, "[clkbuf] dig_manctrl_cw1(%#x): %#x\nbblpm_cw0(%#x): %#x\n", + MT6685_DCXO_DIG_MANCTRL_CW1, + dig_manctrl_cw1, + MT6685_DCXO_BBLPM_CW0, + bblpm_cw0); + printk(BIOS_INFO, "[clkbuf] dig26m_div2(%#x): %#x\n", + RG_XO_DIG26M_DIV2_ADDR, + dig26m_div2); +} + +static void clk_buf_init_pmic_clkbuf(void) +{ + u8 val; + int i; + + /* 1.1 Write XO_BUF impedance & driving */ + for (i = 0; i < XO_NUMBER; ++i) + if (ox[i].mode != CLOCK_BUFFER_DISABLE) + mt6685_write_field(ox[i].reg, ox[i].impedance, + XO_IMPEDANCE_MASK, XO_IMPEDANCE_SHIFT); + + /* 1.2 Write XO_BUF driving */ + for (i = 0; i <= XO_BBCK5; ++i) + if (ox[i].mode != CLOCK_BUFFER_DISABLE) + mt6685_write_field(ox[i].reg, ox[i].driving, XO_DRIVING_MASK, + XO_DRIVING_SHIFT); + + /* 1.3 Write RC voting table */ + for (i = 0; i < XO_NUMBER; i++) { + u8 low, high; + if (ox[i].mode == CLOCK_BUFFER_DISABLE) { + low = 0; + high = 0; + } else { + low = ox[i].voter_mask.low_byte; + high = ox[i].voter_mask.high_byte; + } + mt6685_write8(MT6685_XO_BUF_CTL0_L + (2 * i), low); + mt6685_write8(MT6685_XO_BUF_CTL0_H + (2 * i), high); + } + + /* 1.4 Turn on LDO HW control from XO_BUFs */ + mt6685_write_field(RG_LDO_VRFCK1_HW14_OP_EN_ADDR, + 0x1, + RG_LDO_VRFCK1_HW14_OP_EN_MASK, + RG_LDO_VRFCK1_HW14_OP_EN_SHIFT); + + mt6685_write_field(RG_LDO_VRFCK2_HW14_OP_EN_ADDR, + 0x1, + RG_LDO_VRFCK2_HW14_OP_EN_MASK, + RG_LDO_VRFCK2_HW14_OP_EN_SHIFT); + + mt6685_write_field(RG_LDO_VBBCK_HW14_OP_EN_ADDR, + 0x1, + RG_LDO_VBBCK_HW14_OP_EN_MASK, + RG_LDO_VBBCK_HW14_OP_EN_SHIFT); + + /* 1.5 Turn off LDO SW control */ + mt6685_write_field(RG_LDO_VRFCK1_EN_ADDR, + 0x0, + RG_LDO_VRFCK1_EN_MASK, + RG_LDO_VRFCK1_EN_SHIFT); + + mt6685_write_field(RG_LDO_VRFCK2_EN_ADDR, + 0x0, + RG_LDO_VRFCK2_EN_MASK, + RG_LDO_VRFCK2_EN_SHIFT); + + mt6685_write_field(RG_LDO_VBBCK_EN_ADDR, + 0x0, + RG_LDO_VBBCK_EN_MASK, + RG_LDO_VBBCK_EN_SHIFT); + + /* 1.6 Enable/Disable XO by dws */ + for (i = 0; i < XO_NUMBER; ++i) { + if (ox[i].mode == CLOCK_BUFFER_DISABLE || + ox[i].mode == CLOCK_BUFFER_SW_CONTROL) + mt6685_write_field(ox[i].reg, XO_DISABLE_MODE, + XO_EN_MODE_MASK, XO_EN_MODE_SHIFT); + else if (ox[i].mode == CLOCK_BUFFER_HW_CONTROL) + mt6685_write_field(ox[i].reg, XO_RC_MODE, + XO_EN_MODE_MASK, XO_EN_MODE_SHIFT); + } + + /* 1.7 RC mode setting, en_bb hw mode. And switch to srclken_rc mode */ + val = mt6685_read8(MT6685_DCXO_DIG_MANCTRL_CW1); + val &= ~(XO_PMIC_TOP_DIG_SW_MASK << XO_PMIC_TOP_DIG_SW_SHIFT); + val &= ~(XO_ENBB_MAN_MASK << XO_ENBB_MAN_SHIFT); + val &= ~(XO_ENBB_EN_M_MASK << XO_ENBB_EN_M_SHIFT); + val &= ~(XO_CLKSEL_EN_M_MASK << XO_CLKSEL_EN_M_SHIFT); + mt6685_write8(MT6685_DCXO_DIG_MANCTRL_CW1, val); +} + +static u16 dcxo_dbg_read_auxout(u32 sel) +{ + u16 val; + + mt6685_write_field(XO_STATIC_AUXOUT_SEL_ADDR, sel, XO_STATIC_AUXOUT_SEL_MASK, + XO_STATIC_AUXOUT_SEL_SHIFT); + val = mt6685_read_low_high(XO_STATIC_AUXOUT_L_ADDR, XO_STATIC_AUXOUT_H_ADDR); + + printk(BIOS_INFO, "%s: sel=%d, rg_auxout=%#x\n", __func__, sel, val); + + return val; +} + +int clk_buf_init(void) +{ + /* Check dws setting */ + clk_buf_dump_dws_log(); + + /* Dump lpsd dbg0-3 for debug during pmic_long_press_reset */ + dcxo_dbg_read_auxout(DCXO_DBG_AUXOUT_1); + dcxo_dbg_read_auxout(DCXO_DBG_AUXOUT_2); + dcxo_dbg_read_auxout(DCXO_DBG_AUXOUT_3); + dcxo_dbg_read_auxout(DCXO_DBG_AUXOUT_4); + + clk_buf_init_pmic_clkbuf(); + + /* Check if the setting is ok */ + dump_clkbuf_log(); + + return 0; +} diff --git a/src/soc/mediatek/mt8196/include/soc/clkbuf_ctl.h b/src/soc/mediatek/mt8196/include/soc/clkbuf_ctl.h new file mode 100644 index 0000000..5b425b8 --- /dev/null +++ b/src/soc/mediatek/mt8196/include/soc/clkbuf_ctl.h @@ -0,0 +1,499 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ + +#ifndef __SOC_MEDIATEK_MT8196_INCLUDE_SOC_CLK_BUF_CTL_H__ +#define __SOC_MEDIATEK_MT8196_INCLUDE_SOC_CLK_BUF_CTL_H__ + +#include <console/console.h> + +#define MT6685_PMRC_CON0 0x190 +#define MT6685_PMRC_CON1 0x191 +#define MT6685_PMRC_CON0_SET 0x198 +#define MT6685_PMRC_CON1_SET 0x199 +#define MT6685_PMRC_CON0_CLR 0x19a +#define MT6685_PMRC_CON1_CLR 0x19b +#define MT6685_PMRC_CON3 0x19c +#define MT6685_XO_BUF_CTL0_L 0x54c +#define MT6685_XO_BUF_CTL0_H 0x54d +#define MT6685_XO_BUF_CTL1_L 0x54e +#define MT6685_XO_BUF_CTL1_H 0x54f +#define MT6685_XO_BUF_CTL2_L 0x550 +#define MT6685_XO_BUF_CTL2_H 0x551 +#define MT6685_XO_BUF_CTL3_L 0x552 +#define MT6685_XO_BUF_CTL3_H 0x553 +#define MT6685_XO_BUF_CTL4_L 0x554 +#define MT6685_XO_BUF_CTL4_H 0x555 +#define MT6685_XO_BUF_CTL5_L 0x556 +#define MT6685_XO_BUF_CTL5_H 0x557 +#define MT6685_XO_BUF_CTL6_L 0x558 +#define MT6685_XO_BUF_CTL6_H 0x559 +#define MT6685_XO_BUF_CTL7_L 0x55a +#define MT6685_XO_BUF_CTL7_H 0x55b +#define MT6685_XO_BUF_CTL8_L 0x55c +#define MT6685_XO_BUF_CTL8_H 0x55d +#define MT6685_XO_BUF_CTL9_L 0x55e +#define MT6685_XO_BUF_CTL9_H 0x55f +#define MT6685_XO_BUF_CTL10_L 0x560 +#define MT6685_XO_BUF_CTL10_H 0x561 +#define MT6685_XO_BUF_CTL11_L 0x562 +#define MT6685_XO_BUF_CTL11_H 0x563 +#define MT6685_XO_BUF_CTL12_L 0x564 +#define MT6685_XO_BUF_CTL12_H 0x565 +#define MT6685_XO_CONN_BT0 0x567 +#define MT6685_DCXO_DIG_MANCTRL_CW1 0x796 +#define MT6685_DCXO_BBLPM_CW0 0x797 +#define MT6685_DCXO_BBLPM_CW1 0x798 +#define MT6685_DCXO_LDO_CW0 0x799 +#define MT6685_DCXO_EXTBUF1_CW0 0x79a +#define MT6685_DCXO_EXTBUF2_CW0 0x79b +#define MT6685_DCXO_EXTBUF3_CW0 0x79c +#define MT6685_DCXO_EXTBUF4_CW0 0x79d +#define MT6685_DCXO_EXTBUF5_CW0 0x79e +#define MT6685_DCXO_EXTBUF6_CW0 0x79f +#define MT6685_DCXO_EXTBUF7_CW0 0x7a0 +#define MT6685_DCXO_EXTBUF8_CW0 0x7a1 +#define MT6685_DCXO_EXTBUF9_CW0 0x7a2 +#define MT6685_DCXO_EXTBUF10_CW0 0x7a3 +#define MT6685_DCXO_EXTBUF11_CW0 0x7a4 +#define MT6685_DCXO_EXTBUF12_CW0 0x7a5 +#define MT6685_DCXO_EXTBUF13_CW0 0x7a6 +#define MT6685_DCXO_RGMON_CW0_L 0x7b2 +#define MT6685_DCXO_RGMON_CW0_H 0x7b3 +#define MT6685_DCXO_RGMON_CW2_L 0x7b4 +#define MT6685_DCXO_RGMON_CW2_H 0x7b5 +#define MT6685_DCXO_RGMON_CW1 0x7c3 +#define MT6685_DCXO_DIGCLK_ELR 0x7f4 +#define MT6685_LDO_VBBCK_CON0 0x1b87 +#define MT6685_LDO_VBBCK_OP_EN1 0x1b8e +#define MT6685_LDO_VBBCK_OP_EN1_SET 0x1b8f +#define MT6685_LDO_VBBCK_OP_EN1_CLR 0x1b90 +#define MT6685_LDO_VRFCK1_CON0 0x1b97 +#define MT6685_LDO_VRFCK1_OP_EN1 0x1b9e +#define MT6685_LDO_VRFCK1_OP_EN1_SET 0x1b9f +#define MT6685_LDO_VRFCK1_OP_EN1_CLR 0x1ba0 +#define MT6685_LDO_VRFCK2_CON0 0x1ba7 +#define MT6685_LDO_VRFCK2_OP_EN1 0x1bae +#define MT6685_LDO_VRFCK2_OP_EN1_SET 0x1baf +#define MT6685_LDO_VRFCK2_OP_EN1_CLR 0x1bb0 + +/* Register_TOP_REG */ +#define RG_DCXO_SRCLKEN1_MODE_ADDR MT6685_PMRC_CON3 +#define RG_DCXO_SRCLKEN1_MODE_MASK 0x3 +#define RG_DCXO_SRCLKEN1_MODE_SHIFT 2 +/* Register_SCK_REG */ +#define XO_BBCK1_VOTE_L_ADDR MT6685_XO_BUF_CTL0_L +#define XO_BBCK1_VOTE_L_MASK 0xff +#define XO_BBCK1_VOTE_L_SHIFT 0 +#define XO_BBCK1_VOTE_H_ADDR MT6685_XO_BUF_CTL0_H +#define XO_BBCK1_VOTE_H_MASK 0x3f +#define XO_BBCK1_VOTE_H_SHIFT 0 +#define XO_BBCK2_VOTE_L_ADDR MT6685_XO_BUF_CTL1_L +#define XO_BBCK2_VOTE_L_MASK 0xff +#define XO_BBCK2_VOTE_L_SHIFT 0 +#define XO_BBCK2_VOTE_H_ADDR MT6685_XO_BUF_CTL1_H +#define XO_BBCK2_VOTE_H_MASK 0x3f +#define XO_BBCK2_VOTE_H_SHIFT 0 +#define XO_BBCK3_VOTE_L_ADDR MT6685_XO_BUF_CTL2_L +#define XO_BBCK3_VOTE_L_MASK 0xff +#define XO_BBCK3_VOTE_L_SHIFT 0 +#define XO_BBCK3_VOTE_H_ADDR MT6685_XO_BUF_CTL2_H +#define XO_BBCK3_VOTE_H_MASK 0x3f +#define XO_BBCK3_VOTE_H_SHIFT 0 +#define XO_BBCK4_VOTE_L_ADDR MT6685_XO_BUF_CTL3_L +#define XO_BBCK4_VOTE_L_MASK 0xff +#define XO_BBCK4_VOTE_L_SHIFT 0 +#define XO_BBCK4_VOTE_H_ADDR MT6685_XO_BUF_CTL3_H +#define XO_BBCK4_VOTE_H_MASK 0x3f +#define XO_BBCK4_VOTE_H_SHIFT 0 +#define XO_BBCK5_VOTE_L_ADDR MT6685_XO_BUF_CTL4_L +#define XO_BBCK5_VOTE_L_MASK 0xff +#define XO_BBCK5_VOTE_L_SHIFT 0 +#define XO_BBCK5_VOTE_H_ADDR MT6685_XO_BUF_CTL4_H +#define XO_BBCK5_VOTE_H_MASK 0x3f +#define XO_BBCK5_VOTE_H_SHIFT 0 +#define XO_RFCK1A_VOTE_L_ADDR MT6685_XO_BUF_CTL5_L +#define XO_RFCK1A_VOTE_L_MASK 0xff +#define XO_RFCK1A_VOTE_L_SHIFT 0 +#define XO_RFCK1A_VOTE_H_ADDR MT6685_XO_BUF_CTL5_H +#define XO_RFCK1A_VOTE_H_MASK 0x3f +#define XO_RFCK1A_VOTE_H_SHIFT 0 +#define XO_RFCK1B_VOTE_L_ADDR MT6685_XO_BUF_CTL6_L +#define XO_RFCK1B_VOTE_L_MASK 0xff +#define XO_RFCK1B_VOTE_L_SHIFT 0 +#define XO_RFCK1B_VOTE_H_ADDR MT6685_XO_BUF_CTL6_H +#define XO_RFCK1B_VOTE_H_MASK 0x3f +#define XO_RFCK1B_VOTE_H_SHIFT 0 +#define XO_RFCK1C_VOTE_L_ADDR MT6685_XO_BUF_CTL7_L +#define XO_RFCK1C_VOTE_L_MASK 0xff +#define XO_RFCK1C_VOTE_L_SHIFT 0 +#define XO_RFCK1C_VOTE_H_ADDR MT6685_XO_BUF_CTL7_H +#define XO_RFCK1C_VOTE_H_MASK 0x3f +#define XO_RFCK1C_VOTE_H_SHIFT 0 +#define XO_RFCK2A_VOTE_L_ADDR MT6685_XO_BUF_CTL8_L +#define XO_RFCK2A_VOTE_L_MASK 0xff +#define XO_RFCK2A_VOTE_L_SHIFT 0 +#define XO_RFCK2A_VOTE_H_ADDR MT6685_XO_BUF_CTL8_H +#define XO_RFCK2A_VOTE_H_MASK 0x3f +#define XO_RFCK2A_VOTE_H_SHIFT 0 +#define XO_RFCK2B_VOTE_L_ADDR MT6685_XO_BUF_CTL9_L +#define XO_RFCK2B_VOTE_L_MASK 0xff +#define XO_RFCK2B_VOTE_L_SHIFT 0 +#define XO_RFCK2B_VOTE_H_ADDR MT6685_XO_BUF_CTL9_H +#define XO_RFCK2B_VOTE_H_MASK 0x3f +#define XO_RFCK2B_VOTE_H_SHIFT 0 +#define XO_RFCK2C_VOTE_L_ADDR MT6685_XO_BUF_CTL10_L +#define XO_RFCK2C_VOTE_L_MASK 0xff +#define XO_RFCK2C_VOTE_L_SHIFT 0 +#define XO_RFCK2C_VOTE_H_ADDR MT6685_XO_BUF_CTL10_H +#define XO_RFCK2C_VOTE_H_MASK 0x3f +#define XO_RFCK2C_VOTE_H_SHIFT 0 +#define XO_CONCK1_VOTE_L_ADDR MT6685_XO_BUF_CTL11_L +#define XO_CONCK1_VOTE_L_MASK 0xff +#define XO_CONCK1_VOTE_L_SHIFT 0 +#define XO_CONCK1_VOTE_H_ADDR MT6685_XO_BUF_CTL11_H +#define XO_CONCK1_VOTE_H_MASK 0x3f +#define XO_CONCK1_VOTE_H_SHIFT 0 +#define XO_CONCK2_VOTE_L_ADDR MT6685_XO_BUF_CTL12_L +#define XO_CONCK2_VOTE_L_MASK 0xff +#define XO_CONCK2_VOTE_L_SHIFT 0 +#define XO_CONCK2_VOTE_H_ADDR MT6685_XO_BUF_CTL12_H +#define XO_CONCK2_VOTE_H_MASK 0x3f +#define XO_CONCK2_VOTE_H_SHIFT 0 +#define XO_MODE_CONN_BT_MASK_ADDR MT6685_XO_CONN_BT0 +#define XO_MODE_CONN_BT_MASK_MASK 0x1 +#define XO_MODE_CONN_BT_MASK_SHIFT 0 +#define XO_BUF_CONN_BT_MASK_ADDR MT6685_XO_CONN_BT0 +#define XO_BUF_CONN_BT_MASK_MASK 0x1 +#define XO_BUF_CONN_BT_MASK_SHIFT 1 +/* Register_DCXO_REG */ +#define XO_PMIC_TOP_DIG_SW_ADDR MT6685_DCXO_DIG_MANCTRL_CW1 +#define XO_PMIC_TOP_DIG_SW_MASK 0x1 +#define XO_PMIC_TOP_DIG_SW_SHIFT 0 +#define XO_ENBB_MAN_ADDR MT6685_DCXO_DIG_MANCTRL_CW1 +#define XO_ENBB_MAN_MASK 0x1 +#define XO_ENBB_MAN_SHIFT 1 +#define XO_ENBB_EN_M_ADDR MT6685_DCXO_DIG_MANCTRL_CW1 +#define XO_ENBB_EN_M_MASK 0x1 +#define XO_ENBB_EN_M_SHIFT 2 +#define XO_CLKSEL_MAN_ADDR MT6685_DCXO_DIG_MANCTRL_CW1 +#define XO_CLKSEL_MAN_MASK 0x1 +#define XO_CLKSEL_MAN_SHIFT 3 +#define XO_CLKSEL_EN_M_ADDR MT6685_DCXO_DIG_MANCTRL_CW1 +#define XO_CLKSEL_EN_M_MASK 0x1 +#define XO_CLKSEL_EN_M_SHIFT 4 +#define XO_BB_LPM_EN_M_ADDR MT6685_DCXO_BBLPM_CW0 +#define XO_BB_LPM_EN_M_MASK 0x1 +#define XO_BB_LPM_EN_M_SHIFT 0 +#define XO_BB_LPM_EN_SEL_ADDR MT6685_DCXO_BBLPM_CW0 +#define XO_BB_LPM_EN_SEL_MASK 0x1 +#define XO_BB_LPM_EN_SEL_SHIFT 1 +#define XO_BBCK1_BBLPM_EN_MASK_ADDR MT6685_DCXO_BBLPM_CW0 +#define XO_BBCK1_BBLPM_EN_MASK_MASK 0x1 +#define XO_BBCK1_BBLPM_EN_MASK_SHIFT 2 +#define XO_BBCK2_BBLPM_EN_MASK_ADDR MT6685_DCXO_BBLPM_CW0 +#define XO_BBCK2_BBLPM_EN_MASK_MASK 0x1 +#define XO_BBCK2_BBLPM_EN_MASK_SHIFT 3 +#define XO_BBCK3_BBLPM_EN_MASK_ADDR MT6685_DCXO_BBLPM_CW0 +#define XO_BBCK3_BBLPM_EN_MASK_MASK 0x1 +#define XO_BBCK3_BBLPM_EN_MASK_SHIFT 4 +#define XO_BBCK4_BBLPM_EN_MASK_ADDR MT6685_DCXO_BBLPM_CW0 +#define XO_BBCK4_BBLPM_EN_MASK_MASK 0x1 +#define XO_BBCK4_BBLPM_EN_MASK_SHIFT 5 +#define XO_BBCK5_BBLPM_EN_MASK_ADDR MT6685_DCXO_BBLPM_CW0 +#define XO_BBCK5_BBLPM_EN_MASK_MASK 0x1 +#define XO_BBCK5_BBLPM_EN_MASK_SHIFT 6 +#define XO_BBLPM_EN_MAN_ADDR MT6685_DCXO_BBLPM_CW1 +#define XO_BBLPM_EN_MAN_MASK 0x1 +#define XO_BBLPM_EN_MAN_SHIFT 0 +#define XO_BBLPM_EN_MAN_M_ADDR MT6685_DCXO_BBLPM_CW1 +#define XO_BBLPM_EN_MAN_M_MASK 0x1 +#define XO_BBLPM_EN_MAN_M_SHIFT 1 +#define XO_VBBCK_EN_MAN_ADDR MT6685_DCXO_LDO_CW0 +#define XO_VBBCK_EN_MAN_MASK 0x1 +#define XO_VBBCK_EN_MAN_SHIFT 0 +#define XO_VBBCK_EN_M_ADDR MT6685_DCXO_LDO_CW0 +#define XO_VBBCK_EN_M_MASK 0x1 +#define XO_VBBCK_EN_M_SHIFT 1 +#define XO_VRFCK1_EN_MAN_ADDR MT6685_DCXO_LDO_CW0 +#define XO_VRFCK1_EN_MAN_MASK 0x1 +#define XO_VRFCK1_EN_MAN_SHIFT 2 +#define XO_VRFCK1_EN_M_ADDR MT6685_DCXO_LDO_CW0 +#define XO_VRFCK1_EN_M_MASK 0x1 +#define XO_VRFCK1_EN_M_SHIFT 3 +#define XO_VRFCK2_EN_MAN_ADDR MT6685_DCXO_LDO_CW0 +#define XO_VRFCK2_EN_MAN_MASK 0x1 +#define XO_VRFCK2_EN_MAN_SHIFT 4 +#define XO_VRFCK2_EN_M_ADDR MT6685_DCXO_LDO_CW0 +#define XO_VRFCK2_EN_M_MASK 0x1 +#define XO_VRFCK2_EN_M_SHIFT 5 +#define XO_VCONCK_EN_MAN_ADDR MT6685_DCXO_LDO_CW0 +#define XO_VCONCK_EN_MAN_MASK 0x1 +#define XO_VCONCK_EN_MAN_SHIFT 6 +#define XO_VCONCK_EN_M_ADDR MT6685_DCXO_LDO_CW0 +#define XO_VCONCK_EN_M_MASK 0x1 +#define XO_VCONCK_EN_M_SHIFT 7 +#define XO_BBCK1_MODE_ADDR MT6685_DCXO_EXTBUF1_CW0 +#define XO_BBCK1_EN_M_ADDR MT6685_DCXO_EXTBUF1_CW0 +#define XO_BBCK1_EN_M_MASK 0x1 +#define XO_BBCK1_EN_M_SHIFT 2 +#define RG_XO_EXTBUF_BBCK1_RSEL_ADDR MT6685_DCXO_EXTBUF1_CW0 +#define RG_XO_EXTBUF_BBCK1_RSEL_MASK 0x7 +#define RG_XO_EXTBUF_BBCK1_RSEL_SHIFT 3 +#define RG_XO_EXTBUF_BBCK1_HD_ADDR MT6685_DCXO_EXTBUF1_CW0 +#define RG_XO_EXTBUF_BBCK1_HD_MASK 0x3 +#define RG_XO_EXTBUF_BBCK1_HD_SHIFT 6 +#define XO_BBCK2_MODE_ADDR MT6685_DCXO_EXTBUF2_CW0 +#define XO_BBCK2_EN_M_ADDR MT6685_DCXO_EXTBUF2_CW0 +#define XO_BBCK2_EN_M_MASK 0x1 +#define XO_BBCK2_EN_M_SHIFT 2 +#define RG_XO_EXTBUF_BBCK2_RSEL_ADDR MT6685_DCXO_EXTBUF2_CW0 +#define RG_XO_EXTBUF_BBCK2_RSEL_MASK 0x7 +#define RG_XO_EXTBUF_BBCK2_RSEL_SHIFT 3 +#define RG_XO_EXTBUF_BBCK2_HD_ADDR MT6685_DCXO_EXTBUF2_CW0 +#define RG_XO_EXTBUF_BBCK2_HD_MASK 0x3 +#define RG_XO_EXTBUF_BBCK2_HD_SHIFT 6 +#define XO_BBCK3_MODE_ADDR MT6685_DCXO_EXTBUF3_CW0 +#define XO_BBCK3_EN_M_ADDR MT6685_DCXO_EXTBUF3_CW0 +#define XO_BBCK3_EN_M_MASK 0x1 +#define XO_BBCK3_EN_M_SHIFT 2 +#define RG_XO_EXTBUF_BBCK3_RSEL_ADDR MT6685_DCXO_EXTBUF3_CW0 +#define RG_XO_EXTBUF_BBCK3_RSEL_MASK 0x7 +#define RG_XO_EXTBUF_BBCK3_RSEL_SHIFT 3 +#define RG_XO_EXTBUF_BBCK3_HD_ADDR MT6685_DCXO_EXTBUF3_CW0 +#define RG_XO_EXTBUF_BBCK3_HD_MASK 0x3 +#define RG_XO_EXTBUF_BBCK3_HD_SHIFT 6 +#define XO_BBCK4_MODE_ADDR MT6685_DCXO_EXTBUF4_CW0 +#define XO_BBCK4_EN_M_ADDR MT6685_DCXO_EXTBUF4_CW0 +#define XO_BBCK4_EN_M_MASK 0x1 +#define XO_BBCK4_EN_M_SHIFT 2 +#define RG_XO_EXTBUF_BBCK4_RSEL_ADDR MT6685_DCXO_EXTBUF4_CW0 +#define RG_XO_EXTBUF_BBCK4_RSEL_MASK 0x7 +#define RG_XO_EXTBUF_BBCK4_RSEL_SHIFT 3 +#define RG_XO_EXTBUF_BBCK4_HD_ADDR MT6685_DCXO_EXTBUF4_CW0 +#define RG_XO_EXTBUF_BBCK4_HD_MASK 0x3 +#define RG_XO_EXTBUF_BBCK4_HD_SHIFT 6 +#define XO_BBCK5_MODE_ADDR MT6685_DCXO_EXTBUF5_CW0 +#define XO_BBCK5_EN_M_ADDR MT6685_DCXO_EXTBUF5_CW0 +#define XO_BBCK5_EN_M_MASK 0x1 +#define XO_BBCK5_EN_M_SHIFT 2 +#define RG_XO_EXTBUF_BBCK5_RSEL_ADDR MT6685_DCXO_EXTBUF5_CW0 +#define RG_XO_EXTBUF_BBCK5_RSEL_MASK 0x7 +#define RG_XO_EXTBUF_BBCK5_RSEL_SHIFT 3 +#define RG_XO_EXTBUF_BBCK5_HD_ADDR MT6685_DCXO_EXTBUF5_CW0 +#define RG_XO_EXTBUF_BBCK5_HD_MASK 0x3 +#define RG_XO_EXTBUF_BBCK5_HD_SHIFT 6 +#define XO_RFCK1A_MODE_ADDR MT6685_DCXO_EXTBUF6_CW0 +#define XO_RFCK1A_EN_M_ADDR MT6685_DCXO_EXTBUF6_CW0 +#define XO_RFCK1A_EN_M_MASK 0x1 +#define XO_RFCK1A_EN_M_SHIFT 2 +#define RG_XO_EXTBUF_RFCK1A_RSEL_ADDR MT6685_DCXO_EXTBUF6_CW0 +#define RG_XO_EXTBUF_RFCK1A_RSEL_MASK 0x7 +#define RG_XO_EXTBUF_RFCK1A_RSEL_SHIFT 3 +#define XO_RFCK1B_MODE_ADDR MT6685_DCXO_EXTBUF7_CW0 +#define XO_RFCK1B_EN_M_ADDR MT6685_DCXO_EXTBUF7_CW0 +#define XO_RFCK1B_EN_M_MASK 0x1 +#define XO_RFCK1B_EN_M_SHIFT 2 +#define RG_XO_EXTBUF_RFCK1B_RSEL_ADDR MT6685_DCXO_EXTBUF7_CW0 +#define RG_XO_EXTBUF_RFCK1B_RSEL_MASK 0x7 +#define RG_XO_EXTBUF_RFCK1B_RSEL_SHIFT 3 +#define XO_RFCK1C_MODE_ADDR MT6685_DCXO_EXTBUF8_CW0 +#define XO_RFCK1C_EN_M_ADDR MT6685_DCXO_EXTBUF8_CW0 +#define XO_RFCK1C_EN_M_MASK 0x1 +#define XO_RFCK1C_EN_M_SHIFT 2 +#define RG_XO_EXTBUF_RFCK1C_RSEL_ADDR MT6685_DCXO_EXTBUF8_CW0 +#define RG_XO_EXTBUF_RFCK1C_RSEL_MASK 0x7 +#define RG_XO_EXTBUF_RFCK1C_RSEL_SHIFT 3 +#define XO_RFCK2A_MODE_ADDR MT6685_DCXO_EXTBUF9_CW0 +#define XO_RFCK2A_EN_M_ADDR MT6685_DCXO_EXTBUF9_CW0 +#define XO_RFCK2A_EN_M_MASK 0x1 +#define XO_RFCK2A_EN_M_SHIFT 2 +#define RG_XO_EXTBUF_RFCK2A_RSEL_ADDR MT6685_DCXO_EXTBUF9_CW0 +#define RG_XO_EXTBUF_RFCK2A_RSEL_MASK 0x7 +#define RG_XO_EXTBUF_RFCK2A_RSEL_SHIFT 3 +#define XO_RFCK2B_MODE_ADDR MT6685_DCXO_EXTBUF10_CW0 +#define XO_RFCK2B_EN_M_ADDR MT6685_DCXO_EXTBUF10_CW0 +#define XO_RFCK2B_EN_M_MASK 0x1 +#define XO_RFCK2B_EN_M_SHIFT 2 +#define RG_XO_EXTBUF_RFCK2B_RSEL_ADDR MT6685_DCXO_EXTBUF10_CW0 +#define RG_XO_EXTBUF_RFCK2B_RSEL_MASK 0x7 +#define RG_XO_EXTBUF_RFCK2B_RSEL_SHIFT 3 +#define XO_RFCK2C_MODE_ADDR MT6685_DCXO_EXTBUF11_CW0 +#define XO_RFCK2C_EN_M_ADDR MT6685_DCXO_EXTBUF11_CW0 +#define XO_RFCK2C_EN_M_MASK 0x1 +#define XO_RFCK2C_EN_M_SHIFT 2 +#define RG_XO_EXTBUF_RFCK2C_RSEL_ADDR MT6685_DCXO_EXTBUF11_CW0 +#define RG_XO_EXTBUF_RFCK2C_RSEL_MASK 0x7 +#define RG_XO_EXTBUF_RFCK2C_RSEL_SHIFT 3 +#define XO_CONCK1_MODE_ADDR MT6685_DCXO_EXTBUF12_CW0 +#define XO_CONCK1_EN_M_ADDR MT6685_DCXO_EXTBUF12_CW0 +#define XO_CONCK1_EN_M_MASK 0x1 +#define XO_CONCK1_EN_M_SHIFT 2 +#define RG_XO_EXTBUF_CONCK1_RSEL_ADDR MT6685_DCXO_EXTBUF12_CW0 +#define RG_XO_EXTBUF_CONCK1_RSEL_MASK 0x7 +#define RG_XO_EXTBUF_CONCK1_RSEL_SHIFT 3 +#define XO_CONCK2_MODE_ADDR MT6685_DCXO_EXTBUF13_CW0 +#define XO_CONCK2_EN_M_ADDR MT6685_DCXO_EXTBUF13_CW0 +#define XO_CONCK2_EN_M_MASK 0x1 +#define XO_CONCK2_EN_M_SHIFT 2 +#define RG_XO_EXTBUF_CONCK2_RSEL_ADDR MT6685_DCXO_EXTBUF13_CW0 +#define RG_XO_EXTBUF_CONCK2_RSEL_MASK 0x7 +#define RG_XO_EXTBUF_CONCK2_RSEL_SHIFT 3 +#define XO_AUXOUT_SEL_L_ADDR MT6685_DCXO_RGMON_CW0_L +#define XO_AUXOUT_SEL_L_MASK 0xff +#define XO_AUXOUT_SEL_L_SHIFT 0 +#define XO_AUXOUT_SEL_H_ADDR MT6685_DCXO_RGMON_CW0_H +#define XO_AUXOUT_SEL_H_MASK 0x3 +#define XO_AUXOUT_SEL_H_SHIFT 0 +#define XO_STATIC_AUXOUT_L_ADDR MT6685_DCXO_RGMON_CW2_L +#define XO_STATIC_AUXOUT_L_MASK 0xff +#define XO_STATIC_AUXOUT_L_SHIFT 0 +#define XO_STATIC_AUXOUT_H_ADDR MT6685_DCXO_RGMON_CW2_H +#define XO_STATIC_AUXOUT_H_MASK 0xff +#define XO_STATIC_AUXOUT_H_SHIFT 0 +#define XO_STATIC_AUXOUT_SEL_ADDR MT6685_DCXO_RGMON_CW1 +#define XO_STATIC_AUXOUT_SEL_MASK 0x7f +#define XO_STATIC_AUXOUT_SEL_SHIFT 0 +#define RG_XO_DIG26M_DIV2_ADDR MT6685_DCXO_DIGCLK_ELR +#define RG_XO_DIG26M_DIV2_MASK 0x1 +#define RG_XO_DIG26M_DIV2_SHIFT 0 +/* Register_LDO_REG */ +#define RG_LDO_VBBCK_EN_ADDR MT6685_LDO_VBBCK_CON0 +#define RG_LDO_VBBCK_EN_MASK 0x1 +#define RG_LDO_VBBCK_EN_SHIFT 0 +#define RG_LDO_VBBCK_HW14_OP_EN_ADDR MT6685_LDO_VBBCK_OP_EN1 +#define RG_LDO_VBBCK_HW14_OP_EN_MASK 0x1 +#define RG_LDO_VBBCK_HW14_OP_EN_SHIFT 6 +#define RG_LDO_VRFCK1_EN_ADDR MT6685_LDO_VRFCK1_CON0 +#define RG_LDO_VRFCK1_EN_MASK 0x1 +#define RG_LDO_VRFCK1_EN_SHIFT 0 +#define RG_LDO_VRFCK1_HW14_OP_EN_ADDR MT6685_LDO_VRFCK1_OP_EN1 +#define RG_LDO_VRFCK1_HW14_OP_EN_MASK 0x1 +#define RG_LDO_VRFCK1_HW14_OP_EN_SHIFT 6 +#define RG_LDO_VRFCK2_EN_ADDR MT6685_LDO_VRFCK2_CON0 +#define RG_LDO_VRFCK2_EN_MASK 0x1 +#define RG_LDO_VRFCK2_EN_SHIFT 0 +#define RG_LDO_VRFCK2_HW14_OP_EN_ADDR MT6685_LDO_VRFCK2_OP_EN1 +#define RG_LDO_VRFCK2_HW14_OP_EN_MASK 0x1 +#define RG_LDO_VRFCK2_HW14_OP_EN_SHIFT 6 + +/* PMIF Register */ +#define PMIFSPMI_INF_EN (PMIF_SPMI_BASE + 0x0024) +#define PMIFSPMI_INF_EN_SRCLKEN_RC_HW_MSK 0x1 +#define PMIFSPMI_INF_EN_SRCLKEN_RC_HW_SHFT 4 + +#define PMIFSPMI_OTHER_INF_EN (PMIF_SPMI_BASE + 0x0028) +#define SPMI_OTHER_INF_DCXO0_EN_MSK 0x1 +#define SPMI_OTHER_INF_DCXO0_EN_SHFT 0 +#define SPMI_OTHER_INF_DCXO1_EN_MSK 0x1 +#define SPMI_OTHER_INF_DCXO1_EN_SHFT 1 + +#define PMIFSPMI_ARB_EN (PMIF_SPMI_BASE + 0x0150) +#define PMIFSPMI_ARB_EN_SRCLKEN_RC_HW_MSK 0x1 +#define PMIFSPMI_ARB_EN_SRCLKEN_RC_HW_SHFT 4 +#define PMIFSPMI_ARB_EN_DCXO_CONN_MSK 0x1 +#define PMIFSPMI_ARB_EN_DCXO_CONN_SHFT 17 +#define PMIFSPMI_ARB_EN_DCXO_NFC_MSK 0x1 +#define PMIFSPMI_ARB_EN_DCXO_NFC_SHFT 18 + +#define PMIFSPMI_SLEEP_PROTECTION_CRL (PMIF_SPMI_BASE + 0x03F0) +#define PMIFSPMI_SPM_SLEEP_REQ_SEL_MSK 0x3 +#define PMIFSPMI_SPM_SLEEP_REQ_SEL_SHFT 0 +#define PMIFSPMI_SCP_SLEEP_REQ_SEL_MSK 0x3 +#define PMIFSPMI_SCP_SLEEP_REQ_SEL_SHFT 9 + +#define PMIFSPMI_MODE_CRL (PMIF_SPMI_BASE + 0x0408) +#define PMIFSPMI_MD_CTL_PMIF_RDY_MSK 0x1 +#define PMIFSPMI_MD_CTL_PMIF_RDY_SHFT 9 +#define PMIFSPMI_MD_CTL_SRCLK_EN_MSK 0x1 +#define PMIFSPMI_MD_CTL_SRCLK_EN_SHFT 10 +#define PMIFSPMI_MD_CTL_SRVOL_EN_MSK 0x1 +#define PMIFSPMI_MD_CTL_SRVOL_EN_SHFT 11 + +enum { + CLOCK_BUFFER_DISABLE, + CLOCK_BUFFER_SW_CONTROL, + CLOCK_BUFFER_HW_CONTROL, +}; + +enum { + CLK_BUF_OUTPUT_IMPEDANCE_0, + CLK_BUF_OUTPUT_IMPEDANCE_1, + CLK_BUF_OUTPUT_IMPEDANCE_2, + CLK_BUF_OUTPUT_IMPEDANCE_3, + CLK_BUF_OUTPUT_IMPEDANCE_4, + CLK_BUF_OUTPUT_IMPEDANCE_5, + CLK_BUF_OUTPUT_IMPEDANCE_6, + CLK_BUF_OUTPUT_IMPEDANCE_7, +}; + +enum { + CLK_BUF_DRIVING_STRENGTH_0,/* Max */ + CLK_BUF_DRIVING_STRENGTH_1, + CLK_BUF_DRIVING_STRENGTH_2, + CLK_BUF_DRIVING_STRENGTH_3,/* Min */ +}; + +#define BBCK_BUF1_STATUS_PMIC CLOCK_BUFFER_HW_CONTROL +#define BBCK_BUF2_STATUS_PMIC CLOCK_BUFFER_HW_CONTROL +#define BBCK_BUF3_STATUS_PMIC CLOCK_BUFFER_DISABLE +#define BBCK_BUF4_STATUS_PMIC CLOCK_BUFFER_DISABLE +#define BBCK_BUF5_STATUS_PMIC CLOCK_BUFFER_DISABLE +#define RFCK_BUF1A_STATUS_PMIC CLOCK_BUFFER_DISABLE +#define RFCK_BUF1B_STATUS_PMIC CLOCK_BUFFER_HW_CONTROL +#define RFCK_BUF2A_STATUS_PMIC CLOCK_BUFFER_DISABLE +#define RFCK_BUF2B_STATUS_PMIC CLOCK_BUFFER_DISABLE + +#define BBCK_BUF1_OUTPUT_IMPEDANCE CLK_BUF_OUTPUT_IMPEDANCE_7 +#define BBCK_BUF2_OUTPUT_IMPEDANCE CLK_BUF_OUTPUT_IMPEDANCE_7 +#define BBCK_BUF3_OUTPUT_IMPEDANCE CLK_BUF_OUTPUT_IMPEDANCE_7 +#define BBCK_BUF4_OUTPUT_IMPEDANCE CLK_BUF_OUTPUT_IMPEDANCE_7 +#define BBCK_BUF5_OUTPUT_IMPEDANCE CLK_BUF_OUTPUT_IMPEDANCE_7 +#define RFCK_BUF1A_OUTPUT_IMPEDANCE CLK_BUF_OUTPUT_IMPEDANCE_1 +#define RFCK_BUF1B_OUTPUT_IMPEDANCE CLK_BUF_OUTPUT_IMPEDANCE_1 +#define RFCK_BUF2A_OUTPUT_IMPEDANCE CLK_BUF_OUTPUT_IMPEDANCE_1 +#define RFCK_BUF2B_OUTPUT_IMPEDANCE CLK_BUF_OUTPUT_IMPEDANCE_1 + +#define BBCK_BUF1_DRIVING_STRENGTH CLK_BUF_DRIVING_STRENGTH_2 +#define BBCK_BUF2_DRIVING_STRENGTH CLK_BUF_DRIVING_STRENGTH_2 +#define BBCK_BUF3_DRIVING_STRENGTH CLK_BUF_DRIVING_STRENGTH_2 +#define BBCK_BUF4_DRIVING_STRENGTH CLK_BUF_DRIVING_STRENGTH_2 +#define BBCK_BUF5_DRIVING_STRENGTH CLK_BUF_DRIVING_STRENGTH_2 + +enum pmic_interface_clkbuf { + PMIF_VLD_RDY_CLKBUF = 0, + PMIF_SLP_REQ_CLKBUF, + PMIF_MAX, +}; + +/* XO id: Update this enum for porting */ +enum xo_id { + XO_BBCK1 = 0, + XO_BBCK2, + XO_BBCK3, + XO_BBCK4, + XO_BBCK5, + XO_RFCK1A, + XO_RFCK1B, + XO_RFCK1C, + XO_RFCK2A, + XO_RFCK2B, + XO_RFCK2C, + XO_CONCK1, + XO_CONCK2, + XO_NUMBER, +}; + +struct ox_cfg { + u32 reg; + u8 mode; + u8 impedance; + u8 driving; + struct { + u8 low_byte; + u8 high_byte; + } voter_mask; +}; + +int clk_buf_init(void); +u16 clk_buf_get_pmrc_en0(void); + +#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/85841?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie18bfbb2f3354ba3645799857061dc20de7f6d84 Gerrit-Change-Number: 85841 Gerrit-PatchSet: 8 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ot_song fan <ot_song.fan(a)mediatek.corp-partner.google.com>

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[S] Change in coreboot[main]: soc/mediatek/common/dp: Use assert to check read/write API params
by Yidi Lin (Code Review) 11 Jan '25

11 Jan '25

Yidi Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85931?usp=email ) Change subject: soc/mediatek/common/dp: Use assert to check read/write API params ...................................................................... soc/mediatek/common/dp: Use assert to check read/write API params With CB:85918 and CB:85930, we can clean up the TODO in mtk_dp_mask. Follow DP Phy APIs to use `assert` for the param examination. TEST=verified on Ciri and Navi Change-Id: I94e6ad36d190d773876cbb43eb4ebe17164f3c92 Signed-off-by: Yidi Lin <yidilin(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85931 Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/mediatek/common/dp/dptx_hal_common.c 1 file changed, 8 insertions(+), 20 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved diff --git a/src/soc/mediatek/common/dp/dptx_hal_common.c b/src/soc/mediatek/common/dp/dptx_hal_common.c index 89da19c..fda1b4f 100644 --- a/src/soc/mediatek/common/dp/dptx_hal_common.c +++ b/src/soc/mediatek/common/dp/dptx_hal_common.c @@ -16,11 +16,8 @@ { void *addr = mtk_dp->regs + offset; - if (offset % 4 != 0 || offset > REG_OFFSET_LIMIT) { - printk(BIOS_ERR, "[%s] invalid offset %#x for reg %p\n", __func__, offset, - mtk_dp->regs); - return 0; - } + assert(mtk_dp->regs); + assert(offset % 4 == 0 && offset <= REG_OFFSET_LIMIT); return read32(addr); } @@ -28,11 +25,8 @@ { void *addr = mtk_dp->regs + offset; - if (offset % 4 != 0 || offset > REG_OFFSET_LIMIT) { - printk(BIOS_ERR, "[%s] invalid offset %#x for reg %p\n", __func__, offset, - mtk_dp->regs); - return; - } + assert(mtk_dp->regs); + assert(offset % 4 == 0 && offset <= REG_OFFSET_LIMIT); write32(addr, val); } @@ -41,17 +35,11 @@ { void *addr = mtk_dp->regs + offset; - if (offset % 4 != 0 || offset > REG_OFFSET_LIMIT) { - printk(BIOS_ERR, "[%s] invalid offset %#x for reg %p\n", __func__, offset, - mtk_dp->regs); - return; - } + assert(mtk_dp->regs); + assert(offset % 4 == 0 && offset <= REG_OFFSET_LIMIT); + assert((val & mask) == val); - /* - * TODO: modify to clrsetbits32(addr, mask, val); - * There is asserion error when testing assert((val & mask) == val). - */ - clrsetbits32(addr, mask, val & mask); + clrsetbits32(addr, mask, val); } void mtk_dp_write_byte(struct mtk_dp *mtk_dp, u32 addr, u8 val, u8 mask) -- To view, visit https://review.coreboot.org/c/coreboot/+/85931?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I94e6ad36d190d773876cbb43eb4ebe17164f3c92 Gerrit-Change-Number: 85931 Gerrit-PatchSet: 3 Gerrit-Owner: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: soc/mediatek/common/dp: Correct the settings in dptx_hal_set_msa
by Yidi Lin (Code Review) 11 Jan '25

11 Jan '25

Yidi Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85930?usp=email ) Change subject: soc/mediatek/common/dp: Correct the settings in dptx_hal_set_msa ...................................................................... soc/mediatek/common/dp: Correct the settings in dptx_hal_set_msa Correct the settings according to Linux kernel driver. The related settings can be found in [1]: [1]: https://github.com/torvalds/linux/blob/master/drivers/gpu/drm/mediatek/mtk_… TEST=emerge-rauru coreboot; check FW screen on Ciri and Navi Change-Id: I4ba7da74ce6394240513c482b19ec879b1a0a619 Signed-off-by: Yidi Lin <yidilin(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85930 Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/mediatek/common/dp/dptx_hal_common.c 1 file changed, 7 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved diff --git a/src/soc/mediatek/common/dp/dptx_hal_common.c b/src/soc/mediatek/common/dp/dptx_hal_common.c index 3ba95d1..89da19c 100644 --- a/src/soc/mediatek/common/dp/dptx_hal_common.c +++ b/src/soc/mediatek/common/dp/dptx_hal_common.c @@ -137,6 +137,7 @@ htotal = ha + hsync + hbp + hfp; vtotal = va + vsync + vbp + vfp; + /* horizontal */ DP_WRITE2BYTE(mtk_dp, REG_3010_DP_ENCODER0_P0, htotal); DP_WRITE2BYTE(mtk_dp, REG_3018_DP_ENCODER0_P0, hsync + hbp); mtk_dp_mask(mtk_dp, REG_3028_DP_ENCODER0_P0, @@ -146,7 +147,8 @@ 0 << HSP_SW_DP_ENCODER0_P0_FLDMASK_POS, HSP_SW_DP_ENCODER0_P0_FLDMASK); DP_WRITE2BYTE(mtk_dp, REG_3020_DP_ENCODER0_P0, ha); - DP_WRITE2BYTE(mtk_dp, REG_3014_DP_ENCODER0_P0, va); + /* vertical */ + DP_WRITE2BYTE(mtk_dp, REG_3014_DP_ENCODER0_P0, vtotal); DP_WRITE2BYTE(mtk_dp, REG_301C_DP_ENCODER0_P0, vsync + vbp); mtk_dp_mask(mtk_dp, REG_302C_DP_ENCODER0_P0, vsync << VSW_SW_DP_ENCODER0_P0_FLDMASK_POS, @@ -155,14 +157,16 @@ 0 << VSP_SW_DP_ENCODER0_P0_FLDMASK_POS, VSP_SW_DP_ENCODER0_P0_FLDMASK); DP_WRITE2BYTE(mtk_dp, REG_3024_DP_ENCODER0_P0, va); + /* horizontal */ DP_WRITE2BYTE(mtk_dp, REG_3064_DP_ENCODER0_P0, ha); DP_WRITE2BYTE(mtk_dp, REG_3154_DP_ENCODER0_P0, htotal); DP_WRITE2BYTE(mtk_dp, REG_3158_DP_ENCODER0_P0, hfp); - DP_WRITE2BYTE(mtk_dp, REG_315C_DP_ENCODER0_P0, vsync); + DP_WRITE2BYTE(mtk_dp, REG_315C_DP_ENCODER0_P0, hsync); DP_WRITE2BYTE(mtk_dp, REG_3160_DP_ENCODER0_P0, hsync + hbp); DP_WRITE2BYTE(mtk_dp, REG_3164_DP_ENCODER0_P0, ha); + /* vertical */ DP_WRITE2BYTE(mtk_dp, REG_3168_DP_ENCODER0_P0, vtotal); - DP_WRITE2BYTE(mtk_dp, REG_316C_DP_ENCODER0_P0, hfp); + DP_WRITE2BYTE(mtk_dp, REG_316C_DP_ENCODER0_P0, vfp); DP_WRITE2BYTE(mtk_dp, REG_3170_DP_ENCODER0_P0, vsync); DP_WRITE2BYTE(mtk_dp, REG_3174_DP_ENCODER0_P0, vsync + vbp); DP_WRITE2BYTE(mtk_dp, REG_3178_DP_ENCODER0_P0, va); -- To view, visit https://review.coreboot.org/c/coreboot/+/85930?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4ba7da74ce6394240513c482b19ec879b1a0a619 Gerrit-Change-Number: 85930 Gerrit-PatchSet: 3 Gerrit-Owner: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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coreboot-gerrit January 2025