coreboot-gerrit January 2025

coreboot-gerrit@coreboot.org

1 participants
3269 discussions

[XS] Change in coreboot[main]: soc/mediatek/common/dp: Use DP_WRITE2BYTE if possible
by Yidi Lin (Code Review) 11 Jan '25

11 Jan '25

Yidi Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85918?usp=email ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/mediatek/common/dp: Use DP_WRITE2BYTE if possible ...................................................................... soc/mediatek/common/dp: Use DP_WRITE2BYTE if possible This patch prevents wrong mask passing to mtk_dp_mask. TEST=emerge-rauru coreboot, check FW screen Change-Id: If8c801173089761db55992279045d053c60dcd86 Signed-off-by: Yidi Lin <yidilin(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85918 Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/mediatek/common/dp/dptx_hal.c M src/soc/mediatek/common/dp/dptx_hal_common.c 2 files changed, 3 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved diff --git a/src/soc/mediatek/common/dp/dptx_hal.c b/src/soc/mediatek/common/dp/dptx_hal.c index 70d69cb..28a1480 100644 --- a/src/soc/mediatek/common/dp/dptx_hal.c +++ b/src/soc/mediatek/common/dp/dptx_hal.c @@ -65,7 +65,7 @@ mtk_dp_write_byte(mtk_dp, REG_303C_DP_ENCODER0_P0 + 1, BIT(7), BIT(7)); DP_WRITE2BYTE(mtk_dp, REG_3040_DP_ENCODER0_P0, 0x2020); - mtk_dp_mask(mtk_dp, REG_3364_DP_ENCODER1_P0, 0x2020, 0xfff); + DP_WRITE2BYTE(mtk_dp, REG_3364_DP_ENCODER1_P0, 0x2020); mtk_dp_write_byte(mtk_dp, REG_3300_DP_ENCODER1_P0 + 1, 0x2, BIT(1) | BIT(0)); mtk_dp_write_byte(mtk_dp, REG_3364_DP_ENCODER1_P0 + 1, diff --git a/src/soc/mediatek/common/dp/dptx_hal_common.c b/src/soc/mediatek/common/dp/dptx_hal_common.c index 4ef07ac..3ba95d1 100644 --- a/src/soc/mediatek/common/dp/dptx_hal_common.c +++ b/src/soc/mediatek/common/dp/dptx_hal_common.c @@ -292,12 +292,12 @@ void dptx_hal_setsdp_downcnt_init_inhblanking(struct mtk_dp *mtk_dp, u16 value) { - mtk_dp_mask(mtk_dp, REG_3364_DP_ENCODER1_P0, value, 0xfff); + DP_WRITE2BYTE(mtk_dp, REG_3364_DP_ENCODER1_P0, value); } void dptx_hal_setsdp_downcnt_init(struct mtk_dp *mtk_dp, u16 value) { - mtk_dp_mask(mtk_dp, REG_3040_DP_ENCODER0_P0, value, 0xfff); + DP_WRITE2BYTE(mtk_dp, REG_3040_DP_ENCODER0_P0, value); } bool dptx_hal_auxread_bytes(struct mtk_dp *mtk_dp, u8 cmd, u32 dpcd_addr, size_t length, -- To view, visit https://review.coreboot.org/c/coreboot/+/85918?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If8c801173089761db55992279045d053c60dcd86 Gerrit-Change-Number: 85918 Gerrit-PatchSet: 3 Gerrit-Owner: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

[XS] Change in coreboot[main]: src/soc/mediatek/common/dp: Fix `mask` data type in mtk_dp_write_byte
by Yidi Lin (Code Review) 11 Jan '25

11 Jan '25

Yidi Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85917?usp=email ) Change subject: src/soc/mediatek/common/dp: Fix `mask` data type in mtk_dp_write_byte ...................................................................... src/soc/mediatek/common/dp: Fix `mask` data type in mtk_dp_write_byte TEST=emerge-rauru coreboot Change-Id: I2762d6ca024d60663f6dae0db62a959a191adc02 Signed-off-by: Yidi Lin <yidilin(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85917 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- M src/soc/mediatek/common/dp/dptx_hal_common.c M src/soc/mediatek/common/dp/include/soc/dptx_hal_common.h 2 files changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved diff --git a/src/soc/mediatek/common/dp/dptx_hal_common.c b/src/soc/mediatek/common/dp/dptx_hal_common.c index c2d6986..4ef07ac 100644 --- a/src/soc/mediatek/common/dp/dptx_hal_common.c +++ b/src/soc/mediatek/common/dp/dptx_hal_common.c @@ -54,7 +54,7 @@ clrsetbits32(addr, mask, val & mask); } -void mtk_dp_write_byte(struct mtk_dp *mtk_dp, u32 addr, u8 val, u32 mask) +void mtk_dp_write_byte(struct mtk_dp *mtk_dp, u32 addr, u8 val, u8 mask) { if (addr % 2) { mtk_dp_write(mtk_dp, DP_TX_TOP_APB_WSTRB, 0x12); diff --git a/src/soc/mediatek/common/dp/include/soc/dptx_hal_common.h b/src/soc/mediatek/common/dp/include/soc/dptx_hal_common.h index 7ed41e8..7f0e30f 100644 --- a/src/soc/mediatek/common/dp/include/soc/dptx_hal_common.h +++ b/src/soc/mediatek/common/dp/include/soc/dptx_hal_common.h @@ -69,7 +69,7 @@ void mtk_dp_phy_mask(struct mtk_dp *mtk_dp, u32 offset, u32 val, u32 mask); void mtk_dp_phy_write(struct mtk_dp *mtk_dp, u32 offset, u32 val); u32 mtk_dp_read(struct mtk_dp *mtk_dp, u32 offset); -void mtk_dp_write_byte(struct mtk_dp *mtk_dp, u32 addr, u8 val, u32 mask); +void mtk_dp_write_byte(struct mtk_dp *mtk_dp, u32 addr, u8 val, u8 mask); void mtk_dp_mask(struct mtk_dp *mtk_dp, u32 offset, u32 val, u32 mask); void mtk_dp_write(struct mtk_dp *mtk_dp, u32 offset, u32 val); void dptx_hal_verify_clock(struct mtk_dp *mtk_dp); -- To view, visit https://review.coreboot.org/c/coreboot/+/85917?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2762d6ca024d60663f6dae0db62a959a191adc02 Gerrit-Change-Number: 85917 Gerrit-PatchSet: 3 Gerrit-Owner: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

1 0

[S] Change in coreboot[main]: soc/mediatek/common/dp: Add read/write APIs for DP Phy register
by Yidi Lin (Code Review) 11 Jan '25

11 Jan '25

Yidi Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85914?usp=email ) Change subject: soc/mediatek/common/dp: Add read/write APIs for DP Phy register ...................................................................... soc/mediatek/common/dp: Add read/write APIs for DP Phy register MT8196's eDP architecture is different from previous SoCs. DP Phy needs to be configured during the initialization. Add read/write APIs for DP Phy register configuration. Add a mock definition EDP_PHY_BASE for the SoC that do not support DP Phy configuration. BUG=b:382363408 TEST=emerge-geralt coreboot && emerge-rauru coreboot TEST=check FW screen on Navi Change-Id: I5c00d0aa7e35f03cc3c3aef6a58eadd3d334d8ed Signed-off-by: Yidi Lin <yidilin(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85914 Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/mediatek/common/dp/dptx_common.c M src/soc/mediatek/common/dp/dptx_hal_common.c M src/soc/mediatek/common/dp/include/soc/dptx_common.h M src/soc/mediatek/common/dp/include/soc/dptx_hal_common.h M src/soc/mediatek/mt8188/include/soc/dptx.h M src/soc/mediatek/mt8195/include/soc/dptx.h 6 files changed, 41 insertions(+), 0 deletions(-) Approvals: Yu-Ping Wu: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/mediatek/common/dp/dptx_common.c b/src/soc/mediatek/common/dp/dptx_common.c index 0d078cd..b43bf51 100644 --- a/src/soc/mediatek/common/dp/dptx_common.c +++ b/src/soc/mediatek/common/dp/dptx_common.c @@ -215,6 +215,7 @@ void dptx_init_variable(struct mtk_dp *mtk_dp) { mtk_dp->regs = (void *)EDP_BASE; + mtk_dp->phy_regs = (void *)EDP_PHY_BASE; mtk_dp->train_info.sys_max_linkrate = DP_LINKRATE_HBR3; mtk_dp->train_info.linkrate = DP_LINKRATE_HBR2; mtk_dp->train_info.linklane_count = DP_LANECOUNT_4; diff --git a/src/soc/mediatek/common/dp/dptx_hal_common.c b/src/soc/mediatek/common/dp/dptx_hal_common.c index a7bbad8..c2d6986 100644 --- a/src/soc/mediatek/common/dp/dptx_hal_common.c +++ b/src/soc/mediatek/common/dp/dptx_hal_common.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <assert.h> #include <console/console.h> #include <device/mmio.h> #include <delay.h> @@ -66,6 +67,37 @@ mtk_dp_write(mtk_dp, DP_TX_TOP_APB_WSTRB, 0x0); } +u32 mtk_dp_phy_read(struct mtk_dp *mtk_dp, u32 offset) +{ + void *addr = mtk_dp->phy_regs + offset; + + assert(mtk_dp->phy_regs); + assert(offset % 4 == 0 && offset <= REG_OFFSET_LIMIT); + + return read32(addr); +} + +void mtk_dp_phy_write(struct mtk_dp *mtk_dp, u32 offset, u32 val) +{ + void *addr = mtk_dp->phy_regs + offset; + + assert(mtk_dp->phy_regs); + assert(offset % 4 == 0 && offset <= REG_OFFSET_LIMIT); + + write32(addr, val); +} + +void mtk_dp_phy_mask(struct mtk_dp *mtk_dp, u32 offset, u32 val, u32 mask) +{ + void *addr = mtk_dp->phy_regs + offset; + + assert(mtk_dp->phy_regs); + assert(offset % 4 == 0 && offset <= REG_OFFSET_LIMIT); + assert((val & mask) == val); + + clrsetbits32(addr, mask, val); +} + void dptx_hal_verify_clock(struct mtk_dp *mtk_dp) { u32 m, n, ls_clk, pix_clk; diff --git a/src/soc/mediatek/common/dp/include/soc/dptx_common.h b/src/soc/mediatek/common/dp/include/soc/dptx_common.h index db686d2..1d7e135 100644 --- a/src/soc/mediatek/common/dp/include/soc/dptx_common.h +++ b/src/soc/mediatek/common/dp/include/soc/dptx_common.h @@ -198,6 +198,7 @@ u32 max_hdisplay; u32 max_vdisplay; void *regs; + void *phy_regs; int disp_status; bool power_on; bool audio_enable; diff --git a/src/soc/mediatek/common/dp/include/soc/dptx_hal_common.h b/src/soc/mediatek/common/dp/include/soc/dptx_hal_common.h index 778fe46..7ed41e8 100644 --- a/src/soc/mediatek/common/dp/include/soc/dptx_hal_common.h +++ b/src/soc/mediatek/common/dp/include/soc/dptx_hal_common.h @@ -65,6 +65,9 @@ bool dptx_hal_setswing_preemphasis(struct mtk_dp *mtk_dp, int lane_num, int swing_value, int preemphasis); u8 dptx_hal_get_colorbpp(struct mtk_dp *mtk_dp); +u32 mtk_dp_phy_read(struct mtk_dp *mtk_dp, u32 offset); +void mtk_dp_phy_mask(struct mtk_dp *mtk_dp, u32 offset, u32 val, u32 mask); +void mtk_dp_phy_write(struct mtk_dp *mtk_dp, u32 offset, u32 val); u32 mtk_dp_read(struct mtk_dp *mtk_dp, u32 offset); void mtk_dp_write_byte(struct mtk_dp *mtk_dp, u32 addr, u8 val, u32 mask); void mtk_dp_mask(struct mtk_dp *mtk_dp, u32 offset, u32 val, u32 mask); diff --git a/src/soc/mediatek/mt8188/include/soc/dptx.h b/src/soc/mediatek/mt8188/include/soc/dptx.h index 71a6ff6..c910bed 100644 --- a/src/soc/mediatek/mt8188/include/soc/dptx.h +++ b/src/soc/mediatek/mt8188/include/soc/dptx.h @@ -5,4 +5,6 @@ #include <soc/dptx_common.h> +#define EDP_PHY_BASE 0 + #endif /* __SOC_MEDIATEK_MT8188_INCLUDE_SOC_DPTX_H__ */ diff --git a/src/soc/mediatek/mt8195/include/soc/dptx.h b/src/soc/mediatek/mt8195/include/soc/dptx.h index 9af5b14..50b73ae 100644 --- a/src/soc/mediatek/mt8195/include/soc/dptx.h +++ b/src/soc/mediatek/mt8195/include/soc/dptx.h @@ -5,4 +5,6 @@ #include <soc/dptx_common.h> +#define EDP_PHY_BASE 0 + #endif /* __SOC_MEDIATEK_MT8195_INCLUDE_SOC_DPTX_H__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/85914?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5c00d0aa7e35f03cc3c3aef6a58eadd3d334d8ed Gerrit-Change-Number: 85914 Gerrit-PatchSet: 3 Gerrit-Owner: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

[XL] Change in coreboot[main]: soc/mediatek/common/dp: Move common functions to dptx_hal_common.c
by Yidi Lin (Code Review) 11 Jan '25

11 Jan '25

Yidi Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85861?usp=email ) Change subject: soc/mediatek/common/dp: Move common functions to dptx_hal_common.c ...................................................................... soc/mediatek/common/dp: Move common functions to dptx_hal_common.c Move the functions that can be shared with MT8196 to dptx_hal_common.c. BUG=b:382363408 TEST=emerge-geralt coreboot && emerge-cherry coreboot TEST=verify FW screen on Navi Change-Id: I9e151bc766c312eaf81b4220782775ef1c9d2297 Signed-off-by: Yidi Lin <yidilin(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85861 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- M src/soc/mediatek/common/dp/dptx_hal.c A src/soc/mediatek/common/dp/dptx_hal_common.c M src/soc/mediatek/mt8188/Makefile.mk M src/soc/mediatek/mt8195/Makefile.mk 4 files changed, 541 insertions(+), 559 deletions(-) Approvals: Yu-Ping Wu: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/mediatek/common/dp/dptx_hal.c b/src/soc/mediatek/common/dp/dptx_hal.c index c46f457..70d69cb 100644 --- a/src/soc/mediatek/common/dp/dptx_hal.c +++ b/src/soc/mediatek/common/dp/dptx_hal.c @@ -9,8 +9,6 @@ #include <soc/dptx_reg.h> #include <types.h> -#define REG_OFFSET_LIMIT 0x8000 - struct shift_mask { u32 shift; u32 mask; @@ -28,76 +26,6 @@ [DPTX_LANE3] = { DP_TX3_PRE_EMPH_FLDMASK_POS, DP_TX3_PRE_EMPH_FLDMASK }, }; -u32 mtk_dp_read(struct mtk_dp *mtk_dp, u32 offset) -{ - void *addr = mtk_dp->regs + offset; - - if (offset % 4 != 0 || offset > REG_OFFSET_LIMIT) { - printk(BIOS_ERR, "[%s] invalid offset %#x for reg %p\n", - __func__, offset, mtk_dp->regs); - return 0; - } - - return read32(addr); -} - -void mtk_dp_write(struct mtk_dp *mtk_dp, u32 offset, u32 val) -{ - void *addr = mtk_dp->regs + offset; - - if (offset % 4 != 0 || offset > REG_OFFSET_LIMIT) { - printk(BIOS_ERR, "[%s] invalid offset %#x for reg %p\n", - __func__, offset, mtk_dp->regs); - return; - } - - write32(addr, val); -} - -void mtk_dp_mask(struct mtk_dp *mtk_dp, u32 offset, u32 val, u32 mask) -{ - void *addr = mtk_dp->regs + offset; - - if (offset % 4 != 0 || offset > REG_OFFSET_LIMIT) { - printk(BIOS_ERR, "[%s] invalid offset %#x for reg %p\n", - __func__, offset, mtk_dp->regs); - return; - } - - /* - * TODO: modify to clrsetbits32(addr, mask, val); - * There is asserion error when testing assert((val & mask) == val). - */ - clrsetbits32(addr, mask, val & mask); -} - -void mtk_dp_write_byte(struct mtk_dp *mtk_dp, u32 addr, u8 val, u32 mask) -{ - if (addr % 2) { - mtk_dp_write(mtk_dp, DP_TX_TOP_APB_WSTRB, 0x12); - mtk_dp_mask(mtk_dp, addr - 1, val << 8, mask << 8); - } else { - mtk_dp_write(mtk_dp, DP_TX_TOP_APB_WSTRB, 0x11); - mtk_dp_mask(mtk_dp, addr, val, mask); - } - - mtk_dp_write(mtk_dp, DP_TX_TOP_APB_WSTRB, 0x0); -} - -void dptx_hal_verify_clock(struct mtk_dp *mtk_dp) -{ - u32 m, n, ls_clk, pix_clk; - - m = mtk_dp_read(mtk_dp, REG_33C8_DP_ENCODER1_P0); - n = 0x8000; - ls_clk = mtk_dp->train_info.linkrate; - ls_clk *= 27; - - pix_clk = m * ls_clk / n; - printk(BIOS_DEBUG, "DPTX calc pixel clock = %d MHz, dp_intf clock = %dMHz\n", - pix_clk, pix_clk / 4); -} - void dptx_hal_init_setting(struct mtk_dp *mtk_dp) { DP_WRITE1BYTE(mtk_dp, REG_342C_DP_TRANS_P0, 0x69); @@ -107,67 +35,6 @@ mtk_dp_mask(mtk_dp, DP_TX_TOP_IRQ_MASK, BIT(2), BIT(2)); } -void dptx_hal_bypassmsa_en(struct mtk_dp *mtk_dp, bool enable) -{ - mtk_dp_mask(mtk_dp, REG_3030_DP_ENCODER0_P0, - enable ? 0 : 0x3ff, 0x3ff); -} - -void dptx_hal_set_msa(struct mtk_dp *mtk_dp) -{ - u32 va, vsync, vbp, vfp, vtotal, ha, hsync, hbp, hfp, htotal; - struct edid *edid = mtk_dp->edid; - - va = edid->mode.va; - vsync = edid->mode.vspw; - vbp = edid->mode.vbl - edid->mode.vso - - edid->mode.vspw - edid->mode.vborder; - vfp = edid->mode.vso - edid->mode.vborder; - - ha = edid->mode.ha; - hsync = edid->mode.hspw; - hbp = edid->mode.hbl - edid->mode.hso - - edid->mode.hspw - edid->mode.hborder; - hfp = edid->mode.hso - edid->mode.hborder; - - htotal = ha + hsync + hbp + hfp; - vtotal = va + vsync + vbp + vfp; - - DP_WRITE2BYTE(mtk_dp, REG_3010_DP_ENCODER0_P0, htotal); - DP_WRITE2BYTE(mtk_dp, REG_3018_DP_ENCODER0_P0, hsync + hbp); - mtk_dp_mask(mtk_dp, REG_3028_DP_ENCODER0_P0, - hsync << HSW_SW_DP_ENCODER0_P0_FLDMASK_POS, - HSW_SW_DP_ENCODER0_P0_FLDMASK); - mtk_dp_mask(mtk_dp, REG_3028_DP_ENCODER0_P0, - 0 << HSP_SW_DP_ENCODER0_P0_FLDMASK_POS, - HSP_SW_DP_ENCODER0_P0_FLDMASK); - DP_WRITE2BYTE(mtk_dp, REG_3020_DP_ENCODER0_P0, ha); - DP_WRITE2BYTE(mtk_dp, REG_3014_DP_ENCODER0_P0, va); - DP_WRITE2BYTE(mtk_dp, REG_301C_DP_ENCODER0_P0, vsync + vbp); - mtk_dp_mask(mtk_dp, REG_302C_DP_ENCODER0_P0, - vsync << VSW_SW_DP_ENCODER0_P0_FLDMASK_POS, - VSW_SW_DP_ENCODER0_P0_FLDMASK); - mtk_dp_mask(mtk_dp, REG_302C_DP_ENCODER0_P0, - 0 << VSP_SW_DP_ENCODER0_P0_FLDMASK_POS, - VSP_SW_DP_ENCODER0_P0_FLDMASK); - DP_WRITE2BYTE(mtk_dp, REG_3024_DP_ENCODER0_P0, va); - DP_WRITE2BYTE(mtk_dp, REG_3064_DP_ENCODER0_P0, ha); - DP_WRITE2BYTE(mtk_dp, REG_3154_DP_ENCODER0_P0, htotal); - DP_WRITE2BYTE(mtk_dp, REG_3158_DP_ENCODER0_P0, hfp); - DP_WRITE2BYTE(mtk_dp, REG_315C_DP_ENCODER0_P0, vsync); - DP_WRITE2BYTE(mtk_dp, REG_3160_DP_ENCODER0_P0, hsync + hbp); - DP_WRITE2BYTE(mtk_dp, REG_3164_DP_ENCODER0_P0, ha); - DP_WRITE2BYTE(mtk_dp, REG_3168_DP_ENCODER0_P0, vtotal); - DP_WRITE2BYTE(mtk_dp, REG_316C_DP_ENCODER0_P0, hfp); - DP_WRITE2BYTE(mtk_dp, REG_3170_DP_ENCODER0_P0, vsync); - DP_WRITE2BYTE(mtk_dp, REG_3174_DP_ENCODER0_P0, vsync + vbp); - DP_WRITE2BYTE(mtk_dp, REG_3178_DP_ENCODER0_P0, va); - - printk(BIOS_INFO, "MSA:Htt(%d), Vtt(%d), Hact(%d), Vact(%d), FPS(%d)\n", - htotal, vtotal, ha, va, - edid->mode.pixel_clock * 1000 / htotal / vtotal); -} - void dptx_hal_set_color_format(struct mtk_dp *mtk_dp, u8 out_format) { /* MISC0 */ @@ -193,144 +60,6 @@ } } -void dptx_hal_set_color_depth(struct mtk_dp *mtk_dp, u8 color_depth) -{ - u8 val; - - mtk_dp_write_byte(mtk_dp, REG_3034_DP_ENCODER0_P0, - color_depth << 0x5, 0xe0); - - switch (color_depth) { - case DP_COLOR_DEPTH_6BIT: - val = 4; - break; - case DP_COLOR_DEPTH_8BIT: - val = 3; - break; - case DP_COLOR_DEPTH_10BIT: - val = 2; - break; - case DP_COLOR_DEPTH_12BIT: - val = 1; - break; - case DP_COLOR_DEPTH_16BIT: - val = 0; - break; - default: - return; - } - mtk_dp_write_byte(mtk_dp, REG_303C_DP_ENCODER0_P0 + 1, val, 0x7); -} - -void dptx_hal_setmisc(struct mtk_dp *mtk_dp, u8 cmisc[2]) -{ - mtk_dp_write_byte(mtk_dp, REG_3034_DP_ENCODER0_P0, cmisc[0], 0xfe); - mtk_dp_write_byte(mtk_dp, REG_3034_DP_ENCODER0_P0 + 1, cmisc[1], 0xff); -} - -void dptx_hal_overwrite_mn(struct mtk_dp *mtk_dp, - bool enable, u32 video_m, u32 video_n) -{ - if (enable) { - /* Turn on overwrite MN */ - DP_WRITE2BYTE(mtk_dp, REG_3008_DP_ENCODER0_P0, - video_m & 0xffff); - DP_WRITE1BYTE(mtk_dp, REG_300C_DP_ENCODER0_P0, - (video_m >> 16) & 0xff); - DP_WRITE2BYTE(mtk_dp, REG_3044_DP_ENCODER0_P0, - video_n & 0xffff); - DP_WRITE1BYTE(mtk_dp, REG_3048_DP_ENCODER0_P0, - (video_n >> 16) & 0xff); - DP_WRITE2BYTE(mtk_dp, REG_3050_DP_ENCODER0_P0, - video_n & 0xffff); - - /* Add legerII. */ - DP_WRITE1BYTE(mtk_dp, REG_3054_DP_ENCODER0_P0, - (video_n >> 16) & 0xff); - mtk_dp_write_byte(mtk_dp, REG_3004_DP_ENCODER0_P0 + 1, - BIT(0), BIT(0)); - } else { - /* Turn off overwrite MN */ - mtk_dp_write_byte(mtk_dp, REG_3004_DP_ENCODER0_P0 + 1, - 0, BIT(0)); - } -} - -u8 dptx_hal_get_colorbpp(struct mtk_dp *mtk_dp) -{ - u8 color_bpp; - u8 color_depth = mtk_dp->info.depth; - u8 color_format = mtk_dp->info.format; - - switch (color_depth) { - case DP_COLOR_DEPTH_6BIT: - if (color_format == DP_COLOR_FORMAT_YUV_422) - color_bpp = 16; - else if (color_format == DP_COLOR_FORMAT_YUV_420) - color_bpp = 12; - else - color_bpp = 18; - break; - case DP_COLOR_DEPTH_8BIT: - if (color_format == DP_COLOR_FORMAT_YUV_422) - color_bpp = 16; - else if (color_format == DP_COLOR_FORMAT_YUV_420) - color_bpp = 12; - else - color_bpp = 24; - break; - case DP_COLOR_DEPTH_10BIT: - if (color_format == DP_COLOR_FORMAT_YUV_422) - color_bpp = 20; - else if (color_format == DP_COLOR_FORMAT_YUV_420) - color_bpp = 15; - else - color_bpp = 30; - break; - case DP_COLOR_DEPTH_12BIT: - if (color_format == DP_COLOR_FORMAT_YUV_422) - color_bpp = 24; - else if (color_format == DP_COLOR_FORMAT_YUV_420) - color_bpp = 18; - else - color_bpp = 36; - break; - case DP_COLOR_DEPTH_16BIT: - if (color_format == DP_COLOR_FORMAT_YUV_422) - color_bpp = 32; - else if (color_format == DP_COLOR_FORMAT_YUV_420) - color_bpp = 24; - else - color_bpp = 48; - break; - default: - color_bpp = 24; - printk(BIOS_ERR, "Set wrong bpp = %d\n", color_bpp); - break; - } - - return color_bpp; -} - -void dptx_hal_settu_sramrd_start(struct mtk_dp *mtk_dp, u16 value) -{ - /* - * [5:0] video sram start address - * modify in 480P case only, default=0x1f - */ - mtk_dp_write_byte(mtk_dp, REG_303C_DP_ENCODER0_P0, (u8)value, 0x3f); -} - -void dptx_hal_setsdp_downcnt_init_inhblanking(struct mtk_dp *mtk_dp, u16 value) -{ - mtk_dp_mask(mtk_dp, REG_3364_DP_ENCODER1_P0, value, 0xfff); -} - -void dptx_hal_setsdp_downcnt_init(struct mtk_dp *mtk_dp, u16 value) -{ - mtk_dp_mask(mtk_dp, REG_3040_DP_ENCODER0_P0, value, 0xfff); -} - void dptx_hal_settu_setencoder(struct mtk_dp *mtk_dp) { mtk_dp_write_byte(mtk_dp, REG_303C_DP_ENCODER0_P0 + 1, @@ -349,211 +78,6 @@ return mtk_dp_read(mtk_dp, REG_3414_DP_TRANS_P0) & BIT(2); } -bool dptx_hal_auxread_bytes(struct mtk_dp *mtk_dp, u8 cmd, - u32 dpcd_addr, size_t length, u8 *rx_buf) -{ - bool valid_cmd = false; - u8 reply_cmd, aux_irq_status; - int rd_count; - u32 wait_reply_count = AUX_WAITREPLY_LPNUM; - - DP_WRITE1BYTE(mtk_dp, REG_3640_AUX_TX_P0, 0x7f); - mdelay(1); - - if (length > 16 || (cmd == AUX_CMD_NATIVE_R && length == 0x0)) - return false; - - DP_WRITE1BYTE(mtk_dp, REG_3650_AUX_TX_P0 + 1, 0x1); - DP_WRITE1BYTE(mtk_dp, REG_3644_AUX_TX_P0, cmd); - DP_WRITE2BYTE(mtk_dp, REG_3648_AUX_TX_P0, dpcd_addr & 0xffff); - DP_WRITE1BYTE(mtk_dp, REG_364C_AUX_TX_P0, (dpcd_addr >> 16) & 0xf); - - if (length > 0) { - mtk_dp_mask(mtk_dp, REG_3650_AUX_TX_P0, - (length - 1) << MCU_REQ_DATA_NUM_AUX_TX_P0_FLDMASK_POS, - MCU_REQUEST_DATA_NUM_AUX_TX_P0_FLDMASK); - DP_WRITE1BYTE(mtk_dp, REG_362C_AUX_TX_P0, 0x0); - } - - if (cmd == AUX_CMD_I2C_R || cmd == AUX_CMD_I2C_R_MOT0) - if (length == 0x0) - mtk_dp_mask(mtk_dp, REG_362C_AUX_TX_P0, - 0x1 << AUX_NO_LENGTH_AUX_TX_P0_FLDMASK_POS, - AUX_NO_LENGTH_AUX_TX_P0_FLDMASK); - - mtk_dp_mask(mtk_dp, REG_3630_AUX_TX_P0, - 0x1 << AUX_TX_REQUEST_READY_AUX_TX_P0_FLDMASK_POS, - AUX_TX_REQUEST_READY_AUX_TX_P0_FLDMASK); - - while (--wait_reply_count) { - if (mtk_dp_read(mtk_dp, REG_3618_AUX_TX_P0) & - AUX_RX_FIFO_WRITE_POINTER_AUX_TX_P0_FLDMASK) { - valid_cmd = true; - break; - } - - if (mtk_dp_read(mtk_dp, REG_3618_AUX_TX_P0) & - AUX_RX_FIFO_FULL_AUX_TX_P0_FLDMASK) { - valid_cmd = true; - break; - } - - aux_irq_status = mtk_dp_read(mtk_dp, REG_3640_AUX_TX_P0) & 0xff; - - if (aux_irq_status & AUX_RX_RECV_COMPLETE_IRQ_TX_P0_FLDMASK) { - valid_cmd = true; - break; - } - - if (aux_irq_status & AUX_400US_TIMEOUT_IRQ_AUX_TX_P0_FLDMASK) { - printk(BIOS_ERR, "(AUX Read)HW Timeout 400us irq\n"); - break; - } - } - - reply_cmd = mtk_dp_read(mtk_dp, REG_3624_AUX_TX_P0) & 0xf; - if (reply_cmd) - printk(BIOS_ERR, "reply_cmd(%#x), NACK or Defer\n", reply_cmd); - - if (wait_reply_count == 0x0 || reply_cmd) { - u8 phy_status = 0x0; - - phy_status = mtk_dp_read(mtk_dp, REG_3628_AUX_TX_P0); - if (phy_status != 0x1) - printk(BIOS_ERR, "Aux read: aux hang, need sw reset\n"); - - mtk_dp_mask(mtk_dp, REG_3650_AUX_TX_P0, - 0x1 << MCU_ACK_TRAN_COMPLETE_AUX_TX_P0_FLDMASK_POS, - MCU_ACK_TRANSACTION_COMPLETE_AUX_TX_P0_FLDMASK); - DP_WRITE1BYTE(mtk_dp, REG_3640_AUX_TX_P0, 0x7f); - - mdelay(1); - printk(BIOS_ERR, "wait_reply_count(%#x), TimeOut\n", - wait_reply_count); - return false; - } - - if (length == 0) { - DP_WRITE1BYTE(mtk_dp, REG_362C_AUX_TX_P0, 0x0); - } else { - if (valid_cmd) { - mtk_dp_mask(mtk_dp, REG_3620_AUX_TX_P0, - 0x0 << AUX_RD_MODE_AUX_TX_P0_FLDMASK_POS, - AUX_RD_MODE_AUX_TX_P0_FLDMASK); - - for (rd_count = 0; rd_count < length; rd_count++) { - mtk_dp_mask(mtk_dp, REG_3620_AUX_TX_P0, - 0x1 << AUX_RX_FIFO_R_PULSE_TX_P0_FLDMASK_POS, - AUX_RX_FIFO_READ_PULSE_TX_P0_FLDMASK); - mdelay(1); - *(rx_buf + rd_count) = mtk_dp_read(mtk_dp, - REG_3620_AUX_TX_P0); - } - } else { - printk(BIOS_INFO, "Read TimeOut %#x\n", dpcd_addr); - } - } - - mtk_dp_mask(mtk_dp, REG_3650_AUX_TX_P0, - 0x1 << MCU_ACK_TRAN_COMPLETE_AUX_TX_P0_FLDMASK_POS, - MCU_ACK_TRANSACTION_COMPLETE_AUX_TX_P0_FLDMASK); - DP_WRITE1BYTE(mtk_dp, REG_3640_AUX_TX_P0, 0x7f); - - mdelay(1); - return valid_cmd; -} - -bool dptx_hal_auxwrite_bytes(struct mtk_dp *mtk_dp, u8 cmd, - u32 dpcd_addr, size_t length, u8 *data) -{ - bool valid_cmd = false; - u8 reply_cmd; - int i; - u16 wait_reply_count = AUX_WAITREPLY_LPNUM; - int reg_idx; - - mtk_dp_write_byte(mtk_dp, REG_3704_AUX_TX_P0, - 1 << AUX_TX_FIFO_NEW_MODE_EN_AUX_TX_P0_FLDMASK_POS, - AUX_TX_FIFO_NEW_MODE_EN_AUX_TX_P0_FLDMASK); - DP_WRITE1BYTE(mtk_dp, REG_3650_AUX_TX_P0 + 1, 0x1); - DP_WRITE1BYTE(mtk_dp, REG_3640_AUX_TX_P0, 0x7f); - mdelay(1); - - DP_WRITE1BYTE(mtk_dp, REG_3650_AUX_TX_P0 + 1, 0x1); - DP_WRITE1BYTE(mtk_dp, REG_3644_AUX_TX_P0, cmd); - DP_WRITE1BYTE(mtk_dp, REG_3648_AUX_TX_P0, dpcd_addr & 0xff); - DP_WRITE1BYTE(mtk_dp, REG_3648_AUX_TX_P0 + 1, - (dpcd_addr >> 8) & 0xff); - DP_WRITE1BYTE(mtk_dp, REG_364C_AUX_TX_P0, - (dpcd_addr >> 16) & 0xf); - - if (length > 0) { - DP_WRITE1BYTE(mtk_dp, REG_362C_AUX_TX_P0, 0x0); - for (i = 0; i < (length + 1) / 2; i++) - for (reg_idx = 0; reg_idx < 2; reg_idx++) - if ((i * 2 + reg_idx) < length) - DP_WRITE1BYTE(mtk_dp, - REG_3708_AUX_TX_P0 + i * 4 + reg_idx, - data[i * 2 + reg_idx]); - DP_WRITE1BYTE(mtk_dp, REG_3650_AUX_TX_P0 + 1, - ((length - 1) & 0xf) << 4); - } else { - DP_WRITE1BYTE(mtk_dp, REG_362C_AUX_TX_P0, 0x1); - } - - mtk_dp_write_byte(mtk_dp, REG_3704_AUX_TX_P0, - AUX_TX_FIFO_WRITE_DATA_NEW_MODE_TOGGLE_AUX_TX_P0_FLDMASK, - AUX_TX_FIFO_WRITE_DATA_NEW_MODE_TOGGLE_AUX_TX_P0_FLDMASK); - DP_WRITE1BYTE(mtk_dp, REG_3630_AUX_TX_P0, 0x8); - - while (--wait_reply_count) { - u8 aux_irq_status; - - aux_irq_status = mtk_dp_read(mtk_dp, REG_3640_AUX_TX_P0) & 0xff; - mdelay(1); - if (aux_irq_status & AUX_RX_RECV_COMPLETE_IRQ_TX_P0_FLDMASK) { - valid_cmd = true; - break; - } - - if (aux_irq_status & AUX_400US_TIMEOUT_IRQ_AUX_TX_P0_FLDMASK) - break; - } - - reply_cmd = mtk_dp_read(mtk_dp, REG_3624_AUX_TX_P0) & 0xf; - if (reply_cmd) - printk(BIOS_ERR, "reply_cmd(%#x), NACK or Defer\n", reply_cmd); - - if (wait_reply_count == 0x0 || reply_cmd) { - u8 phy_status = 0x0; - - phy_status = mtk_dp_read(mtk_dp, REG_3628_AUX_TX_P0); - if (phy_status != 0x1) - printk(BIOS_ERR, - "Aux write: aux hang, need SW reset!\n"); - - DP_WRITE1BYTE(mtk_dp, REG_3650_AUX_TX_P0 + 1, 0x1); - DP_WRITE1BYTE(mtk_dp, REG_3640_AUX_TX_P0, 0x7f); - - mdelay(1); - - printk(BIOS_INFO, "reply_cmd(%#x), wait_reply_count(%d)\n", - reply_cmd, wait_reply_count); - return false; - } - - DP_WRITE1BYTE(mtk_dp, REG_3650_AUX_TX_P0 + 1, 0x1); - - if (length == 0) - DP_WRITE1BYTE(mtk_dp, REG_362C_AUX_TX_P0, 0x0); - - DP_WRITE1BYTE(mtk_dp, REG_3640_AUX_TX_P0, 0x7f); - - mdelay(1); - - return valid_cmd; -} - bool dptx_hal_setswing_preemphasis(struct mtk_dp *mtk_dp, int lane_num, int swing_value, int preemphasis) { @@ -586,13 +110,6 @@ 0, volt_preemphasis[lane].mask); } -void dptx_hal_hpd_int_en(struct mtk_dp *mtk_dp, bool enable) -{ - /* [7]:int, [6]:Con, [5]DisCon, [4]No-Use: UnMASK HPD Port */ - mtk_dp_write_byte(mtk_dp, REG_3418_DP_TRANS_P0, - enable ? 0 : GENMASK(7, 5), GENMASK(7, 5)); -} - void dptx_hal_hpd_detect_setting(struct mtk_dp *mtk_dp) { mtk_dp_write_byte(mtk_dp, REG_3410_DP_TRANS_P0, @@ -748,77 +265,3 @@ /* Power on BandGap, TPLL and Lane */ mtk_dp_write(mtk_dp, 0x2000, 0x3); } - -void dptx_hal_set_txtrainingpattern(struct mtk_dp *mtk_dp, int value) -{ - /* if Set TPS1. */ - if (value == BIT(4)) - dptx_hal_phy_setidlepattern(mtk_dp, false); - - mtk_dp_write_byte(mtk_dp, REG_3400_DP_TRANS_P0 + 1, - value, GENMASK(7, 4)); -} - -void dptx_hal_phy_setidlepattern(struct mtk_dp *mtk_dp, bool enable) -{ - mtk_dp_write_byte(mtk_dp, REG_3580_DP_TRANS_P0 + 1, - enable ? 0xf : 0x0, 0xf); -} - -void dptx_hal_set_ef_mode(struct mtk_dp *mtk_dp, bool enable) -{ - /* - * [4]: REG_enhanced_frame_mode - * [1 : 0]: REG_lane_num - */ - if (enable) - mtk_dp_write_byte(mtk_dp, REG_3000_DP_ENCODER0_P0, - BIT(4), BIT(4)); - else - mtk_dp_write_byte(mtk_dp, REG_3000_DP_ENCODER0_P0, - 0, BIT(4)); -} - -void dptx_hal_setscramble(struct mtk_dp *mtk_dp, bool enable) -{ - /* [0]: dp tx transmitter scramble enable. */ - if (enable) - mtk_dp_write_byte(mtk_dp, REG_3404_DP_TRANS_P0, - BIT(0), BIT(0)); - else - mtk_dp_write_byte(mtk_dp, REG_3404_DP_TRANS_P0, - 0, BIT(0)); -} - -void dptx_hal_videomute(struct mtk_dp *mtk_dp, bool enable) -{ - if (enable) { - mtk_dp_write_byte(mtk_dp, REG_3000_DP_ENCODER0_P0, - BIT(3) | BIT(2), BIT(3) | BIT(2)); - mtk_dp_write_byte(mtk_dp, DP_TX_SECURE_REG11, - BIT(3) | BIT(4), BIT(3) | BIT(4)); - } else { - mtk_dp_write_byte(mtk_dp, REG_3000_DP_ENCODER0_P0, - BIT(3), BIT(3) | BIT(2)); - mtk_dp_write_byte(mtk_dp, DP_TX_SECURE_REG11, - BIT(4), BIT(3) | BIT(4)); - } - printk(BIOS_DEBUG, "mute = %#x\n", read32(mtk_dp->regs + 0x402c)); -} - -void dptx_hal_analog_power_en(struct mtk_dp *mtk_dp, bool enable) -{ - if (enable) { - mtk_dp_write_byte(mtk_dp, DP_TX_TOP_RESET_AND_PROBE, - 0, BIT(4)); - mdelay(1); - mtk_dp_write_byte(mtk_dp, DP_TX_TOP_RESET_AND_PROBE, - BIT(4), BIT(4)); - } else { - DP_WRITE2BYTE(mtk_dp, TOP_OFFSET, 0x0); - mdelay(1); - DP_WRITE2BYTE(mtk_dp, 0x0034, 0x4aa); - DP_WRITE2BYTE(mtk_dp, 0x1040, 0x0); - DP_WRITE2BYTE(mtk_dp, 0x0038, 0x555); - } -} diff --git a/src/soc/mediatek/common/dp/dptx_hal_common.c b/src/soc/mediatek/common/dp/dptx_hal_common.c new file mode 100644 index 0000000..a7bbad8 --- /dev/null +++ b/src/soc/mediatek/common/dp/dptx_hal_common.c @@ -0,0 +1,539 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <device/mmio.h> +#include <delay.h> +#include <edid.h> +#include <soc/dptx.h> +#include <soc/dptx_hal.h> +#include <soc/dptx_reg.h> +#include <types.h> + +#define REG_OFFSET_LIMIT 0x8000 + +u32 mtk_dp_read(struct mtk_dp *mtk_dp, u32 offset) +{ + void *addr = mtk_dp->regs + offset; + + if (offset % 4 != 0 || offset > REG_OFFSET_LIMIT) { + printk(BIOS_ERR, "[%s] invalid offset %#x for reg %p\n", __func__, offset, + mtk_dp->regs); + return 0; + } + + return read32(addr); +} +void mtk_dp_write(struct mtk_dp *mtk_dp, u32 offset, u32 val) +{ + void *addr = mtk_dp->regs + offset; + + if (offset % 4 != 0 || offset > REG_OFFSET_LIMIT) { + printk(BIOS_ERR, "[%s] invalid offset %#x for reg %p\n", __func__, offset, + mtk_dp->regs); + return; + } + + write32(addr, val); +} + +void mtk_dp_mask(struct mtk_dp *mtk_dp, u32 offset, u32 val, u32 mask) +{ + void *addr = mtk_dp->regs + offset; + + if (offset % 4 != 0 || offset > REG_OFFSET_LIMIT) { + printk(BIOS_ERR, "[%s] invalid offset %#x for reg %p\n", __func__, offset, + mtk_dp->regs); + return; + } + + /* + * TODO: modify to clrsetbits32(addr, mask, val); + * There is asserion error when testing assert((val & mask) == val). + */ + clrsetbits32(addr, mask, val & mask); +} + +void mtk_dp_write_byte(struct mtk_dp *mtk_dp, u32 addr, u8 val, u32 mask) +{ + if (addr % 2) { + mtk_dp_write(mtk_dp, DP_TX_TOP_APB_WSTRB, 0x12); + mtk_dp_mask(mtk_dp, addr - 1, val << 8, mask << 8); + } else { + mtk_dp_write(mtk_dp, DP_TX_TOP_APB_WSTRB, 0x11); + mtk_dp_mask(mtk_dp, addr, val, mask); + } + + mtk_dp_write(mtk_dp, DP_TX_TOP_APB_WSTRB, 0x0); +} + +void dptx_hal_verify_clock(struct mtk_dp *mtk_dp) +{ + u32 m, n, ls_clk, pix_clk; + + m = mtk_dp_read(mtk_dp, REG_33C8_DP_ENCODER1_P0); + n = 0x8000; + ls_clk = mtk_dp->train_info.linkrate; + ls_clk *= 27; + + pix_clk = m * ls_clk / n; + printk(BIOS_DEBUG, "DPTX calc pixel clock = %d MHz, dp_intf clock = %dMHz\n", pix_clk, + pix_clk / 4); +} + +void dptx_hal_bypassmsa_en(struct mtk_dp *mtk_dp, bool enable) +{ + mtk_dp_mask(mtk_dp, REG_3030_DP_ENCODER0_P0, enable ? 0 : 0x3ff, 0x3ff); +} + +void dptx_hal_set_msa(struct mtk_dp *mtk_dp) +{ + u32 va, vsync, vbp, vfp, vtotal, ha, hsync, hbp, hfp, htotal; + struct edid *edid = mtk_dp->edid; + + va = edid->mode.va; + vsync = edid->mode.vspw; + vbp = edid->mode.vbl - edid->mode.vso - + edid->mode.vspw - edid->mode.vborder; + vfp = edid->mode.vso - edid->mode.vborder; + + ha = edid->mode.ha; + hsync = edid->mode.hspw; + hbp = edid->mode.hbl - edid->mode.hso - + edid->mode.hspw - edid->mode.hborder; + hfp = edid->mode.hso - edid->mode.hborder; + + htotal = ha + hsync + hbp + hfp; + vtotal = va + vsync + vbp + vfp; + + DP_WRITE2BYTE(mtk_dp, REG_3010_DP_ENCODER0_P0, htotal); + DP_WRITE2BYTE(mtk_dp, REG_3018_DP_ENCODER0_P0, hsync + hbp); + mtk_dp_mask(mtk_dp, REG_3028_DP_ENCODER0_P0, + hsync << HSW_SW_DP_ENCODER0_P0_FLDMASK_POS, + HSW_SW_DP_ENCODER0_P0_FLDMASK); + mtk_dp_mask(mtk_dp, REG_3028_DP_ENCODER0_P0, + 0 << HSP_SW_DP_ENCODER0_P0_FLDMASK_POS, + HSP_SW_DP_ENCODER0_P0_FLDMASK); + DP_WRITE2BYTE(mtk_dp, REG_3020_DP_ENCODER0_P0, ha); + DP_WRITE2BYTE(mtk_dp, REG_3014_DP_ENCODER0_P0, va); + DP_WRITE2BYTE(mtk_dp, REG_301C_DP_ENCODER0_P0, vsync + vbp); + mtk_dp_mask(mtk_dp, REG_302C_DP_ENCODER0_P0, + vsync << VSW_SW_DP_ENCODER0_P0_FLDMASK_POS, + VSW_SW_DP_ENCODER0_P0_FLDMASK); + mtk_dp_mask(mtk_dp, REG_302C_DP_ENCODER0_P0, + 0 << VSP_SW_DP_ENCODER0_P0_FLDMASK_POS, + VSP_SW_DP_ENCODER0_P0_FLDMASK); + DP_WRITE2BYTE(mtk_dp, REG_3024_DP_ENCODER0_P0, va); + DP_WRITE2BYTE(mtk_dp, REG_3064_DP_ENCODER0_P0, ha); + DP_WRITE2BYTE(mtk_dp, REG_3154_DP_ENCODER0_P0, htotal); + DP_WRITE2BYTE(mtk_dp, REG_3158_DP_ENCODER0_P0, hfp); + DP_WRITE2BYTE(mtk_dp, REG_315C_DP_ENCODER0_P0, vsync); + DP_WRITE2BYTE(mtk_dp, REG_3160_DP_ENCODER0_P0, hsync + hbp); + DP_WRITE2BYTE(mtk_dp, REG_3164_DP_ENCODER0_P0, ha); + DP_WRITE2BYTE(mtk_dp, REG_3168_DP_ENCODER0_P0, vtotal); + DP_WRITE2BYTE(mtk_dp, REG_316C_DP_ENCODER0_P0, hfp); + DP_WRITE2BYTE(mtk_dp, REG_3170_DP_ENCODER0_P0, vsync); + DP_WRITE2BYTE(mtk_dp, REG_3174_DP_ENCODER0_P0, vsync + vbp); + DP_WRITE2BYTE(mtk_dp, REG_3178_DP_ENCODER0_P0, va); + + printk(BIOS_INFO, "MSA:Htt(%d), Vtt(%d), Hact(%d), Vact(%d), FPS(%d)\n", + htotal, vtotal, ha, va, + edid->mode.pixel_clock * 1000 / htotal / vtotal); +} + +void dptx_hal_set_color_depth(struct mtk_dp *mtk_dp, u8 color_depth) +{ + u8 val; + + mtk_dp_write_byte(mtk_dp, REG_3034_DP_ENCODER0_P0, color_depth << 0x5, 0xe0); + + switch (color_depth) { + case DP_COLOR_DEPTH_6BIT: + val = 4; + break; + case DP_COLOR_DEPTH_8BIT: + val = 3; + break; + case DP_COLOR_DEPTH_10BIT: + val = 2; + break; + case DP_COLOR_DEPTH_12BIT: + val = 1; + break; + case DP_COLOR_DEPTH_16BIT: + val = 0; + break; + default: + return; + } + mtk_dp_write_byte(mtk_dp, REG_303C_DP_ENCODER0_P0 + 1, val, 0x7); +} + +void dptx_hal_setmisc(struct mtk_dp *mtk_dp, u8 cmisc[2]) +{ + mtk_dp_write_byte(mtk_dp, REG_3034_DP_ENCODER0_P0, cmisc[0], 0xfe); + mtk_dp_write_byte(mtk_dp, REG_3034_DP_ENCODER0_P0 + 1, cmisc[1], 0xff); +} + +void dptx_hal_overwrite_mn(struct mtk_dp *mtk_dp, bool enable, u32 video_m, u32 video_n) +{ + if (enable) { + /* Turn on overwrite MN */ + DP_WRITE2BYTE(mtk_dp, REG_3008_DP_ENCODER0_P0, video_m & 0xffff); + DP_WRITE1BYTE(mtk_dp, REG_300C_DP_ENCODER0_P0, (video_m >> 16) & 0xff); + DP_WRITE2BYTE(mtk_dp, REG_3044_DP_ENCODER0_P0, video_n & 0xffff); + DP_WRITE1BYTE(mtk_dp, REG_3048_DP_ENCODER0_P0, (video_n >> 16) & 0xff); + DP_WRITE2BYTE(mtk_dp, REG_3050_DP_ENCODER0_P0, video_n & 0xffff); + + /* Add legerII. */ + DP_WRITE1BYTE(mtk_dp, REG_3054_DP_ENCODER0_P0, (video_n >> 16) & 0xff); + mtk_dp_write_byte(mtk_dp, REG_3004_DP_ENCODER0_P0 + 1, BIT(0), BIT(0)); + } else { + /* Turn off overwrite MN */ + mtk_dp_write_byte(mtk_dp, REG_3004_DP_ENCODER0_P0 + 1, 0, BIT(0)); + } +} + +u8 dptx_hal_get_colorbpp(struct mtk_dp *mtk_dp) +{ + u8 color_bpp; + u8 color_depth = mtk_dp->info.depth; + u8 color_format = mtk_dp->info.format; + + switch (color_depth) { + case DP_COLOR_DEPTH_6BIT: + if (color_format == DP_COLOR_FORMAT_YUV_422) + color_bpp = 16; + else if (color_format == DP_COLOR_FORMAT_YUV_420) + color_bpp = 12; + else + color_bpp = 18; + break; + case DP_COLOR_DEPTH_8BIT: + if (color_format == DP_COLOR_FORMAT_YUV_422) + color_bpp = 16; + else if (color_format == DP_COLOR_FORMAT_YUV_420) + color_bpp = 12; + else + color_bpp = 24; + break; + case DP_COLOR_DEPTH_10BIT: + if (color_format == DP_COLOR_FORMAT_YUV_422) + color_bpp = 20; + else if (color_format == DP_COLOR_FORMAT_YUV_420) + color_bpp = 15; + else + color_bpp = 30; + break; + case DP_COLOR_DEPTH_12BIT: + if (color_format == DP_COLOR_FORMAT_YUV_422) + color_bpp = 24; + else if (color_format == DP_COLOR_FORMAT_YUV_420) + color_bpp = 18; + else + color_bpp = 36; + break; + case DP_COLOR_DEPTH_16BIT: + if (color_format == DP_COLOR_FORMAT_YUV_422) + color_bpp = 32; + else if (color_format == DP_COLOR_FORMAT_YUV_420) + color_bpp = 24; + else + color_bpp = 48; + break; + default: + color_bpp = 24; + printk(BIOS_ERR, "Set wrong bpp = %d\n", color_bpp); + break; + } + + return color_bpp; +} + +void dptx_hal_settu_sramrd_start(struct mtk_dp *mtk_dp, u16 value) +{ + /* + * [5:0] video sram start address + * modify in 480P case only, default=0x1f + */ + mtk_dp_write_byte(mtk_dp, REG_303C_DP_ENCODER0_P0, (u8)value, 0x3f); +} + +void dptx_hal_setsdp_downcnt_init_inhblanking(struct mtk_dp *mtk_dp, u16 value) +{ + mtk_dp_mask(mtk_dp, REG_3364_DP_ENCODER1_P0, value, 0xfff); +} + +void dptx_hal_setsdp_downcnt_init(struct mtk_dp *mtk_dp, u16 value) +{ + mtk_dp_mask(mtk_dp, REG_3040_DP_ENCODER0_P0, value, 0xfff); +} + +bool dptx_hal_auxread_bytes(struct mtk_dp *mtk_dp, u8 cmd, u32 dpcd_addr, size_t length, + u8 *rx_buf) +{ + bool valid_cmd = false; + u8 reply_cmd, aux_irq_status; + int rd_count; + u32 wait_reply_count = AUX_WAITREPLY_LPNUM; + + DP_WRITE1BYTE(mtk_dp, REG_3640_AUX_TX_P0, 0x7f); + mdelay(1); + + if (length > 16 || (cmd == AUX_CMD_NATIVE_R && length == 0x0)) + return false; + + DP_WRITE1BYTE(mtk_dp, REG_3650_AUX_TX_P0 + 1, 0x1); + DP_WRITE1BYTE(mtk_dp, REG_3644_AUX_TX_P0, cmd); + DP_WRITE2BYTE(mtk_dp, REG_3648_AUX_TX_P0, dpcd_addr & 0xffff); + DP_WRITE1BYTE(mtk_dp, REG_364C_AUX_TX_P0, (dpcd_addr >> 16) & 0xf); + + if (length > 0) { + mtk_dp_mask(mtk_dp, REG_3650_AUX_TX_P0, + (length - 1) << MCU_REQ_DATA_NUM_AUX_TX_P0_FLDMASK_POS, + MCU_REQUEST_DATA_NUM_AUX_TX_P0_FLDMASK); + DP_WRITE1BYTE(mtk_dp, REG_362C_AUX_TX_P0, 0x0); + } + + if (cmd == AUX_CMD_I2C_R || cmd == AUX_CMD_I2C_R_MOT0) + if (length == 0x0) + mtk_dp_mask(mtk_dp, REG_362C_AUX_TX_P0, + 0x1 << AUX_NO_LENGTH_AUX_TX_P0_FLDMASK_POS, + AUX_NO_LENGTH_AUX_TX_P0_FLDMASK); + + mtk_dp_mask(mtk_dp, REG_3630_AUX_TX_P0, + 0x1 << AUX_TX_REQUEST_READY_AUX_TX_P0_FLDMASK_POS, + AUX_TX_REQUEST_READY_AUX_TX_P0_FLDMASK); + + while (--wait_reply_count) { + if (mtk_dp_read(mtk_dp, REG_3618_AUX_TX_P0) & + AUX_RX_FIFO_WRITE_POINTER_AUX_TX_P0_FLDMASK) { + valid_cmd = true; + break; + } + + if (mtk_dp_read(mtk_dp, REG_3618_AUX_TX_P0) & + AUX_RX_FIFO_FULL_AUX_TX_P0_FLDMASK) { + valid_cmd = true; + break; + } + + aux_irq_status = mtk_dp_read(mtk_dp, REG_3640_AUX_TX_P0) & 0xff; + + if (aux_irq_status & AUX_RX_RECV_COMPLETE_IRQ_TX_P0_FLDMASK) { + valid_cmd = true; + break; + } + + if (aux_irq_status & AUX_400US_TIMEOUT_IRQ_AUX_TX_P0_FLDMASK) { + printk(BIOS_ERR, "(AUX Read)HW Timeout 400us irq\n"); + break; + } + } + + reply_cmd = mtk_dp_read(mtk_dp, REG_3624_AUX_TX_P0) & 0xf; + if (reply_cmd) + printk(BIOS_ERR, "reply_cmd(%#x), NACK or Defer\n", reply_cmd); + + if (wait_reply_count == 0x0 || reply_cmd) { + u8 phy_status = 0x0; + + phy_status = mtk_dp_read(mtk_dp, REG_3628_AUX_TX_P0); + if (phy_status != 0x1) + printk(BIOS_ERR, "Aux read: aux hang, need sw reset\n"); + + mtk_dp_mask(mtk_dp, REG_3650_AUX_TX_P0, + 0x1 << MCU_ACK_TRAN_COMPLETE_AUX_TX_P0_FLDMASK_POS, + MCU_ACK_TRANSACTION_COMPLETE_AUX_TX_P0_FLDMASK); + DP_WRITE1BYTE(mtk_dp, REG_3640_AUX_TX_P0, 0x7f); + + mdelay(1); + printk(BIOS_ERR, "wait_reply_count(%#x), TimeOut\n", wait_reply_count); + return false; + } + + if (length == 0) { + DP_WRITE1BYTE(mtk_dp, REG_362C_AUX_TX_P0, 0x0); + } else { + if (valid_cmd) { + mtk_dp_mask(mtk_dp, REG_3620_AUX_TX_P0, + 0x0 << AUX_RD_MODE_AUX_TX_P0_FLDMASK_POS, + AUX_RD_MODE_AUX_TX_P0_FLDMASK); + + for (rd_count = 0; rd_count < length; rd_count++) { + mtk_dp_mask(mtk_dp, REG_3620_AUX_TX_P0, + 0x1 << AUX_RX_FIFO_R_PULSE_TX_P0_FLDMASK_POS, + AUX_RX_FIFO_READ_PULSE_TX_P0_FLDMASK); + mdelay(1); + *(rx_buf + rd_count) = mtk_dp_read(mtk_dp, REG_3620_AUX_TX_P0); + } + } else { + printk(BIOS_INFO, "Read TimeOut %#x\n", dpcd_addr); + } + } + + mtk_dp_mask(mtk_dp, REG_3650_AUX_TX_P0, + 0x1 << MCU_ACK_TRAN_COMPLETE_AUX_TX_P0_FLDMASK_POS, + MCU_ACK_TRANSACTION_COMPLETE_AUX_TX_P0_FLDMASK); + DP_WRITE1BYTE(mtk_dp, REG_3640_AUX_TX_P0, 0x7f); + + mdelay(1); + return valid_cmd; +} + +bool dptx_hal_auxwrite_bytes(struct mtk_dp *mtk_dp, u8 cmd, u32 dpcd_addr, size_t length, + u8 *data) +{ + bool valid_cmd = false; + u8 reply_cmd; + int i; + u16 wait_reply_count = AUX_WAITREPLY_LPNUM; + int reg_idx; + + mtk_dp_write_byte(mtk_dp, REG_3704_AUX_TX_P0, + 1 << AUX_TX_FIFO_NEW_MODE_EN_AUX_TX_P0_FLDMASK_POS, + AUX_TX_FIFO_NEW_MODE_EN_AUX_TX_P0_FLDMASK); + DP_WRITE1BYTE(mtk_dp, REG_3650_AUX_TX_P0 + 1, 0x1); + DP_WRITE1BYTE(mtk_dp, REG_3640_AUX_TX_P0, 0x7f); + mdelay(1); + + DP_WRITE1BYTE(mtk_dp, REG_3650_AUX_TX_P0 + 1, 0x1); + DP_WRITE1BYTE(mtk_dp, REG_3644_AUX_TX_P0, cmd); + DP_WRITE1BYTE(mtk_dp, REG_3648_AUX_TX_P0, dpcd_addr & 0xff); + DP_WRITE1BYTE(mtk_dp, REG_3648_AUX_TX_P0 + 1, (dpcd_addr >> 8) & 0xff); + DP_WRITE1BYTE(mtk_dp, REG_364C_AUX_TX_P0, (dpcd_addr >> 16) & 0xf); + + if (length > 0) { + DP_WRITE1BYTE(mtk_dp, REG_362C_AUX_TX_P0, 0x0); + for (i = 0; i < (length + 1) / 2; i++) + for (reg_idx = 0; reg_idx < 2; reg_idx++) + if ((i * 2 + reg_idx) < length) + DP_WRITE1BYTE(mtk_dp, + REG_3708_AUX_TX_P0 + i * 4 + reg_idx, + data[i * 2 + reg_idx]); + DP_WRITE1BYTE(mtk_dp, REG_3650_AUX_TX_P0 + 1, ((length - 1) & 0xf) << 4); + } else { + DP_WRITE1BYTE(mtk_dp, REG_362C_AUX_TX_P0, 0x1); + } + + mtk_dp_write_byte(mtk_dp, REG_3704_AUX_TX_P0, + AUX_TX_FIFO_WRITE_DATA_NEW_MODE_TOGGLE_AUX_TX_P0_FLDMASK, + AUX_TX_FIFO_WRITE_DATA_NEW_MODE_TOGGLE_AUX_TX_P0_FLDMASK); + DP_WRITE1BYTE(mtk_dp, REG_3630_AUX_TX_P0, 0x8); + + while (--wait_reply_count) { + u8 aux_irq_status; + + aux_irq_status = mtk_dp_read(mtk_dp, REG_3640_AUX_TX_P0) & 0xff; + mdelay(1); + if (aux_irq_status & AUX_RX_RECV_COMPLETE_IRQ_TX_P0_FLDMASK) { + valid_cmd = true; + break; + } + + if (aux_irq_status & AUX_400US_TIMEOUT_IRQ_AUX_TX_P0_FLDMASK) + break; + } + + reply_cmd = mtk_dp_read(mtk_dp, REG_3624_AUX_TX_P0) & 0xf; + if (reply_cmd) + printk(BIOS_ERR, "reply_cmd(%#x), NACK or Defer\n", reply_cmd); + + if (wait_reply_count == 0x0 || reply_cmd) { + u8 phy_status = 0x0; + + phy_status = mtk_dp_read(mtk_dp, REG_3628_AUX_TX_P0); + if (phy_status != 0x1) + printk(BIOS_ERR, "Aux write: aux hang, need SW reset!\n"); + + DP_WRITE1BYTE(mtk_dp, REG_3650_AUX_TX_P0 + 1, 0x1); + DP_WRITE1BYTE(mtk_dp, REG_3640_AUX_TX_P0, 0x7f); + + mdelay(1); + + printk(BIOS_INFO, "reply_cmd(%#x), wait_reply_count(%d)\n", reply_cmd, + wait_reply_count); + return false; + } + + DP_WRITE1BYTE(mtk_dp, REG_3650_AUX_TX_P0 + 1, 0x1); + + if (length == 0) + DP_WRITE1BYTE(mtk_dp, REG_362C_AUX_TX_P0, 0x0); + + DP_WRITE1BYTE(mtk_dp, REG_3640_AUX_TX_P0, 0x7f); + + mdelay(1); + + return valid_cmd; +} + +void dptx_hal_hpd_int_en(struct mtk_dp *mtk_dp, bool enable) +{ + /* [7]:int, [6]:Con, [5]DisCon, [4]No-Use: UnMASK HPD Port */ + mtk_dp_write_byte(mtk_dp, REG_3418_DP_TRANS_P0, enable ? 0 : GENMASK(7, 5), + GENMASK(7, 5)); +} + +void dptx_hal_set_txtrainingpattern(struct mtk_dp *mtk_dp, int value) +{ + /* if Set TPS1. */ + if (value == BIT(4)) + dptx_hal_phy_setidlepattern(mtk_dp, false); + + mtk_dp_write_byte(mtk_dp, REG_3400_DP_TRANS_P0 + 1, value, GENMASK(7, 4)); +} + +void dptx_hal_phy_setidlepattern(struct mtk_dp *mtk_dp, bool enable) +{ + mtk_dp_write_byte(mtk_dp, REG_3580_DP_TRANS_P0 + 1, + enable ? 0xf : 0x0, 0xf); +} + +void dptx_hal_set_ef_mode(struct mtk_dp *mtk_dp, bool enable) +{ + /* + * [4]: REG_enhanced_frame_mode + * [1 : 0]: REG_lane_num + */ + if (enable) + mtk_dp_write_byte(mtk_dp, REG_3000_DP_ENCODER0_P0, BIT(4), BIT(4)); + else + mtk_dp_write_byte(mtk_dp, REG_3000_DP_ENCODER0_P0, 0, BIT(4)); +} + +void dptx_hal_setscramble(struct mtk_dp *mtk_dp, bool enable) +{ + /* [0]: dp tx transmitter scramble enable. */ + if (enable) + mtk_dp_write_byte(mtk_dp, REG_3404_DP_TRANS_P0, BIT(0), BIT(0)); + else + mtk_dp_write_byte(mtk_dp, REG_3404_DP_TRANS_P0, 0, BIT(0)); +} + +void dptx_hal_videomute(struct mtk_dp *mtk_dp, bool enable) +{ + if (enable) { + mtk_dp_write_byte(mtk_dp, REG_3000_DP_ENCODER0_P0, BIT(3) | BIT(2), + BIT(3) | BIT(2)); + mtk_dp_write_byte(mtk_dp, DP_TX_SECURE_REG11, BIT(3) | BIT(4), BIT(3) | BIT(4)); + } else { + mtk_dp_write_byte(mtk_dp, REG_3000_DP_ENCODER0_P0, BIT(3), BIT(3) | BIT(2)); + mtk_dp_write_byte(mtk_dp, DP_TX_SECURE_REG11, BIT(4), BIT(3) | BIT(4)); + } + printk(BIOS_DEBUG, "mute = %#x\n", read32(mtk_dp->regs + 0x402c)); +} + +void dptx_hal_analog_power_en(struct mtk_dp *mtk_dp, bool enable) +{ + if (enable) { + mtk_dp_write_byte(mtk_dp, DP_TX_TOP_RESET_AND_PROBE, 0, BIT(4)); + mdelay(1); + mtk_dp_write_byte(mtk_dp, DP_TX_TOP_RESET_AND_PROBE, BIT(4), BIT(4)); + } else { + DP_WRITE2BYTE(mtk_dp, TOP_OFFSET, 0x0); + mdelay(1); + DP_WRITE2BYTE(mtk_dp, 0x0034, 0x4aa); + DP_WRITE2BYTE(mtk_dp, 0x1040, 0x0); + DP_WRITE2BYTE(mtk_dp, 0x0038, 0x555); + } +} diff --git a/src/soc/mediatek/mt8188/Makefile.mk b/src/soc/mediatek/mt8188/Makefile.mk index c09317e..2f1a0f5 100644 --- a/src/soc/mediatek/mt8188/Makefile.mk +++ b/src/soc/mediatek/mt8188/Makefile.mk @@ -39,7 +39,7 @@ ramstage-y += ../common/devapc.c devapc.c ramstage-y += ../common/dfd.c ramstage-y += ../common/display.c -ramstage-y += ../common/dp/dptx_common.c +ramstage-y += ../common/dp/dptx_common.c ../common/dp/dptx_hal_common.c ramstage-y += ../common/dp/dp_intf.c ../common/dp/dptx.c ../common/dp/dptx_hal.c dp_intf.c ramstage-y += ../common/dpm_v1.c ramstage-$(CONFIG_DPM_FOUR_CHANNEL) += ../common/dpm_4ch.c diff --git a/src/soc/mediatek/mt8195/Makefile.mk b/src/soc/mediatek/mt8195/Makefile.mk index 85e261e..7c3d3f4 100644 --- a/src/soc/mediatek/mt8195/Makefile.mk +++ b/src/soc/mediatek/mt8195/Makefile.mk @@ -50,7 +50,7 @@ ramstage-y += ../common/display.c ramstage-y += ../common/dpm_v1.c ramstage-$(CONFIG_DPM_FOUR_CHANNEL) += ../common/dpm_4ch.c -ramstage-y += ../common/dp/dptx_common.c +ramstage-y += ../common/dp/dptx_common.c ../common/dp/dptx_hal_common.c ramstage-y += ../common/dp/dp_intf.c ../common/dp/dptx.c ../common/dp/dptx_hal.c dp_intf.c ramstage-y += emi.c ramstage-y += hdmi.c -- To view, visit https://review.coreboot.org/c/coreboot/+/85861?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9e151bc766c312eaf81b4220782775ef1c9d2297 Gerrit-Change-Number: 85861 Gerrit-PatchSet: 9 Gerrit-Owner: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jarried Lin <jarried.lin(a)mediatek.com>

1 0

[XS] Change in coreboot[main]: intel/common/rtd3: Allow emitting PSD0 Method for PCH Root Ports
by Subrata Banik (Code Review) 11 Jan '25

11 Jan '25

Attention is currently required from: Matt DeVillier, Sean Rhodes. Subrata Banik has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/85696?usp=email ) Change subject: intel/common/rtd3: Allow emitting PSD0 Method for PCH Root Ports ...................................................................... Patch Set 7: (1 comment) File src/soc/intel/common/block/pcie/rtd3/rtd3.c: https://review.coreboot.org/c/coreboot/+/85696/comment/2101ce50_88e81f0c?us… : PS5, Line 437: if (rp_type != PCIE_RP_PCH) { > Modphy gatting is supported only for PCIe root port under PCH in rtd3.c. The CPU PCIe root ports in older archecture like Tiger Lake Alder lake do not have this support. However, In the recent SoC architecture, all PCIe Root ports in PCD (i.e. PCIE_RP_PCH) and therefore, modPHY gating is supported for all RP ports. Please see src/soc/intel/common/block/pcie/rtd3/chip.h for the comments regarding of ext_pm_support. Thanks Cliff for taking look into this. We should introduce a newer Kconfig for CPU RPs to enable this feature and let applicable SoC to select that Kconfig (rather enabling RTD3 control for CPU Rps like what this CL initially attempted) -- To view, visit https://review.coreboot.org/c/coreboot/+/85696?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia34cc1f9099ca88fa16a83174ec90ca14f43ab56 Gerrit-Change-Number: 85696 Gerrit-PatchSet: 7 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Comment-Date: Sat, 11 Jan 2025 03:08:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Cliff Huang <cliff.huang(a)intel.com> Comment-In-Reply-To: Sean Rhodes <sean(a)starlabs.systems> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com>

1 0

[L] Change in coreboot[main]: mb/starlabs/starbook: Put options in CFR cbtable
by Matt DeVillier (Code Review) 11 Jan '25

11 Jan '25

Attention is currently required from: Angel Pons, Christian Walter, Sean Rhodes. Matt DeVillier has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/74743?usp=email ) Change subject: mb/starlabs/starbook: Put options in CFR cbtable ...................................................................... Patch Set 35: (1 comment) File src/mainboard/starlabs/starbook/cfr.c: https://review.coreboot.org/c/coreboot/+/74743/comment/e097e8df_d9c31aab?us… : PS35, Line 380: void lb_board(struct lb_header *header) : { : char *current = (char *)lb_new_record(header); : struct lb_cfr *cfr_root = (struct lb_cfr *)current; : : cfr_write_setup_menu(cfr_root, sm_root); : } : should be: ``` void mb_cfr_setup_menu(struct lb_cfr *cfr_root) { cfr_write_setup_menu(cfr_root, sm_root); } ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/74743?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I816893e5c2663ed55ae9fa5dd662489b27332aa6 Gerrit-Change-Number: 74743 Gerrit-PatchSet: 35 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Lean Sheng Tan <tanleansheng(a)outlook.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Sat, 11 Jan 2025 02:24:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

1 0

[L] Change in coreboot[main]: \mb/starlabs/starfighter: Put options in CFR cbtable
by Matt DeVillier (Code Review) 11 Jan '25

11 Jan '25

Attention is currently required from: Sean Rhodes. Matt DeVillier has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/85709?usp=email ) Change subject: \mb/starlabs/starfighter: Put options in CFR cbtable ...................................................................... Patch Set 7: (1 comment) File src/mainboard/starlabs/starfighter/cfr.c: https://review.coreboot.org/c/coreboot/+/85709/comment/b919acb8_b71e0f0f?us… : PS7, Line 323: void lb_board(struct lb_header *header) : { : char *current = (char *)lb_new_record(header); : struct lb_cfr *cfr_root = (struct lb_cfr *)current; : : cfr_write_setup_menu(cfr_root, sm_root); : } should be: ``` void mb_cfr_setup_menu(struct lb_cfr *cfr_root) { cfr_write_setup_menu(cfr_root, sm_root); } ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/85709?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3e3b5448282aa81a89356f1d3145381d65e47aaa Gerrit-Change-Number: 85709 Gerrit-PatchSet: 7 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Comment-Date: Sat, 11 Jan 2025 02:24:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

1 0

[L] Change in coreboot[main]: mb/starlabs/byte_adl: Put options in CFR cbtable
by Matt DeVillier (Code Review) 11 Jan '25

11 Jan '25

Attention is currently required from: Sean Rhodes. Matt DeVillier has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/85710?usp=email ) Change subject: mb/starlabs/byte_adl: Put options in CFR cbtable ...................................................................... Patch Set 7: (1 comment) File src/mainboard/starlabs/byte_adl/cfr.c: https://review.coreboot.org/c/coreboot/+/85710/comment/8cf5ca78_50725170?us… : PS7, Line 211: void lb_board(struct lb_header *header) : { : char *current = (char *)lb_new_record(header); : struct lb_cfr *cfr_root = (struct lb_cfr *)current; : : cfr_write_setup_menu(cfr_root, sm_root); : } should be: ``` void mb_cfr_setup_menu(struct lb_cfr *cfr_root) { cfr_write_setup_menu(cfr_root, sm_root); } ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/85710?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I11349397e41fb2c7a3f26ab172a2c4b30d24bc0a Gerrit-Change-Number: 85710 Gerrit-PatchSet: 7 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Comment-Date: Sat, 11 Jan 2025 02:23:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

1 0

[L] Change in coreboot[main]: mb/starlabs/starlite_adl: Put options in CFR cbtable
by Matt DeVillier (Code Review) 11 Jan '25

11 Jan '25

Attention is currently required from: Sean Rhodes. Matt DeVillier has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/85711?usp=email ) Change subject: mb/starlabs/starlite_adl: Put options in CFR cbtable ...................................................................... Patch Set 7: (1 comment) File src/mainboard/starlabs/starlite_adl/cfr.c: https://review.coreboot.org/c/coreboot/+/85711/comment/1a8db85a_af5c0e2b?us… : PS7, Line 320: void lb_board(struct lb_header *header) : { : char *current = (char *)lb_new_record(header); : struct lb_cfr *cfr_root = (struct lb_cfr *)current; : : cfr_write_setup_menu(cfr_root, sm_root); : } should be: ``` void mb_cfr_setup_menu(struct lb_cfr *cfr_root) { cfr_write_setup_menu(cfr_root, sm_root); } ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/85711?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If92f61dece7e67bfd2e29927198c9ebb81c4d363 Gerrit-Change-Number: 85711 Gerrit-PatchSet: 7 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Comment-Date: Sat, 11 Jan 2025 02:23:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

1 0

[S] Change in coreboot[main]: util/chromeos/crosfirmware: Add special handling for REEF board
by Matt DeVillier (Code Review) 11 Jan '25

11 Jan '25

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85873?usp=email ) Change subject: util/chromeos/crosfirmware: Add special handling for REEF board ...................................................................... util/chromeos/crosfirmware: Add special handling for REEF board The layout of an extracted REEF shellball doesn't conform to the usual ones used by other boards, so add a special-case handler for it. TEST= run `bash croshfirmware.sh reef` and receive the correct firmware image for the board. Change-Id: Ib391f30a77b6aa75aa130ffb525e6e1d1239a588 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85873 Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M util/chromeos/crosfirmware.sh 1 file changed, 8 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Felix Singer: Looks good to me, approved diff --git a/util/chromeos/crosfirmware.sh b/util/chromeos/crosfirmware.sh index ee87329..1972aec 100755 --- a/util/chromeos/crosfirmware.sh +++ b/util/chromeos/crosfirmware.sh @@ -105,8 +105,14 @@ _version=$(cat $_unpacked/VERSION | grep -m 1 -e Model.*$_board -A5 | grep "BIOS version:" | cut -f2 -d: | tr -d \ ) fi - _bios_image=$(grep "IMAGE_MAIN" $_unpacked/models/$_board/setvars.sh | - cut -f2 -d\") + if [ -f $_unpacked/models/$_board/setvars.sh ]; then + _bios_image=$(grep "IMAGE_MAIN" $_unpacked/models/$_board/setvars.sh | + cut -f2 -d'"') + else + # special case for REEF, others? + _version=$(grep -m1 "host" "$_unpacked/manifest.json" | cut -f12 -d'"') + _bios_image=$(grep -m1 "image" "$_unpacked/manifest.json" | cut -f4 -d'"') + fi elif [ -f "$_unpacked/manifest.json" ]; then _version=$(grep -m1 -A1 "$BOARD" "$_unpacked/manifest.json" | grep "host" | cut -f12 -d'"') _bios_image=$(grep -m1 -A3 "$BOARD" "$_unpacked/manifest.json" | grep "image" | cut -f4 -d'"') -- To view, visit https://review.coreboot.org/c/coreboot/+/85873?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib391f30a77b6aa75aa130ffb525e6e1d1239a588 Gerrit-Change-Number: 85873 Gerrit-PatchSet: 4 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit January 2025